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Update NetStar board

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Patch by Ladislav Michl, 03 Nov 2005
This commit is contained in:
Wolfgang Denk 2006-07-21 11:38:33 +02:00
parent 029b6dc77c
commit 87a5c73d66
7 changed files with 103 additions and 41 deletions
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3
CHANGELOG
View file

@ -2,6 +2,9 @@
Changes since U-Boot 1.1.4: Changes since U-Boot 1.1.4:
====================================================================== ======================================================================
* Update NetStar board
Patch by Ladislav Michl, 03 Nov 2005
* Make code better readable. * Make code better readable.
Patch by Ladislav Michl, 14 Sep 2005 Patch by Ladislav Michl, 14 Sep 2005

80
board/netstar/crcek.S
View file

@ -13,6 +13,7 @@
* u32 - crc32 * u32 - crc32
*/ */
#include <config.h>
#include "crcek.h" #include "crcek.h"
/** /**
@ -39,7 +40,7 @@
.macro crcuj, offset, size .macro crcuj, offset, size
mov r0, #0 mov r0, #0
ldr r1, \offset ldr r1, \offset
ldr r2, [r1] ldr r2, [r1], #4
cmp r2, r0 @ no data, no problem cmp r2, r0 @ no data, no problem
beq 2f beq 2f
tst r2, #3 @ unaligned size tst r2, #3 @ unaligned size
@ -47,7 +48,6 @@
ldr r3, \size ldr r3, \size
cmp r2, r3 @ bogus size cmp r2, r3 @ bogus size
bhi 2f bhi 2f
add r1, r1, #4
do_crc32 do_crc32
ldr r1, [r1] ldr r1, [r1]
2: 2:
@ -55,16 +55,71 @@
.endm .endm
.macro wait, reg .macro wait, reg
mov \reg, #0x1000 mov \reg, #0x100000
3: 3:
subs \reg, \reg, #0x1 subs \reg, \reg, #0x1
bne 3b bne 3b
.endm .endm
.text .text
.globl crcek .globl crcek
crcek: crcek:
b crc2_bad /* Enable I-cache */
mrc p15, 0, r1, c0, c0, 0 @ read C15 ID register
mrc p15, 0, r1, c0, c0, 1 @ read C15 Cache information register
mrc p15, 0, r1, c1, c0, 0 @ read C15 Control register
orr r1, r1, #0x1000 @ enable I-cache, map interrupt vector 0xffff0000
mcr p15, 0, r1, c1, c0, 0 @ write C15 Control register
mov r1, #0x00
mcr p15, 0, r1, c7, c5, 0 @ Flush I-cache
nop
nop
nop
nop
/* Setup clocking mode */
ldr r0, MPU_CLKM_BASE @ base of CLOCK unit
ldrh r1, [r0, #0x18] @ ARM_SYST - get reset status
bic r1, r1, #(7 << 11) @ clear clock select
orr r1, r1, #(2 << 11) @ set synchronous scalable
mov r2, #0
loop:
cmp r2, #1 @ this loop will wait for at least 100 cycles
streqh r1, [r0, #0x18] @ before issuing next request from MPU
add r2, r2, #1 @ on the 1st run code is loaded into I-cache
cmp r2, #16 @ and second run will set clocking mode
bne loop
nop
/* Setup clock dividers */
ldr r1, CKCTL_VAL
orr r1, r1, #0x2000 @ enable DSP clock
strh r1, [r0] @ setup clock divisors
/* Setup DPLL to generate requested freq */
ldr r0, DPLL1_BASE @ base of DPLL1 register
mov r1, #0x0010 @ set PLL_ENABLE
orr r1, r1, #0x2000 @ set IOB to new locking
orr r1, r1, #(OMAP5910_DPLL_MUL << 7) @ setup multiplier CLKREF
orr r1, r1, #(OMAP5910_DPLL_DIV << 5) @ setup divider CLKREF
strh r1, [r0] @ write
locking:
ldrh r1, [r0] @ get DPLL value
tst r1, #0x01
beq locking @ while LOCK not set
/* Enable clock */
ldr r0, MPU_CLKM_BASE @ base of CLOCK unit
mov r1, #(1 << 10) @ disable idle mode do not check
@ nWAKEUP pin, other remain active
strh r1, [r0, #0x04]
ldr r1, EN_CLK_VAL
strh r1, [r0, #0x08]
mov r1, #0x003f @ FLASH.RP not enabled in idle and
strh r1, [r0, #0x0c] @ max delayed ( 32 x CLKIN )
mov r6, #0 mov r6, #0
crcuj _LOADER1_OFFSET, _LOADER_SIZE crcuj _LOADER1_OFFSET, _LOADER_SIZE
bne crc1_bad bne crc1_bad
@ -76,9 +131,8 @@ crc1_bad:
crc2_bad: crc2_bad:
ldr r3, _LOADER1_OFFSET ldr r3, _LOADER1_OFFSET
ldr r4, _LOADER2_OFFSET ldr r4, _LOADER2_OFFSET
b boot_2nd teq r6, #3
tst r6, #3 bne one_is_bad @ one of them (or both) has bad crc
beq one_is_bad @ one of them (or both) has bad crc
ldr r1, [r3, #4] ldr r1, [r3, #4]
ldr r2, [r4, #4] ldr r2, [r4, #4]
cmp r1, r2 @ boot 2nd loader if versions differ cmp r1, r2 @ boot 2nd loader if versions differ
@ -90,6 +144,7 @@ one_is_bad:
tst r6, #2 tst r6, #2
bne boot_2nd bne boot_2nd
@ We are doomed, so let user know. @ We are doomed, so let user know.
hell:
ldr r0, GPIO_BASE @ configure GPIO pins ldr r0, GPIO_BASE @ configure GPIO pins
ldr r1, GPIO_DIRECTION ldr r1, GPIO_DIRECTION
strh r1, [r0, #0x08] strh r1, [r0, #0x08]
@ -171,6 +226,15 @@ CRC32_TABLE:
GPIO_BASE: GPIO_BASE:
.word 0xfffce000 .word 0xfffce000
MPU_CLKM_BASE:
.word 0xfffece00
DPLL1_BASE:
.word 0xfffecf00
CKCTL_VAL:
.word OMAP5910_ARM_CKCTL
EN_CLK_VAL:
.word OMAP5910_ARM_EN_CLK
GPIO_DIRECTION: GPIO_DIRECTION:
.word 0x0000ffe7 .word 0x0000ffe7

2
board/netstar/crcit.c
View file

@ -77,7 +77,7 @@ int main(int argc, char **argv)
} else if ((argc == 4) && (strcmp(argv[1], "-v") == 0)) { } else if ((argc == 4) && (strcmp(argv[1], "-v") == 0)) {
char *endptr, *nptr = argv[2]; char *endptr, *nptr = argv[2];
unsigned ver = strtoul(nptr, &endptr, 0); unsigned ver = strtoul(nptr, &endptr, 0);
if (nptr != '\0' && endptr == '\0') if (*nptr != '\0' && *endptr == '\0')
return doit(argv[3], ver); return doit(argv[3], ver);
} }
fprintf(stderr, "Usage: crcit [-v version] <image>\n"); fprintf(stderr, "Usage: crcit [-v version] <image>\n");

1
board/netstar/eeprom.c
View file

@ -213,3 +213,4 @@ int eeprom(int argc, char *argv[])
return 0; return 0;
} }

5
board/netstar/nand.c
View file

@ -57,10 +57,11 @@ static int netstar_nand_ready(struct mtd_info *mtd)
void board_nand_init(struct nand_chip *nand) void board_nand_init(struct nand_chip *nand)
{ {
nand->options = NAND_SAMSUNG_LP_OPTIONS; nand->options = NAND_SAMSUNG_LP_OPTIONS;
nand->eccmode = NAND_ECC_SOFT; nand->eccmode = NAND_ECC_SOFT;
nand->hwcontrol = netstar_nand_hwcontrol; nand->hwcontrol = netstar_nand_hwcontrol;
/* nand->dev_ready = netstar_nand_ready; */ /* nand->dev_ready = netstar_nand_ready; */
nand->chip_delay = 18; nand->chip_delay = 18;
} }
#endif #endif

6
board/netstar/netstar.c
View file

@ -27,7 +27,6 @@ DECLARE_GLOBAL_DATA_PTR;
int board_init(void) int board_init(void)
{ {
/* arch number of NetStar board */ /* arch number of NetStar board */
/* TODO: use define from asm/mach-types.h */
gd->bd->bi_arch_number = 692; gd->bd->bi_arch_number = 692;
/* adress of boot parameters */ /* adress of boot parameters */
@ -51,16 +50,13 @@ int dram_init(void)
return 0; return 0;
} }
extern void partition_flash(void);
int misc_init_r(void) int misc_init_r(void)
{ {
return 0; return 0;
} }
extern void nand_init(void);
int board_late_init(void) int board_late_init(void)
{ {
return 0; return 0;
} }

47
board/netstar/setup.S
View file

@ -58,10 +58,10 @@ VAL_EMIFF_SDRAM_CONFIG: .word ((0 << 0) | (0 << 1) | (3 << 2) | (0xf << 4) | (0
VAL_EMIFF_SDRAM_CONFIG: .word ((0 << 0) | (0 << 1) | (3 << 2) | (0xd << 4) | (0x246 << 8) | (0 << 24) | (0 << 26) | (0 << 27)) VAL_EMIFF_SDRAM_CONFIG: .word ((0 << 0) | (0 << 1) | (3 << 2) | (0xd << 4) | (0x246 << 8) | (0 << 24) | (0 << 26) | (0 << 27))
#endif #endif
VAL_EMIFF_SDRAM_CONFIG2: .word 0x00000003 VAL_EMIFF_SDRAM_CONFIG2: .word 0x00000003
VAL_EMIFF_MRS: .word 0x00000037 VAL_EMIFF_MRS: .word 0x00000037
/* /*
* GPIO04 - Green LED (Red LED is connected to LED Pulse Generator) * GPIO04 - Green LED (Red LED is connected to LED Pulse Generator)
* GPIO07 - LAN91C111 reset * GPIO07 - LAN91C111 reset
*/ */
@ -106,7 +106,7 @@ MUX_CONFIG_OFFSETS:
.align 1 .align 1
.byte 0x00 @ FUNC_MUX_CTRL_0 .byte 0x00 @ FUNC_MUX_CTRL_0
.byte 0x04 @ FUNC_MUX_CTRL_1 .byte 0x04 @ FUNC_MUX_CTRL_1
.byte 0x08 @ FUNC_MUX_CTRL_2 .byte 0x08 @ FUNC_MUX_CTRL_2
.byte 0x10 @ FUNC_MUX_CTRL_3 .byte 0x10 @ FUNC_MUX_CTRL_3
.byte 0x14 @ FUNC_MUX_CTRL_4 .byte 0x14 @ FUNC_MUX_CTRL_4
.byte 0x18 @ FUNC_MUX_CTRL_5 .byte 0x18 @ FUNC_MUX_CTRL_5
@ -145,25 +145,23 @@ lowlevel_init:
nop nop
/* Setup clocking mode */ /* Setup clocking mode */
ldr r0, OMAP5910_MPU_CLKM_BASE @ prepare base of CLOCK unit ldr r0, OMAP5910_MPU_CLKM_BASE @ base of CLOCK unit
ldrh r1, [r0, #0x18] @ get reset status ldrh r1, [r0, #0x18] @ ARM_SYST - get reset status
bic r1, r1, #(7 << 11) @ clear clock select bic r1, r1, #(7 << 11) @ clear clock select
orr r1, r1, #(2 << 11) @ set synchronous scalable orr r1, r1, #(2 << 11) @ set synchronous scalable
mov r2, #0 @ set wait counter to 100 clock cycles mov r2, #0
loop:
icache_loop: cmp r2, #1 @ this loop will wait for at least 100 cycles
cmp r2, #0x01 streqh r1, [r0, #0x18] @ before issuing next request from MPU
streqh r1, [r0, #0x18] add r2, r2, #1 @ on the 1st run code is loaded into I-cache
add r2, r2, #0x01 cmp r2, #16 @ and second run will set clocking mode
cmp r2, #0x10 bne loop
bne icache_loop
nop nop
/* Setup clock divisors */ /* Setup clock dividers */
ldr r0, OMAP5910_MPU_CLKM_BASE @ base of CLOCK unit
ldr r1, _OMAP5910_ARM_CKCTL ldr r1, _OMAP5910_ARM_CKCTL
orr r1, r1, #0x2000 @ enable DSP clock orr r1, r1, #0x2000 @ enable DSP clock
strh r1, [r0, #0x00] @ setup clock divisors strh r1, [r0] @ setup clock divisors
/* Setup DPLL to generate requested freq */ /* Setup DPLL to generate requested freq */
ldr r0, OMAP5910_DPLL1_BASE @ base of DPLL1 register ldr r0, OMAP5910_DPLL1_BASE @ base of DPLL1 register
@ -182,18 +180,17 @@ locking:
ldr r0, OMAP5910_MPU_CLKM_BASE @ base of CLOCK unit ldr r0, OMAP5910_MPU_CLKM_BASE @ base of CLOCK unit
mov r1, #(1 << 10) @ disable idle mode do not check mov r1, #(1 << 10) @ disable idle mode do not check
@ nWAKEUP pin, other remain active @ nWAKEUP pin, other remain active
strh r1, [r0, #0x04] strh r1, [r0, #0x04]
ldr r1, _OMAP5910_ARM_EN_CLK ldr r1, _OMAP5910_ARM_EN_CLK
strh r1, [r0, #0x08] strh r1, [r0, #0x08]
mov r1, #0x003f @ FLASH.RP not enabled in idle and mov r1, #0x003f @ FLASH.RP not enabled in idle and
@ max delayed ( 32 x CLKIN ) strh r1, [r0, #0x0c] @ max delayed ( 32 x CLKIN )
strh r1, [r0, #0x0c]
/* Configure 5910 pins functions to match our board. */ /* Configure 5910 pins functions to match our board. */
ldr r0, MUX_CONFIG_BASE ldr r0, MUX_CONFIG_BASE
adr r1, MUX_CONFIG_VALUES adr r1, MUX_CONFIG_VALUES
adr r2, MUX_CONFIG_OFFSETS adr r2, MUX_CONFIG_OFFSETS
next_mux_cfg: next_mux_cfg:
ldrb r3, [r2], #1 ldrb r3, [r2], #1
ldr r4, [r1], #4 ldr r4, [r1], #4
cmp r3, #0xff cmp r3, #0xff
@ -240,15 +237,15 @@ next_mux_cfg:
strh r1, [r0, #0x34] strh r1, [r0, #0x34]
/* Setup clock divisors */ /* Setup clock divisors */
ldr r0, OMAP5910_ULPD_PWR_MNG_BASE @ base of ULDPL DPLL1 register ldr r0, OMAP5910_ULPD_PWR_MNG_BASE @ base of ULDPL DPLL1 register
mov r1, #0x0010 @ set PLL_ENABLE mov r1, #0x0010 @ set PLL_ENABLE
orr r1, r1, #0x2000 @ set IOB to new locking orr r1, r1, #0x2000 @ set IOB to new locking
strh r1, [r0] @ write strh r1, [r0] @ write
ulocking: ulocking:
ldrh r1, [r0] @ get DPLL value ldrh r1, [r0] @ get DPLL value
tst r1, #1 tst r1, #1
beq ulocking @ while LOCK not set beq ulocking @ while LOCK not set
/* EMIF init */ /* EMIF init */
@ -257,7 +254,7 @@ ulocking:
bic r1, r1, #0x0c @ pwr down disabled, flash WP bic r1, r1, #0x0c @ pwr down disabled, flash WP
orr r1, r1, #0x01 orr r1, r1, #0x01
str r1, [r0, #0x0c] str r1, [r0, #0x0c]
ldr r1, VAL_EMIFS_CS0_CONFIG ldr r1, VAL_EMIFS_CS0_CONFIG
str r1, [r0, #0x10] @ EMIFS_CS0_CONFIG str r1, [r0, #0x10] @ EMIFS_CS0_CONFIG
ldr r1, VAL_EMIFS_CS1_CONFIG ldr r1, VAL_EMIFS_CS1_CONFIG