mirror of
https://github.com/Fishwaldo/u-boot.git
synced 2025-03-18 13:11:31 +00:00
Merge branch 'master' of git://git.denx.de/u-boot-arm
* 'master' of git://git.denx.de/u-boot-arm: ARM: Add Calxeda Highbank platform dkb: make mmc command as default enabled Marvell: dkb: add mmc support ARM: pantheon: add mmc definition davinci: remove config.mk file from the sources ARM:AM33XX: Add support for TI AM335X EVM ARM:AM33XX: Added timer support ARM:AM33XX: Add emif/ddr support ARM:AM33XX: Add clock definitions ARM:AM33XX: Added support for AM33xx omap3/emif4: fix registers definition davinci: remove obsolete macro CONFIG_EMAC_MDIO_PHY_NUM davinci: emac: add support for more than 1 PHYs davinci: emac: add new features to autonegotiate for EMAC da850evm: Move LPSC configuration to board_early_init_f() omap4_panda: Build in cmd_gpio support on panda omap: Don't use gpio_free to change direction to input mmc: omap: Allow OMAP_HSMMC[23]_BASE to be unset OMAP3: overo : Add environment variable optargs to bootargs OMAP3: overo: Move ethernet CS4 configuration to execute based on board id OMAP3: overo : Use ttyO2 instead of ttyS2. da830: add support for NAND boot mode dm36x: revert cache disable patch dm644X: revert cache disable patch devkit8000: Add malloc space omap: spl: fix build break due to changes in FAT OMAP3 SPL: Provide weak omap_rev_string omap: beagle: Use ubifs instead of jffs2 for nand boot omap: overo: Disable pull-ups on camera PCLK, HS and VS signals omap: overo: Configure mux for gpio10 SPL: Add DMA library omap3: Add interface for omap3 DMA omap3: Add DMA register accessors omap3: Add Base register for DMA arm, davinci: add missing LSPC define for MMC/SD1 U-Boot/SPL: omap4: Make ddr pre-calculated timings as default. DaVinci: correct MDSTAT.STATE mask omap4: splitting padconfs into common, 4430 and 4460 omap4: adding revision detection for 4460 ES1.1 omap4: replacing OMAP4_CONTROL with OMAP4430_CONTROL gplug: fixed build error as a result of code cleanup patch kirkwood_spi: add dummy spi_init() gpio: mvmfp: reduce include platform file ARM: orion5x: reduce dependence of including platform file serial: reduce include platform file for marvell chip ARM: kirkwood: reduce dependence of including platform file ARM: armada100: reduce dependence of including platform file ARM: pantheon: reduce dependence of including platform file Armada100: Add env storage support for Marvell gplugD Armada100: Add SPI flash support for Marvell gplugD Armada100: Add SPI support for Marvell gplugD SPI: Add SPI driver support for Marvell Armada100 dreamplug: initial board support. imx: fix coding style misc: pmic: drop old Freescale's pmic driver MX31: mx31pdk: use new pmic driver MX31: mx31ads: use new pmic driver MX31: mx31_litekit: use new pmic driver MX5: mx53evk: use new pmic driver MX5: mx51evk: use new pmic driver MX35: mx35pdk: use new pmic driver misc: pmic: addI2C support to pmic_fsl driver misc: pmic: use I2C_SET_BUS in pmic I2C MX5: efikamx/efikasb: use new pmic driver MX3: qong: use new pmic driver RTC: Switch mc13783 to generic pmic code MX5: vision2: use new pmic driver misc: pmic: Freescale PMIC switches to generic PMIC driver misc:pmic:samsung Enable PMIC driver at GONI target misc:pmic:max8998 MAX8998 support at a new PMIC driver. misc:pmic:core New generic PMIC driver mx31pdk: Remove unneeded config mx31: provide readable WEIM CS accessor MX51: vision2: Set global macros I2C: Add i2c_get/set_speed() to mxc_i2c.c ARM: Update mach-types devkit8000: Add config to enable SPL MMC boot devkit8000: protect board_mmc_init arm, post: add missing post_time_ms for arm cosmetic, post: Codingstyle cleanup arm, logbuffer: make it compileclean tegra2: Enable MMC for Seaboard tegra2: Add more pinmux functions tegra2: Rename PIN_ to PINGRP_ tegra2: Add more clock functions tegra2: Clean up board code a little tegra2: Rename CLOCK_PLL_ID to CLOCK_ID
This commit is contained in:
commit
87a5d60103
193 changed files with 9485 additions and 32117 deletions
12
MAINTAINERS
12
MAINTAINERS
|
@ -70,6 +70,10 @@ Conn Clark <clark@esteem.com>
|
|||
|
||||
ESTEEM192E MPC8xx
|
||||
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||||
Jason Cooper <u-boot@lakedaemon.net>
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||||
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||||
dreamplug ARM926EJS (Kirkwood SoC)
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||||
|
||||
Joe D'Abbraccio <ljd015@freescale.com>
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||||
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MPC837xERDB MPC837x
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||||
|
@ -215,6 +219,10 @@ Wolfgang Grandegger <wg@denx.de>
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|||
IPHASE4539 MPC8260
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||||
SCM MPC8260
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||||
|
||||
Rob Herring <rob.herring@calxeda.com>
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||||
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||||
highbank highbank
|
||||
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||||
Klaus Heydeck <heydeck@kieback-peter.de>
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||||
KUP4K MPC855
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||||
|
@ -734,6 +742,10 @@ Nagendra T S <nagendra@mistralsolutions.com>
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|||
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||||
am3517_crane ARM ARMV7 (AM35x SoC)
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||||
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||||
Chandan Nath <chandan.nath@ti.com>
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||||
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||||
am335x_evm ARM ARMV7 (AM33xx Soc)
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||||
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||||
Kyungmin Park <kyungmin.park@samsung.com>
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||||
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||||
apollon ARM1136EJS
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||||
|
|
3
Makefile
3
Makefile
|
@ -289,6 +289,9 @@ LIBS += lib/libfdt/libfdt.o
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LIBS += api/libapi.o
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LIBS += post/libpost.o
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ifeq ($(SOC),am33xx)
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LIBS += $(CPUDIR)/omap-common/libomap-common.o
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endif
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ifeq ($(SOC),omap3)
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LIBS += $(CPUDIR)/omap-common/libomap-common.o
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endif
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|
|
|
@ -25,6 +25,7 @@
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|||
#include <asm/arch/imx-regs.h>
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#include <asm/arch/clock.h>
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#include <asm/io.h>
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#include <asm/arch/sys_proto.h>
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static u32 mx31_decode_pll(u32 reg, u32 infreq)
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{
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@ -140,6 +141,16 @@ void mx31_set_pad(enum iomux_pins pin, u32 config)
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}
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void mxc_setup_weimcs(int cs, const struct mxc_weimcs *weimcs)
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{
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struct mx31_weim *weim = (struct mx31_weim *) WEIM_BASE;
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struct mx31_weim_cscr *cscr = &weim->cscr[cs];
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writel(weimcs->upper, &cscr->upper);
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writel(weimcs->lower, &cscr->lower);
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writel(weimcs->additional, &cscr->additional);
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}
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struct mx3_cpu_type mx31_cpu_type[] = {
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{ .srev = 0x00, .v = 0x10 },
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{ .srev = 0x10, .v = 0x11 },
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|
|
|
@ -43,7 +43,11 @@
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DECLARE_GLOBAL_DATA_PTR;
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/* "time" is measured in 1 / CONFIG_SYS_HZ seconds, "tick" is internal timer period */
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/*
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* "time" is measured in 1 / CONFIG_SYS_HZ seconds,
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* "tick" is internal timer period
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*/
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#ifdef CONFIG_MX31_TIMER_HIGH_PRECISION
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/* ~0.4% error - measured with stop-watch on 100s boot-delay */
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static inline unsigned long long tick_to_time(unsigned long long tick)
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|
@ -68,7 +72,8 @@ static inline unsigned long long us_to_tick(unsigned long long us)
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}
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#else
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/* ~2% error */
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#define TICK_PER_TIME ((CONFIG_MX31_CLK32 + CONFIG_SYS_HZ / 2) / CONFIG_SYS_HZ)
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#define TICK_PER_TIME ((CONFIG_MX31_CLK32 + CONFIG_SYS_HZ / 2) \
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/ CONFIG_SYS_HZ)
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#define US_PER_TICK (1000000 / CONFIG_MX31_CLK32)
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static inline unsigned long long tick_to_time(unsigned long long tick)
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|
@ -91,7 +96,7 @@ static inline unsigned long long us_to_tick(unsigned long long us)
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#endif
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/* The 32768Hz 32-bit timer overruns in 131072 seconds */
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int timer_init (void)
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int timer_init(void)
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{
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int i;
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|
@ -106,7 +111,7 @@ int timer_init (void)
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return 0;
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}
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unsigned long long get_ticks (void)
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unsigned long long get_ticks(void)
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{
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ulong now = GPTCNT; /* current tick value */
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||||
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|
@ -119,7 +124,7 @@ unsigned long long get_ticks (void)
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return gd->tbl;
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}
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ulong get_timer_masked (void)
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ulong get_timer_masked(void)
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{
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/*
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* get_ticks() returns a long long (64 bit), it wraps in
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|
@ -130,13 +135,13 @@ ulong get_timer_masked (void)
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return tick_to_time(get_ticks());
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}
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ulong get_timer (ulong base)
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ulong get_timer(ulong base)
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{
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return get_timer_masked () - base;
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return get_timer_masked() - base;
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}
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|
||||
/* delay x useconds AND preserve advance timestamp value */
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void __udelay (unsigned long usec)
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void __udelay(unsigned long usec)
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||||
{
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||||
unsigned long long tmp;
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||||
ulong tmo;
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|
@ -148,7 +153,7 @@ void __udelay (unsigned long usec)
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/*NOP*/;
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||||
}
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||||
|
||||
void reset_cpu (ulong addr)
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void reset_cpu(ulong addr)
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{
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struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE;
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wdog->wcr = WDOG_ENABLE;
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|
|
|
@ -240,7 +240,7 @@ unsigned int mxc_get_main_clock(enum mxc_main_clocks clk)
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}
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break;
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case IPG_CLK:
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ret_val = get_ipg_clk();;
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ret_val = get_ipg_clk();
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break;
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case IPG_PER_CLK:
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ret_val = get_ipg_per_clk();
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||||
|
|
|
@ -24,8 +24,8 @@
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|||
*/
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||||
#include <common.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/armada100.h>
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#include <asm/io.h>
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|
||||
#define UARTCLK14745KHZ (APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(1))
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#define SET_MRVL_ID (1<<8)
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|
|
|
@ -24,6 +24,7 @@
|
|||
*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/armada100.h>
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DECLARE_GLOBAL_DATA_PTR;
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|
|
|
@ -24,6 +24,7 @@
|
|||
*/
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#include <common.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/armada100.h>
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||||
|
||||
/*
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|
|
|
@ -39,11 +39,9 @@ int et1011c_get_link_speed(int phy_addr)
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u_int16_t data;
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||||
|
||||
if (davinci_eth_phy_read(phy_addr, MII_STATUS_REG, &data) && (data & 0x04)) {
|
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davinci_eth_phy_read(EMAC_MDIO_PHY_NUM,
|
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MII_PHY_CONFIG_REG, &data);
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davinci_eth_phy_read(phy_addr, MII_PHY_CONFIG_REG, &data);
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/* Enable 125MHz clock sourced from PHY */
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davinci_eth_phy_write(EMAC_MDIO_PHY_NUM,
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MII_PHY_CONFIG_REG,
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davinci_eth_phy_write(phy_addr, MII_PHY_CONFIG_REG,
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data | PHY_SYS_CLK_EN);
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return (1);
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}
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|
|
|
@ -45,6 +45,8 @@
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|||
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#include <config.h>
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#define MDSTAT_STATE 0x3f
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.globl lowlevel_init
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lowlevel_init:
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|
@ -268,7 +270,7 @@ checkStatClkStop:
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checkDDRStatClkStop:
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ldr r6, MDSTAT_DDR2
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ldr r7, [r6]
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and r7, r7, $0x1f
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and r7, r7, $MDSTAT_STATE
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cmp r7, $0x03
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bne checkDDRStatClkStop
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|
@ -343,7 +345,7 @@ checkStatClkStop2:
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checkDDRStatClkStop2:
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ldr r6, MDSTAT_DDR2
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ldr r7, [r6]
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and r7, r7, $0x1f
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and r7, r7, $MDSTAT_STATE
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cmp r7, $0x01
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bne checkDDRStatClkStop2
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|
@ -374,7 +376,7 @@ checkStatClkEn2:
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checkDDRStatClkEn2:
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ldr r6, MDSTAT_DDR2
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ldr r7, [r6]
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and r7, r7, $0x1f
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and r7, r7, $MDSTAT_STATE
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cmp r7, $0x03
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bne checkDDRStatClkEn2
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||||
|
|
|
@ -83,7 +83,7 @@ void lpsc_on(unsigned int id)
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while (readl(ptstat) & 0x01)
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continue;
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||||
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||||
if ((readl(mdstat) & 0x1f) == 0x03)
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if ((readl(mdstat) & PSC_MDSTAT_STATE) == 0x03)
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return; /* Already on and enabled */
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||||
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writel(readl(mdctl) | 0x03, mdctl);
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|
@ -114,7 +114,7 @@ void lpsc_on(unsigned int id)
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|||
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||||
while (readl(ptstat) & 0x01)
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||||
continue;
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||||
while ((readl(mdstat) & 0x1f) != 0x03)
|
||||
while ((readl(mdstat) & PSC_MDSTAT_STATE) != 0x03)
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||||
continue;
|
||||
}
|
||||
|
||||
|
|
0
arch/arm/cpu/arm926ejs/kirkwood/asm-offsets.s
Normal file
0
arch/arm/cpu/arm926ejs/kirkwood/asm-offsets.s
Normal file
|
@ -26,6 +26,8 @@
|
|||
#include <netdev.h>
|
||||
#include <asm/cache.h>
|
||||
#include <u-boot/md5.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/cpu.h>
|
||||
#include <asm/arch/kirkwood.h>
|
||||
#include <hush.h>
|
||||
|
||||
|
|
|
@ -24,6 +24,8 @@
|
|||
|
||||
#include <config.h>
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/cpu.h>
|
||||
#include <asm/arch/kirkwood.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
|
|
@ -10,6 +10,8 @@
|
|||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/cpu.h>
|
||||
#include <asm/arch/kirkwood.h>
|
||||
#include <asm/arch/mpp.h>
|
||||
|
||||
|
|
|
@ -22,6 +22,7 @@
|
|||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/kirkwood.h>
|
||||
|
||||
#define UBOOT_CNTR 0 /* counter to use for uboot timer */
|
||||
|
|
|
@ -39,7 +39,7 @@
|
|||
* f = 2 * f_ref * --------------------
|
||||
* pd + 1
|
||||
*/
|
||||
static unsigned int imx_decode_pll (unsigned int pll, unsigned int f_ref)
|
||||
static unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref)
|
||||
{
|
||||
unsigned int mfi = (pll >> CCM_PLL_MFI_SHIFT)
|
||||
& CCM_PLL_MFI_MASK;
|
||||
|
@ -52,57 +52,57 @@ static unsigned int imx_decode_pll (unsigned int pll, unsigned int f_ref)
|
|||
|
||||
mfi = mfi <= 5 ? 5 : mfi;
|
||||
|
||||
return lldiv (2 * (u64) f_ref * (mfi * (mfd + 1) + mfn),
|
||||
return lldiv(2 * (u64) f_ref * (mfi * (mfd + 1) + mfn),
|
||||
(mfd + 1) * (pd + 1));
|
||||
}
|
||||
|
||||
static ulong imx_get_mpllclk (void)
|
||||
static ulong imx_get_mpllclk(void)
|
||||
{
|
||||
struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
|
||||
ulong fref = 24000000;
|
||||
|
||||
return imx_decode_pll (readl (&ccm->mpctl), fref);
|
||||
return imx_decode_pll(readl(&ccm->mpctl), fref);
|
||||
}
|
||||
|
||||
ulong imx_get_armclk (void)
|
||||
ulong imx_get_armclk(void)
|
||||
{
|
||||
struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
|
||||
ulong cctl = readl (&ccm->cctl);
|
||||
ulong fref = imx_get_mpllclk ();
|
||||
ulong cctl = readl(&ccm->cctl);
|
||||
ulong fref = imx_get_mpllclk();
|
||||
ulong div;
|
||||
|
||||
if (cctl & CCM_CCTL_ARM_SRC)
|
||||
fref = lldiv ((fref * 3), 4);
|
||||
fref = lldiv((fref * 3), 4);
|
||||
|
||||
div = ((cctl >> CCM_CCTL_ARM_DIV_SHIFT)
|
||||
& CCM_CCTL_ARM_DIV_MASK) + 1;
|
||||
|
||||
return lldiv (fref, div);
|
||||
return lldiv(fref, div);
|
||||
}
|
||||
|
||||
ulong imx_get_ahbclk (void)
|
||||
ulong imx_get_ahbclk(void)
|
||||
{
|
||||
struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
|
||||
ulong cctl = readl (&ccm->cctl);
|
||||
ulong fref = imx_get_armclk ();
|
||||
ulong cctl = readl(&ccm->cctl);
|
||||
ulong fref = imx_get_armclk();
|
||||
ulong div;
|
||||
|
||||
div = ((cctl >> CCM_CCTL_AHB_DIV_SHIFT)
|
||||
& CCM_CCTL_AHB_DIV_MASK) + 1;
|
||||
|
||||
return lldiv (fref, div);
|
||||
return lldiv(fref, div);
|
||||
}
|
||||
|
||||
ulong imx_get_perclk (int clk)
|
||||
ulong imx_get_perclk(int clk)
|
||||
{
|
||||
struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
|
||||
ulong fref = imx_get_ahbclk ();
|
||||
ulong fref = imx_get_ahbclk();
|
||||
ulong div;
|
||||
|
||||
div = readl (&ccm->pcdr[CCM_PERCLK_REG (clk)]);
|
||||
div = ((div >> CCM_PERCLK_SHIFT (clk)) & CCM_PERCLK_MASK) + 1;
|
||||
div = readl(&ccm->pcdr[CCM_PERCLK_REG(clk)]);
|
||||
div = ((div >> CCM_PERCLK_SHIFT(clk)) & CCM_PERCLK_MASK) + 1;
|
||||
|
||||
return lldiv (fref, div);
|
||||
return lldiv(fref, div);
|
||||
}
|
||||
|
||||
u32 get_cpu_rev(void)
|
||||
|
@ -153,7 +153,7 @@ static char *get_reset_cause(void)
|
|||
|
||||
}
|
||||
|
||||
int print_cpuinfo (void)
|
||||
int print_cpuinfo(void)
|
||||
{
|
||||
char buf[32];
|
||||
u32 cpurev = get_cpu_rev();
|
||||
|
@ -161,22 +161,22 @@ int print_cpuinfo (void)
|
|||
printf("CPU: Freescale i.MX25 rev%d.%d%s at %s MHz\n",
|
||||
(cpurev & 0xF0) >> 4, (cpurev & 0x0F),
|
||||
((cpurev & 0x8000) ? " unknown" : ""),
|
||||
strmhz (buf, imx_get_armclk ()));
|
||||
strmhz(buf, imx_get_armclk()));
|
||||
printf("Reset cause: %s\n\n", get_reset_cause());
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
int cpu_eth_init (bd_t * bis)
|
||||
int cpu_eth_init(bd_t *bis)
|
||||
{
|
||||
#if defined(CONFIG_FEC_MXC)
|
||||
struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
|
||||
ulong val;
|
||||
|
||||
val = readl (&ccm->cgr0);
|
||||
val = readl(&ccm->cgr0);
|
||||
val |= (1 << 23);
|
||||
writel (val, &ccm->cgr0);
|
||||
return fecmxc_initialize (bis);
|
||||
writel(val, &ccm->cgr0);
|
||||
return fecmxc_initialize(bis);
|
||||
#else
|
||||
return 0;
|
||||
#endif
|
||||
|
@ -186,10 +186,10 @@ int cpu_eth_init (bd_t * bis)
|
|||
* Initializes on-chip MMC controllers.
|
||||
* to override, implement board_mmc_init()
|
||||
*/
|
||||
int cpu_mmc_init (bd_t * bis)
|
||||
int cpu_mmc_init(bd_t *bis)
|
||||
{
|
||||
#ifdef CONFIG_MXC_MMC
|
||||
return mxc_mmc_init (bis);
|
||||
return mxc_mmc_init(bis);
|
||||
#else
|
||||
return 0;
|
||||
#endif
|
||||
|
@ -206,7 +206,7 @@ void mx25_uart1_init_pins(void)
|
|||
|
||||
muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE;
|
||||
padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE;
|
||||
muxmode0 = MX25_PIN_MUX_MODE (0);
|
||||
muxmode0 = MX25_PIN_MUX_MODE(0);
|
||||
/*
|
||||
* set up input pins with hysteresis and 100K pull-ups
|
||||
*/
|
||||
|
@ -227,25 +227,25 @@ void mx25_uart1_init_pins(void)
|
|||
|
||||
/* UART1 */
|
||||
/* rxd */
|
||||
writel (muxmode0, &muxctl->pad_uart1_rxd);
|
||||
writel (inpadctl, &padctl->pad_uart1_rxd);
|
||||
writel(muxmode0, &muxctl->pad_uart1_rxd);
|
||||
writel(inpadctl, &padctl->pad_uart1_rxd);
|
||||
|
||||
/* txd */
|
||||
writel (muxmode0, &muxctl->pad_uart1_txd);
|
||||
writel (outpadctl, &padctl->pad_uart1_txd);
|
||||
writel(muxmode0, &muxctl->pad_uart1_txd);
|
||||
writel(outpadctl, &padctl->pad_uart1_txd);
|
||||
|
||||
/* rts */
|
||||
writel (muxmode0, &muxctl->pad_uart1_rts);
|
||||
writel (outpadctl, &padctl->pad_uart1_rts);
|
||||
writel(muxmode0, &muxctl->pad_uart1_rts);
|
||||
writel(outpadctl, &padctl->pad_uart1_rts);
|
||||
|
||||
/* cts */
|
||||
writel (muxmode0, &muxctl->pad_uart1_cts);
|
||||
writel (inpadctl, &padctl->pad_uart1_cts);
|
||||
writel(muxmode0, &muxctl->pad_uart1_cts);
|
||||
writel(inpadctl, &padctl->pad_uart1_cts);
|
||||
}
|
||||
#endif /* CONFIG_MXC_UART */
|
||||
|
||||
#ifdef CONFIG_FEC_MXC
|
||||
void mx25_fec_init_pins (void)
|
||||
void mx25_fec_init_pins(void)
|
||||
{
|
||||
struct iomuxc_mux_ctl *muxctl;
|
||||
struct iomuxc_pad_ctl *padctl;
|
||||
|
@ -256,7 +256,7 @@ void mx25_fec_init_pins (void)
|
|||
|
||||
muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE;
|
||||
padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE;
|
||||
muxmode0 = MX25_PIN_MUX_MODE (0);
|
||||
muxmode0 = MX25_PIN_MUX_MODE(0);
|
||||
inpadctl_100kpd = MX25_PIN_PAD_CTL_HYS
|
||||
| MX25_PIN_PAD_CTL_PKE
|
||||
| MX25_PIN_PAD_CTL_PUE | MX25_PIN_PAD_CTL_100K_PD;
|
||||
|
@ -275,40 +275,40 @@ void mx25_fec_init_pins (void)
|
|||
outpadctl = MX25_PIN_PAD_CTL_PUE | MX25_PIN_PAD_CTL_100K_PD;
|
||||
|
||||
/* FEC_TX_CLK */
|
||||
writel (muxmode0, &muxctl->pad_fec_tx_clk);
|
||||
writel (inpadctl_100kpd, &padctl->pad_fec_tx_clk);
|
||||
writel(muxmode0, &muxctl->pad_fec_tx_clk);
|
||||
writel(inpadctl_100kpd, &padctl->pad_fec_tx_clk);
|
||||
|
||||
/* FEC_RX_DV */
|
||||
writel (muxmode0, &muxctl->pad_fec_rx_dv);
|
||||
writel (inpadctl_100kpd, &padctl->pad_fec_rx_dv);
|
||||
writel(muxmode0, &muxctl->pad_fec_rx_dv);
|
||||
writel(inpadctl_100kpd, &padctl->pad_fec_rx_dv);
|
||||
|
||||
/* FEC_RDATA0 */
|
||||
writel (muxmode0, &muxctl->pad_fec_rdata0);
|
||||
writel (inpadctl_100kpd, &padctl->pad_fec_rdata0);
|
||||
writel(muxmode0, &muxctl->pad_fec_rdata0);
|
||||
writel(inpadctl_100kpd, &padctl->pad_fec_rdata0);
|
||||
|
||||
/* FEC_TDATA0 */
|
||||
writel (muxmode0, &muxctl->pad_fec_tdata0);
|
||||
writel (outpadctl, &padctl->pad_fec_tdata0);
|
||||
writel(muxmode0, &muxctl->pad_fec_tdata0);
|
||||
writel(outpadctl, &padctl->pad_fec_tdata0);
|
||||
|
||||
/* FEC_TX_EN */
|
||||
writel (muxmode0, &muxctl->pad_fec_tx_en);
|
||||
writel (outpadctl, &padctl->pad_fec_tx_en);
|
||||
writel(muxmode0, &muxctl->pad_fec_tx_en);
|
||||
writel(outpadctl, &padctl->pad_fec_tx_en);
|
||||
|
||||
/* FEC_MDC */
|
||||
writel (muxmode0, &muxctl->pad_fec_mdc);
|
||||
writel (outpadctl, &padctl->pad_fec_mdc);
|
||||
writel(muxmode0, &muxctl->pad_fec_mdc);
|
||||
writel(outpadctl, &padctl->pad_fec_mdc);
|
||||
|
||||
/* FEC_MDIO */
|
||||
writel (muxmode0, &muxctl->pad_fec_mdio);
|
||||
writel (inpadctl_22kpu, &padctl->pad_fec_mdio);
|
||||
writel(muxmode0, &muxctl->pad_fec_mdio);
|
||||
writel(inpadctl_22kpu, &padctl->pad_fec_mdio);
|
||||
|
||||
/* FEC_RDATA1 */
|
||||
writel (muxmode0, &muxctl->pad_fec_rdata1);
|
||||
writel (inpadctl_100kpd, &padctl->pad_fec_rdata1);
|
||||
writel(muxmode0, &muxctl->pad_fec_rdata1);
|
||||
writel(inpadctl_100kpd, &padctl->pad_fec_rdata1);
|
||||
|
||||
/* FEC_TDATA1 */
|
||||
writel (muxmode0, &muxctl->pad_fec_tdata1);
|
||||
writel (outpadctl, &padctl->pad_fec_tdata1);
|
||||
writel(muxmode0, &muxctl->pad_fec_tdata1);
|
||||
writel(outpadctl, &padctl->pad_fec_tdata1);
|
||||
|
||||
}
|
||||
|
||||
|
|
|
@ -39,7 +39,7 @@
|
|||
/*
|
||||
* Reset the cpu by setting up the watchdog timer and let it time out
|
||||
*/
|
||||
void reset_cpu (ulong ignored)
|
||||
void reset_cpu(ulong ignored)
|
||||
{
|
||||
struct wdog_regs *regs = (struct wdog_regs *)IMX_WDT_BASE;
|
||||
/* Disable watchdog and set Time-Out field to 0 */
|
||||
|
|
|
@ -15,7 +15,7 @@
|
|||
*
|
||||
* (C) Copyright 2009 DENX Software Engineering
|
||||
* Author: John Rigby <jrigby@gmail.com>
|
||||
* Add support for MX25
|
||||
* Add support for MX25
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
|
@ -43,8 +43,8 @@
|
|||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#define timestamp gd->tbl
|
||||
#define lastinc gd->lastinc
|
||||
#define timestamp (gd->tbl)
|
||||
#define lastinc (gd->lastinc)
|
||||
|
||||
/*
|
||||
* "time" is measured in 1 / CONFIG_SYS_HZ seconds,
|
||||
|
@ -121,7 +121,7 @@ int timer_init(void)
|
|||
return 0;
|
||||
}
|
||||
|
||||
unsigned long long get_ticks (void)
|
||||
unsigned long long get_ticks(void)
|
||||
{
|
||||
struct gpt_regs *gpt = (struct gpt_regs *)IMX_GPT1_BASE;
|
||||
ulong now = readl(&gpt->counter); /* current tick value */
|
||||
|
@ -140,7 +140,7 @@ unsigned long long get_ticks (void)
|
|||
return timestamp;
|
||||
}
|
||||
|
||||
ulong get_timer_masked (void)
|
||||
ulong get_timer_masked(void)
|
||||
{
|
||||
/*
|
||||
* get_ticks() returns a long long (64 bit), it wraps in
|
||||
|
@ -151,13 +151,13 @@ ulong get_timer_masked (void)
|
|||
return tick_to_time(get_ticks());
|
||||
}
|
||||
|
||||
ulong get_timer (ulong base)
|
||||
ulong get_timer(ulong base)
|
||||
{
|
||||
return get_timer_masked () - base;
|
||||
return get_timer_masked() - base;
|
||||
}
|
||||
|
||||
/* delay x useconds AND preserve advance timstamp value */
|
||||
void __udelay (unsigned long usec)
|
||||
void __udelay(unsigned long usec)
|
||||
{
|
||||
unsigned long long tmp;
|
||||
ulong tmo;
|
||||
|
|
|
@ -39,7 +39,7 @@
|
|||
/*
|
||||
* Reset the cpu by setting up the watchdog timer and let it time out
|
||||
*/
|
||||
void reset_cpu (ulong ignored)
|
||||
void reset_cpu(ulong ignored)
|
||||
{
|
||||
struct wdog_regs *regs = (struct wdog_regs *)IMX_WDT_BASE;
|
||||
/* Disable watchdog and set Time-Out field to 0 */
|
||||
|
|
|
@ -45,8 +45,8 @@
|
|||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#define timestamp gd->tbl
|
||||
#define lastinc gd->lastinc
|
||||
#define timestamp (gd->tbl)
|
||||
#define lastinc (gd->lastinc)
|
||||
|
||||
/*
|
||||
* "time" is measured in 1 / CONFIG_SYS_HZ seconds,
|
||||
|
@ -124,7 +124,7 @@ int timer_init(void)
|
|||
return 0;
|
||||
}
|
||||
|
||||
unsigned long long get_ticks (void)
|
||||
unsigned long long get_ticks(void)
|
||||
{
|
||||
struct gpt_regs *regs = (struct gpt_regs *)IMX_TIM1_BASE;
|
||||
ulong now = readl(®s->gpt_tcn); /* current tick value */
|
||||
|
@ -143,7 +143,7 @@ unsigned long long get_ticks (void)
|
|||
return timestamp;
|
||||
}
|
||||
|
||||
ulong get_timer_masked (void)
|
||||
ulong get_timer_masked(void)
|
||||
{
|
||||
/*
|
||||
* get_ticks() returns a long long (64 bit), it wraps in
|
||||
|
@ -154,13 +154,13 @@ ulong get_timer_masked (void)
|
|||
return tick_to_time(get_ticks());
|
||||
}
|
||||
|
||||
ulong get_timer (ulong base)
|
||||
ulong get_timer(ulong base)
|
||||
{
|
||||
return get_timer_masked () - base;
|
||||
return get_timer_masked() - base;
|
||||
}
|
||||
|
||||
/* delay x useconds AND preserve advance timstamp value */
|
||||
void __udelay (unsigned long usec)
|
||||
void __udelay(unsigned long usec)
|
||||
{
|
||||
unsigned long long tmp;
|
||||
ulong tmo;
|
||||
|
|
|
@ -28,8 +28,9 @@
|
|||
#include <common.h>
|
||||
#include <netdev.h>
|
||||
#include <asm/cache.h>
|
||||
#include <asm/io.h>
|
||||
#include <u-boot/md5.h>
|
||||
#include <asm/arch/orion5x.h>
|
||||
#include <asm/arch/cpu.h>
|
||||
#include <hush.h>
|
||||
|
||||
#define BUFLEN 16
|
||||
|
|
|
@ -27,7 +27,7 @@
|
|||
|
||||
#include <common.h>
|
||||
#include <config.h>
|
||||
#include <asm/arch/orion5x.h>
|
||||
#include <asm/arch/cpu.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
|
|
|
@ -25,7 +25,7 @@
|
|||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/arch/orion5x.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
#define UBOOT_CNTR 0 /* counter to use for uboot timer */
|
||||
|
||||
|
|
|
@ -23,8 +23,8 @@
|
|||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/arch/cpu.h>
|
||||
#include <asm/arch/pantheon.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
#define UARTCLK14745KHZ (APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(1))
|
||||
#define SET_MRVL_ID (1<<8)
|
||||
|
@ -42,6 +42,9 @@ int arch_cpu_init(void)
|
|||
struct panthmpmu_registers *mpmu =
|
||||
(struct panthmpmu_registers*) PANTHEON_MPMU_BASE;
|
||||
|
||||
struct panthapmu_registers *apmu =
|
||||
(struct panthapmu_registers *) PANTHEON_APMU_BASE;
|
||||
|
||||
/* set SEL_MRVL_ID bit in PANTHEON_CPU_CONF register */
|
||||
val = readl(&cpuregs->cpu_conf);
|
||||
val = val | SET_MRVL_ID;
|
||||
|
@ -65,6 +68,14 @@ int arch_cpu_init(void)
|
|||
writel(APBC_FNCLK | APBC_APBCLK, &apbclkres->twsi);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MV_SDHCI
|
||||
/* Enable mmc clock */
|
||||
writel(APMU_PERI_CLK | APMU_AXI_CLK | APMU_PERI_RST | APMU_AXI_RST,
|
||||
&apmu->sd1);
|
||||
writel(APMU_PERI_CLK | APMU_AXI_CLK | APMU_PERI_RST | APMU_AXI_RST,
|
||||
&apmu->sd3);
|
||||
#endif
|
||||
|
||||
icache_enable();
|
||||
|
||||
return 0;
|
||||
|
|
|
@ -23,6 +23,7 @@
|
|||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/pantheon.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
|
|
@ -23,6 +23,7 @@
|
|||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/arch/cpu.h>
|
||||
#include <asm/arch/pantheon.h>
|
||||
|
||||
/*
|
||||
|
|
48
arch/arm/cpu/armv7/am33xx/Makefile
Normal file
48
arch/arm/cpu/armv7/am33xx/Makefile
Normal file
|
@ -0,0 +1,48 @@
|
|||
#
|
||||
# Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed "as is" WITHOUT ANY WARRANTY of any
|
||||
# kind, whether express or implied; without even the implied warranty
|
||||
# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
|
||||
LIB = $(obj)lib$(SOC).o
|
||||
|
||||
SOBJS := lowlevel_init.o
|
||||
|
||||
COBJS += clock.o
|
||||
COBJS += sys_info.o
|
||||
COBJS += ddr.o
|
||||
COBJS += emif4.o
|
||||
COBJS += board.o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS) $(COBJS-y) $(SOBJS))
|
||||
|
||||
all: $(obj).depend $(LIB)
|
||||
|
||||
$(LIB): $(OBJS)
|
||||
$(call cmd_link_o_target, $(OBJS))
|
||||
|
||||
clean:
|
||||
rm -f $(SOBJS) $(OBJS)
|
||||
|
||||
distclean: clean
|
||||
rm -f $(LIB) core *.bak .depend
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk
|
||||
|
||||
sinclude $(obj).depend
|
||||
|
||||
#########################################################################
|
66
arch/arm/cpu/armv7/am33xx/board.c
Normal file
66
arch/arm/cpu/armv7/am33xx/board.c
Normal file
|
@ -0,0 +1,66 @@
|
|||
/*
|
||||
* board.c
|
||||
*
|
||||
* Common board functions for AM33XX based boards
|
||||
*
|
||||
* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/arch/cpu.h>
|
||||
#include <asm/arch/hardware.h>
|
||||
#include <asm/arch/ddr_defs.h>
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
|
||||
struct timer_reg *timerreg = (struct timer_reg *)DM_TIMER2_BASE;
|
||||
|
||||
/*
|
||||
* early system init of muxing and clocks.
|
||||
*/
|
||||
void s_init(u32 in_ddr)
|
||||
{
|
||||
/* WDT1 is already running when the bootloader gets control
|
||||
* Disable it to avoid "random" resets
|
||||
*/
|
||||
writel(0xAAAA, &wdtimer->wdtwspr);
|
||||
while (readl(&wdtimer->wdtwwps) != 0x0)
|
||||
;
|
||||
writel(0x5555, &wdtimer->wdtwspr);
|
||||
while (readl(&wdtimer->wdtwwps) != 0x0)
|
||||
;
|
||||
|
||||
/* Setup the PLLs and the clocks for the peripherals */
|
||||
#ifdef CONFIG_SETUP_PLL
|
||||
pll_init();
|
||||
#endif
|
||||
if (!in_ddr)
|
||||
config_ddr();
|
||||
}
|
||||
|
||||
/* Initialize timer */
|
||||
void init_timer(void)
|
||||
{
|
||||
/* Reset the Timer */
|
||||
writel(0x2, (&timerreg->tsicrreg));
|
||||
|
||||
/* Wait until the reset is done */
|
||||
while (readl(&timerreg->tiocpcfgreg) & 1)
|
||||
;
|
||||
|
||||
/* Start the Timer */
|
||||
writel(0x1, (&timerreg->tclrreg));
|
||||
}
|
273
arch/arm/cpu/armv7/am33xx/clock.c
Normal file
273
arch/arm/cpu/armv7/am33xx/clock.c
Normal file
|
@ -0,0 +1,273 @@
|
|||
/*
|
||||
* clock.c
|
||||
*
|
||||
* clocks for AM33XX based boards
|
||||
*
|
||||
* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/arch/cpu.h>
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/hardware.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
#define PRCM_MOD_EN 0x2
|
||||
#define PRCM_FORCE_WAKEUP 0x2
|
||||
|
||||
#define PRCM_EMIF_CLK_ACTIVITY BIT(2)
|
||||
#define PRCM_L3_GCLK_ACTIVITY BIT(4)
|
||||
|
||||
#define PLL_BYPASS_MODE 0x4
|
||||
#define ST_MN_BYPASS 0x00000100
|
||||
#define ST_DPLL_CLK 0x00000001
|
||||
#define CLK_SEL_MASK 0x7ffff
|
||||
#define CLK_DIV_MASK 0x1f
|
||||
#define CLK_DIV2_MASK 0x7f
|
||||
#define CLK_SEL_SHIFT 0x8
|
||||
#define CLK_MODE_SEL 0x7
|
||||
#define CLK_MODE_MASK 0xfffffff8
|
||||
#define CLK_DIV_SEL 0xFFFFFFE0
|
||||
|
||||
|
||||
const struct cm_perpll *cmper = (struct cm_perpll *)CM_PER;
|
||||
const struct cm_wkuppll *cmwkup = (struct cm_wkuppll *)CM_WKUP;
|
||||
const struct cm_dpll *cmdpll = (struct cm_dpll *)CM_DPLL;
|
||||
|
||||
static void enable_interface_clocks(void)
|
||||
{
|
||||
/* Enable all the Interconnect Modules */
|
||||
writel(PRCM_MOD_EN, &cmper->l3clkctrl);
|
||||
while (readl(&cmper->l3clkctrl) != PRCM_MOD_EN)
|
||||
;
|
||||
|
||||
writel(PRCM_MOD_EN, &cmper->l4lsclkctrl);
|
||||
while (readl(&cmper->l4lsclkctrl) != PRCM_MOD_EN)
|
||||
;
|
||||
|
||||
writel(PRCM_MOD_EN, &cmper->l4fwclkctrl);
|
||||
while (readl(&cmper->l4fwclkctrl) != PRCM_MOD_EN)
|
||||
;
|
||||
|
||||
writel(PRCM_MOD_EN, &cmwkup->wkl4wkclkctrl);
|
||||
while (readl(&cmwkup->wkl4wkclkctrl) != PRCM_MOD_EN)
|
||||
;
|
||||
|
||||
writel(PRCM_MOD_EN, &cmper->l3instrclkctrl);
|
||||
while (readl(&cmper->l3instrclkctrl) != PRCM_MOD_EN)
|
||||
;
|
||||
|
||||
writel(PRCM_MOD_EN, &cmper->l4hsclkctrl);
|
||||
while (readl(&cmper->l4hsclkctrl) != PRCM_MOD_EN)
|
||||
;
|
||||
}
|
||||
|
||||
/*
|
||||
* Force power domain wake up transition
|
||||
* Ensure that the corresponding interface clock is active before
|
||||
* using the peripheral
|
||||
*/
|
||||
static void power_domain_wkup_transition(void)
|
||||
{
|
||||
writel(PRCM_FORCE_WAKEUP, &cmper->l3clkstctrl);
|
||||
writel(PRCM_FORCE_WAKEUP, &cmper->l4lsclkstctrl);
|
||||
writel(PRCM_FORCE_WAKEUP, &cmwkup->wkclkstctrl);
|
||||
writel(PRCM_FORCE_WAKEUP, &cmper->l4fwclkstctrl);
|
||||
writel(PRCM_FORCE_WAKEUP, &cmper->l3sclkstctrl);
|
||||
}
|
||||
|
||||
/*
|
||||
* Enable the peripheral clock for required peripherals
|
||||
*/
|
||||
static void enable_per_clocks(void)
|
||||
{
|
||||
/* Enable the control module though RBL would have done it*/
|
||||
writel(PRCM_MOD_EN, &cmwkup->wkctrlclkctrl);
|
||||
while (readl(&cmwkup->wkctrlclkctrl) != PRCM_MOD_EN)
|
||||
;
|
||||
|
||||
/* Enable the module clock */
|
||||
writel(PRCM_MOD_EN, &cmper->timer2clkctrl);
|
||||
while (readl(&cmper->timer2clkctrl) != PRCM_MOD_EN)
|
||||
;
|
||||
|
||||
/* UART0 */
|
||||
writel(PRCM_MOD_EN, &cmwkup->wkup_uart0ctrl);
|
||||
while (readl(&cmwkup->wkup_uart0ctrl) != PRCM_MOD_EN)
|
||||
;
|
||||
}
|
||||
|
||||
static void mpu_pll_config(void)
|
||||
{
|
||||
u32 clkmode, clksel, div_m2;
|
||||
|
||||
clkmode = readl(&cmwkup->clkmoddpllmpu);
|
||||
clksel = readl(&cmwkup->clkseldpllmpu);
|
||||
div_m2 = readl(&cmwkup->divm2dpllmpu);
|
||||
|
||||
/* Set the PLL to bypass Mode */
|
||||
writel(PLL_BYPASS_MODE, &cmwkup->clkmoddpllmpu);
|
||||
while (readl(&cmwkup->idlestdpllmpu) != ST_MN_BYPASS)
|
||||
;
|
||||
|
||||
clksel = clksel & (~CLK_SEL_MASK);
|
||||
clksel = clksel | ((MPUPLL_M << CLK_SEL_SHIFT) | MPUPLL_N);
|
||||
writel(clksel, &cmwkup->clkseldpllmpu);
|
||||
|
||||
div_m2 = div_m2 & ~CLK_DIV_MASK;
|
||||
div_m2 = div_m2 | MPUPLL_M2;
|
||||
writel(div_m2, &cmwkup->divm2dpllmpu);
|
||||
|
||||
clkmode = clkmode | CLK_MODE_SEL;
|
||||
writel(clkmode, &cmwkup->clkmoddpllmpu);
|
||||
|
||||
while (readl(&cmwkup->idlestdpllmpu) != ST_DPLL_CLK)
|
||||
;
|
||||
}
|
||||
|
||||
static void core_pll_config(void)
|
||||
{
|
||||
u32 clkmode, clksel, div_m4, div_m5, div_m6;
|
||||
|
||||
clkmode = readl(&cmwkup->clkmoddpllcore);
|
||||
clksel = readl(&cmwkup->clkseldpllcore);
|
||||
div_m4 = readl(&cmwkup->divm4dpllcore);
|
||||
div_m5 = readl(&cmwkup->divm5dpllcore);
|
||||
div_m6 = readl(&cmwkup->divm6dpllcore);
|
||||
|
||||
/* Set the PLL to bypass Mode */
|
||||
writel(PLL_BYPASS_MODE, &cmwkup->clkmoddpllcore);
|
||||
|
||||
while (readl(&cmwkup->idlestdpllcore) != ST_MN_BYPASS)
|
||||
;
|
||||
|
||||
clksel = clksel & (~CLK_SEL_MASK);
|
||||
clksel = clksel | ((COREPLL_M << CLK_SEL_SHIFT) | COREPLL_N);
|
||||
writel(clksel, &cmwkup->clkseldpllcore);
|
||||
|
||||
div_m4 = div_m4 & ~CLK_DIV_MASK;
|
||||
div_m4 = div_m4 | COREPLL_M4;
|
||||
writel(div_m4, &cmwkup->divm4dpllcore);
|
||||
|
||||
div_m5 = div_m5 & ~CLK_DIV_MASK;
|
||||
div_m5 = div_m5 | COREPLL_M5;
|
||||
writel(div_m5, &cmwkup->divm5dpllcore);
|
||||
|
||||
div_m6 = div_m6 & ~CLK_DIV_MASK;
|
||||
div_m6 = div_m6 | COREPLL_M6;
|
||||
writel(div_m6, &cmwkup->divm6dpllcore);
|
||||
|
||||
clkmode = clkmode | CLK_MODE_SEL;
|
||||
writel(clkmode, &cmwkup->clkmoddpllcore);
|
||||
|
||||
while (readl(&cmwkup->idlestdpllcore) != ST_DPLL_CLK)
|
||||
;
|
||||
}
|
||||
|
||||
static void per_pll_config(void)
|
||||
{
|
||||
u32 clkmode, clksel, div_m2;
|
||||
|
||||
clkmode = readl(&cmwkup->clkmoddpllper);
|
||||
clksel = readl(&cmwkup->clkseldpllper);
|
||||
div_m2 = readl(&cmwkup->divm2dpllper);
|
||||
|
||||
/* Set the PLL to bypass Mode */
|
||||
writel(PLL_BYPASS_MODE, &cmwkup->clkmoddpllper);
|
||||
|
||||
while (readl(&cmwkup->idlestdpllper) != ST_MN_BYPASS)
|
||||
;
|
||||
|
||||
clksel = clksel & (~CLK_SEL_MASK);
|
||||
clksel = clksel | ((PERPLL_M << CLK_SEL_SHIFT) | PERPLL_N);
|
||||
writel(clksel, &cmwkup->clkseldpllper);
|
||||
|
||||
div_m2 = div_m2 & ~CLK_DIV2_MASK;
|
||||
div_m2 = div_m2 | PERPLL_M2;
|
||||
writel(div_m2, &cmwkup->divm2dpllper);
|
||||
|
||||
clkmode = clkmode | CLK_MODE_SEL;
|
||||
writel(clkmode, &cmwkup->clkmoddpllper);
|
||||
|
||||
while (readl(&cmwkup->idlestdpllper) != ST_DPLL_CLK)
|
||||
;
|
||||
}
|
||||
|
||||
static void ddr_pll_config(void)
|
||||
{
|
||||
u32 clkmode, clksel, div_m2;
|
||||
|
||||
clkmode = readl(&cmwkup->clkmoddpllddr);
|
||||
clksel = readl(&cmwkup->clkseldpllddr);
|
||||
div_m2 = readl(&cmwkup->divm2dpllddr);
|
||||
|
||||
/* Set the PLL to bypass Mode */
|
||||
clkmode = (clkmode & CLK_MODE_MASK) | PLL_BYPASS_MODE;
|
||||
writel(clkmode, &cmwkup->clkmoddpllddr);
|
||||
|
||||
/* Wait till bypass mode is enabled */
|
||||
while ((readl(&cmwkup->idlestdpllddr) & ST_MN_BYPASS)
|
||||
!= ST_MN_BYPASS)
|
||||
;
|
||||
|
||||
clksel = clksel & (~CLK_SEL_MASK);
|
||||
clksel = clksel | ((DDRPLL_M << CLK_SEL_SHIFT) | DDRPLL_N);
|
||||
writel(clksel, &cmwkup->clkseldpllddr);
|
||||
|
||||
div_m2 = div_m2 & CLK_DIV_SEL;
|
||||
div_m2 = div_m2 | DDRPLL_M2;
|
||||
writel(div_m2, &cmwkup->divm2dpllddr);
|
||||
|
||||
clkmode = (clkmode & CLK_MODE_MASK) | CLK_MODE_SEL;
|
||||
writel(clkmode, &cmwkup->clkmoddpllddr);
|
||||
|
||||
/* Wait till dpll is locked */
|
||||
while ((readl(&cmwkup->idlestdpllddr) & ST_DPLL_CLK) != ST_DPLL_CLK)
|
||||
;
|
||||
}
|
||||
|
||||
void enable_emif_clocks(void)
|
||||
{
|
||||
/* Enable the EMIF_FW Functional clock */
|
||||
writel(PRCM_MOD_EN, &cmper->emiffwclkctrl);
|
||||
/* Enable EMIF0 Clock */
|
||||
writel(PRCM_MOD_EN, &cmper->emifclkctrl);
|
||||
/* Poll for emif_gclk & L3_G clock are active */
|
||||
while ((readl(&cmper->l3clkstctrl) & (PRCM_EMIF_CLK_ACTIVITY |
|
||||
PRCM_L3_GCLK_ACTIVITY)) != (PRCM_EMIF_CLK_ACTIVITY |
|
||||
PRCM_L3_GCLK_ACTIVITY))
|
||||
;
|
||||
/* Poll if module is functional */
|
||||
while ((readl(&cmper->emifclkctrl)) != PRCM_MOD_EN)
|
||||
;
|
||||
}
|
||||
|
||||
/*
|
||||
* Configure the PLL/PRCM for necessary peripherals
|
||||
*/
|
||||
void pll_init()
|
||||
{
|
||||
mpu_pll_config();
|
||||
core_pll_config();
|
||||
per_pll_config();
|
||||
ddr_pll_config();
|
||||
|
||||
/* Enable the required interconnect clocks */
|
||||
enable_interface_clocks();
|
||||
|
||||
/* Power domain wake up transition */
|
||||
power_domain_wkup_transition();
|
||||
|
||||
/* Enable the required peripherals */
|
||||
enable_per_clocks();
|
||||
}
|
147
arch/arm/cpu/armv7/am33xx/ddr.c
Normal file
147
arch/arm/cpu/armv7/am33xx/ddr.c
Normal file
|
@ -0,0 +1,147 @@
|
|||
/*
|
||||
* DDR Configuration for AM33xx devices.
|
||||
*
|
||||
* Copyright (C) 2011 Texas Instruments Incorporated -
|
||||
http://www.ti.com/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed .as is. WITHOUT ANY WARRANTY of any
|
||||
* kind, whether express or implied; without even the implied warranty
|
||||
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <asm/arch/cpu.h>
|
||||
#include <asm/arch/ddr_defs.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
/**
|
||||
* Base address for EMIF instances
|
||||
*/
|
||||
static struct emif_regs *emif_reg = {
|
||||
(struct emif_regs *)EMIF4_0_CFG_BASE};
|
||||
|
||||
/**
|
||||
* Base address for DDR instance
|
||||
*/
|
||||
static struct ddr_regs *ddr_reg[2] = {
|
||||
(struct ddr_regs *)DDR_PHY_BASE_ADDR,
|
||||
(struct ddr_regs *)DDR_PHY_BASE_ADDR2};
|
||||
|
||||
/**
|
||||
* Base address for ddr io control instances
|
||||
*/
|
||||
static struct ddr_cmdtctrl *ioctrl_reg = {
|
||||
(struct ddr_cmdtctrl *)DDR_CONTROL_BASE_ADDR};
|
||||
|
||||
/**
|
||||
* As a convention, all functions here return 0 on success
|
||||
* -1 on failure.
|
||||
*/
|
||||
|
||||
/**
|
||||
* Configure SDRAM
|
||||
*/
|
||||
int config_sdram(struct sdram_config *cfg)
|
||||
{
|
||||
writel(cfg->sdrcr, &emif_reg->sdrcr);
|
||||
writel(cfg->sdrcr2, &emif_reg->sdrcr2);
|
||||
writel(cfg->refresh, &emif_reg->sdrrcr);
|
||||
writel(cfg->refresh_sh, &emif_reg->sdrrcsr);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* Set SDRAM timings
|
||||
*/
|
||||
int set_sdram_timings(struct sdram_timing *t)
|
||||
{
|
||||
writel(t->time1, &emif_reg->sdrtim1);
|
||||
writel(t->time1_sh, &emif_reg->sdrtim1sr);
|
||||
writel(t->time2, &emif_reg->sdrtim2);
|
||||
writel(t->time2_sh, &emif_reg->sdrtim2sr);
|
||||
writel(t->time3, &emif_reg->sdrtim3);
|
||||
writel(t->time3_sh, &emif_reg->sdrtim3sr);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* Configure DDR PHY
|
||||
*/
|
||||
int config_ddr_phy(struct ddr_phy_control *p)
|
||||
{
|
||||
writel(p->reg, &emif_reg->ddrphycr);
|
||||
writel(p->reg_sh, &emif_reg->ddrphycsr);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* Configure DDR CMD control registers
|
||||
*/
|
||||
int config_cmd_ctrl(struct cmd_control *cmd)
|
||||
{
|
||||
writel(cmd->cmd0csratio, &ddr_reg[0]->cm0csratio);
|
||||
writel(cmd->cmd0csforce, &ddr_reg[0]->cm0csforce);
|
||||
writel(cmd->cmd0csdelay, &ddr_reg[0]->cm0csdelay);
|
||||
writel(cmd->cmd0dldiff, &ddr_reg[0]->cm0dldiff);
|
||||
writel(cmd->cmd0iclkout, &ddr_reg[0]->cm0iclkout);
|
||||
|
||||
writel(cmd->cmd1csratio, &ddr_reg[0]->cm1csratio);
|
||||
writel(cmd->cmd1csforce, &ddr_reg[0]->cm1csforce);
|
||||
writel(cmd->cmd1csdelay, &ddr_reg[0]->cm1csdelay);
|
||||
writel(cmd->cmd1dldiff, &ddr_reg[0]->cm1dldiff);
|
||||
writel(cmd->cmd1iclkout, &ddr_reg[0]->cm1iclkout);
|
||||
|
||||
writel(cmd->cmd2csratio, &ddr_reg[0]->cm2csratio);
|
||||
writel(cmd->cmd2csforce, &ddr_reg[0]->cm2csforce);
|
||||
writel(cmd->cmd2csdelay, &ddr_reg[0]->cm2csdelay);
|
||||
writel(cmd->cmd2dldiff, &ddr_reg[0]->cm2dldiff);
|
||||
writel(cmd->cmd2iclkout, &ddr_reg[0]->cm2iclkout);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* Configure DDR DATA registers
|
||||
*/
|
||||
int config_ddr_data(int macrono, struct ddr_data *data)
|
||||
{
|
||||
writel(data->datardsratio0, &ddr_reg[macrono]->dt0rdsratio0);
|
||||
writel(data->datardsratio1, &ddr_reg[macrono]->dt0rdsratio1);
|
||||
|
||||
writel(data->datawdsratio0, &ddr_reg[macrono]->dt0wdsratio0);
|
||||
writel(data->datawdsratio1, &ddr_reg[macrono]->dt0wdsratio1);
|
||||
|
||||
writel(data->datawiratio0, &ddr_reg[macrono]->dt0wiratio0);
|
||||
writel(data->datawiratio1, &ddr_reg[macrono]->dt0wiratio1);
|
||||
writel(data->datagiratio0, &ddr_reg[macrono]->dt0giratio0);
|
||||
writel(data->datagiratio1, &ddr_reg[macrono]->dt0giratio1);
|
||||
|
||||
writel(data->datafwsratio0, &ddr_reg[macrono]->dt0fwsratio0);
|
||||
writel(data->datafwsratio1, &ddr_reg[macrono]->dt0fwsratio1);
|
||||
|
||||
writel(data->datawrsratio0, &ddr_reg[macrono]->dt0wrsratio0);
|
||||
writel(data->datawrsratio1, &ddr_reg[macrono]->dt0wrsratio1);
|
||||
|
||||
writel(data->datadldiff0, &ddr_reg[macrono]->dt0dldiff0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int config_io_ctrl(struct ddr_ioctrl *ioctrl)
|
||||
{
|
||||
writel(ioctrl->cmd1ctl, &ioctrl_reg->cm0ioctl);
|
||||
writel(ioctrl->cmd2ctl, &ioctrl_reg->cm1ioctl);
|
||||
writel(ioctrl->cmd3ctl, &ioctrl_reg->cm2ioctl);
|
||||
writel(ioctrl->data1ctl, &ioctrl_reg->dt0ioctl);
|
||||
writel(ioctrl->data2ctl, &ioctrl_reg->dt1ioctl);
|
||||
|
||||
return 0;
|
||||
}
|
201
arch/arm/cpu/armv7/am33xx/emif4.c
Normal file
201
arch/arm/cpu/armv7/am33xx/emif4.c
Normal file
|
@ -0,0 +1,201 @@
|
|||
/*
|
||||
* emif4.c
|
||||
*
|
||||
* AM33XX emif4 configuration file
|
||||
*
|
||||
* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/arch/cpu.h>
|
||||
#include <asm/arch/ddr_defs.h>
|
||||
#include <asm/arch/hardware.h>
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
struct ddr_regs *ddrregs = (struct ddr_regs *)DDR_PHY_BASE_ADDR;
|
||||
struct vtp_reg *vtpreg = (struct vtp_reg *)VTP0_CTRL_ADDR;
|
||||
struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR;
|
||||
|
||||
|
||||
int dram_init(void)
|
||||
{
|
||||
/* dram_init must store complete ramsize in gd->ram_size */
|
||||
gd->ram_size = get_ram_size(
|
||||
(void *)CONFIG_SYS_SDRAM_BASE,
|
||||
CONFIG_MAX_RAM_BANK_SIZE);
|
||||
return 0;
|
||||
}
|
||||
|
||||
void dram_init_banksize(void)
|
||||
{
|
||||
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
|
||||
gd->bd->bi_dram[0].size = gd->ram_size;
|
||||
}
|
||||
|
||||
|
||||
#ifdef CONFIG_AM335X_CONFIG_DDR
|
||||
static void data_macro_config(int dataMacroNum)
|
||||
{
|
||||
struct ddr_data data;
|
||||
|
||||
data.datardsratio0 = ((DDR2_RD_DQS<<30)|(DDR2_RD_DQS<<20)
|
||||
|(DDR2_RD_DQS<<10)|(DDR2_RD_DQS<<0));
|
||||
data.datardsratio1 = DDR2_RD_DQS>>2;
|
||||
data.datawdsratio0 = ((DDR2_WR_DQS<<30)|(DDR2_WR_DQS<<20)
|
||||
|(DDR2_WR_DQS<<10)|(DDR2_WR_DQS<<0));
|
||||
data.datawdsratio1 = DDR2_WR_DQS>>2;
|
||||
data.datawiratio0 = ((DDR2_PHY_WRLVL<<30)|(DDR2_PHY_WRLVL<<20)
|
||||
|(DDR2_PHY_WRLVL<<10)|(DDR2_PHY_WRLVL<<0));
|
||||
data.datawiratio1 = DDR2_PHY_WRLVL>>2;
|
||||
data.datagiratio0 = ((DDR2_PHY_GATELVL<<30)|(DDR2_PHY_GATELVL<<20)
|
||||
|(DDR2_PHY_GATELVL<<10)|(DDR2_PHY_GATELVL<<0));
|
||||
data.datagiratio1 = DDR2_PHY_GATELVL>>2;
|
||||
data.datafwsratio0 = ((DDR2_PHY_FIFO_WE<<30)|(DDR2_PHY_FIFO_WE<<20)
|
||||
|(DDR2_PHY_FIFO_WE<<10)|(DDR2_PHY_FIFO_WE<<0));
|
||||
data.datafwsratio1 = DDR2_PHY_FIFO_WE>>2;
|
||||
data.datawrsratio0 = ((DDR2_PHY_WR_DATA<<30)|(DDR2_PHY_WR_DATA<<20)
|
||||
|(DDR2_PHY_WR_DATA<<10)|(DDR2_PHY_WR_DATA<<0));
|
||||
data.datawrsratio1 = DDR2_PHY_WR_DATA>>2;
|
||||
data.datadldiff0 = PHY_DLL_LOCK_DIFF;
|
||||
|
||||
config_ddr_data(dataMacroNum, &data);
|
||||
}
|
||||
|
||||
static void cmd_macro_config(void)
|
||||
{
|
||||
struct cmd_control cmd;
|
||||
|
||||
cmd.cmd0csratio = DDR2_RATIO;
|
||||
cmd.cmd0csforce = CMD_FORCE;
|
||||
cmd.cmd0csdelay = CMD_DELAY;
|
||||
cmd.cmd0dldiff = DDR2_DLL_LOCK_DIFF;
|
||||
cmd.cmd0iclkout = DDR2_INVERT_CLKOUT;
|
||||
|
||||
cmd.cmd1csratio = DDR2_RATIO;
|
||||
cmd.cmd1csforce = CMD_FORCE;
|
||||
cmd.cmd1csdelay = CMD_DELAY;
|
||||
cmd.cmd1dldiff = DDR2_DLL_LOCK_DIFF;
|
||||
cmd.cmd1iclkout = DDR2_INVERT_CLKOUT;
|
||||
|
||||
cmd.cmd2csratio = DDR2_RATIO;
|
||||
cmd.cmd2csforce = CMD_FORCE;
|
||||
cmd.cmd2csdelay = CMD_DELAY;
|
||||
cmd.cmd2dldiff = DDR2_DLL_LOCK_DIFF;
|
||||
cmd.cmd2iclkout = DDR2_INVERT_CLKOUT;
|
||||
|
||||
config_cmd_ctrl(&cmd);
|
||||
|
||||
}
|
||||
|
||||
static void config_vtp(void)
|
||||
{
|
||||
writel(readl(&vtpreg->vtp0ctrlreg) | VTP_CTRL_ENABLE,
|
||||
&vtpreg->vtp0ctrlreg);
|
||||
writel(readl(&vtpreg->vtp0ctrlreg) & (~VTP_CTRL_START_EN),
|
||||
&vtpreg->vtp0ctrlreg);
|
||||
writel(readl(&vtpreg->vtp0ctrlreg) | VTP_CTRL_START_EN,
|
||||
&vtpreg->vtp0ctrlreg);
|
||||
|
||||
/* Poll for READY */
|
||||
while ((readl(&vtpreg->vtp0ctrlreg) & VTP_CTRL_READY) !=
|
||||
VTP_CTRL_READY)
|
||||
;
|
||||
}
|
||||
|
||||
static void config_emif_ddr2(void)
|
||||
{
|
||||
int i;
|
||||
int ret;
|
||||
struct sdram_config cfg;
|
||||
struct sdram_timing tmg;
|
||||
struct ddr_phy_control phyc;
|
||||
|
||||
/*Program EMIF0 CFG Registers*/
|
||||
phyc.reg = EMIF_READ_LATENCY;
|
||||
phyc.reg_sh = EMIF_READ_LATENCY;
|
||||
phyc.reg2 = EMIF_READ_LATENCY;
|
||||
|
||||
tmg.time1 = EMIF_TIM1;
|
||||
tmg.time1_sh = EMIF_TIM1;
|
||||
tmg.time2 = EMIF_TIM2;
|
||||
tmg.time2_sh = EMIF_TIM2;
|
||||
tmg.time3 = EMIF_TIM3;
|
||||
tmg.time3_sh = EMIF_TIM3;
|
||||
|
||||
cfg.sdrcr = EMIF_SDCFG;
|
||||
cfg.sdrcr2 = EMIF_SDCFG;
|
||||
cfg.refresh = 0x00004650;
|
||||
cfg.refresh_sh = 0x00004650;
|
||||
|
||||
/* Program EMIF instance */
|
||||
ret = config_ddr_phy(&phyc);
|
||||
if (ret < 0)
|
||||
printf("Couldn't configure phyc\n");
|
||||
|
||||
ret = config_sdram(&cfg);
|
||||
if (ret < 0)
|
||||
printf("Couldn't configure SDRAM\n");
|
||||
|
||||
ret = set_sdram_timings(&tmg);
|
||||
if (ret < 0)
|
||||
printf("Couldn't configure timings\n");
|
||||
|
||||
/* Delay */
|
||||
for (i = 0; i < 5000; i++)
|
||||
;
|
||||
|
||||
cfg.refresh = EMIF_SDREF;
|
||||
cfg.refresh_sh = EMIF_SDREF;
|
||||
cfg.sdrcr = EMIF_SDCFG;
|
||||
cfg.sdrcr2 = EMIF_SDCFG;
|
||||
|
||||
ret = config_sdram(&cfg);
|
||||
if (ret < 0)
|
||||
printf("Couldn't configure SDRAM\n");
|
||||
}
|
||||
|
||||
void config_ddr(void)
|
||||
{
|
||||
int data_macro_0 = 0;
|
||||
int data_macro_1 = 1;
|
||||
struct ddr_ioctrl ioctrl;
|
||||
|
||||
enable_emif_clocks();
|
||||
|
||||
config_vtp();
|
||||
|
||||
cmd_macro_config();
|
||||
|
||||
data_macro_config(data_macro_0);
|
||||
data_macro_config(data_macro_1);
|
||||
|
||||
writel(PHY_RANK0_DELAY, &ddrregs->dt0rdelays0);
|
||||
writel(PHY_RANK0_DELAY, &ddrregs->dt1rdelays0);
|
||||
|
||||
ioctrl.cmd1ctl = DDR_IOCTRL_VALUE;
|
||||
ioctrl.cmd2ctl = DDR_IOCTRL_VALUE;
|
||||
ioctrl.cmd3ctl = DDR_IOCTRL_VALUE;
|
||||
ioctrl.data1ctl = DDR_IOCTRL_VALUE;
|
||||
ioctrl.data2ctl = DDR_IOCTRL_VALUE;
|
||||
|
||||
config_io_ctrl(&ioctrl);
|
||||
|
||||
writel(readl(&ddrctrl->ddrioctrl) & 0xefffffff, &ddrctrl->ddrioctrl);
|
||||
writel(readl(&ddrctrl->ddrckectrl) | 0x00000001, &ddrctrl->ddrckectrl);
|
||||
|
||||
config_emif_ddr2();
|
||||
}
|
||||
#endif
|
72
arch/arm/cpu/armv7/am33xx/lowlevel_init.S
Normal file
72
arch/arm/cpu/armv7/am33xx/lowlevel_init.S
Normal file
|
@ -0,0 +1,72 @@
|
|||
/*
|
||||
* lowlevel_init.S
|
||||
*
|
||||
* AM33XX low level initialization.
|
||||
*
|
||||
* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
|
||||
*
|
||||
* Initial Code by:
|
||||
* Mansoor Ahamed <mansoor.ahamed@ti.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
|
||||
* kind, whether express or implied; without even the implied warranty
|
||||
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <config.h>
|
||||
#include <asm/arch/hardware.h>
|
||||
|
||||
_mark1:
|
||||
.word mark1
|
||||
_lowlevel_init1:
|
||||
.word lowlevel_init
|
||||
_s_init_start:
|
||||
.word s_init_start
|
||||
|
||||
_TEXT_BASE:
|
||||
.word CONFIG_SYS_TEXT_BASE /* sdram load addr from config.mk */
|
||||
|
||||
/*****************************************************************************
|
||||
* lowlevel_init: - Platform low level init.
|
||||
****************************************************************************/
|
||||
.globl lowlevel_init
|
||||
lowlevel_init:
|
||||
|
||||
/* The link register is saved in ip by start.S */
|
||||
mov r6, ip
|
||||
/* check if we are already running from RAM */
|
||||
ldr r2, _lowlevel_init1
|
||||
ldr r3, _TEXT_BASE
|
||||
sub r4, r2, r3
|
||||
sub r0, pc, r4
|
||||
ldr sp, SRAM_STACK
|
||||
mark1:
|
||||
ldr r5, _mark1
|
||||
sub r5, r5, r2 /* bytes between mark1 and lowlevel_init */
|
||||
sub r0, r0, r5 /* r0 <- _start w.r.t current place of execution */
|
||||
mov r10, #0x0 /* r10 has in_ddr used by s_init() */
|
||||
|
||||
ands r0, r0, #0xC0000000
|
||||
/* MSB 2 bits <> 0 then we are in ocmc or DDR */
|
||||
cmp r0, #0x80000000
|
||||
bne s_init_start
|
||||
mov r10, #0x01
|
||||
b s_init_start
|
||||
|
||||
s_init_start:
|
||||
mov r0, r10 /* passing in_ddr in r0 */
|
||||
bl s_init
|
||||
/* back to arch calling code */
|
||||
mov pc, r6
|
||||
/* the literal pools origin */
|
||||
.ltorg
|
||||
|
||||
SRAM_STACK:
|
||||
/* Place stack at the top */
|
||||
.word LOW_LEVEL_SRAM_STACK
|
130
arch/arm/cpu/armv7/am33xx/sys_info.c
Normal file
130
arch/arm/cpu/armv7/am33xx/sys_info.c
Normal file
|
@ -0,0 +1,130 @@
|
|||
/*
|
||||
* sys_info.c
|
||||
*
|
||||
* System information functions
|
||||
*
|
||||
* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
|
||||
*
|
||||
* Derived from Beagle Board and 3430 SDP code by
|
||||
* Richard Woodruff <r-woodruff2@ti.com>
|
||||
* Syed Mohammed Khasim <khasim@ti.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <asm/arch/cpu.h>
|
||||
#include <asm/arch/clock.h>
|
||||
|
||||
struct ctrl_stat *cstat = (struct ctrl_stat *)CTRL_BASE;
|
||||
|
||||
/**
|
||||
* get_cpu_rev(void) - extract rev info
|
||||
*/
|
||||
u32 get_cpu_rev(void)
|
||||
{
|
||||
u32 id;
|
||||
u32 rev;
|
||||
|
||||
id = readl(DEVICE_ID);
|
||||
rev = (id >> 28) & 0xff;
|
||||
|
||||
return rev;
|
||||
}
|
||||
|
||||
/**
|
||||
* get_cpu_type(void) - extract cpu info
|
||||
*/
|
||||
u32 get_cpu_type(void)
|
||||
{
|
||||
u32 id = 0;
|
||||
u32 partnum;
|
||||
|
||||
id = readl(DEVICE_ID);
|
||||
partnum = (id >> 12) & 0xffff;
|
||||
|
||||
return partnum;
|
||||
}
|
||||
|
||||
/**
|
||||
* get_board_rev() - setup to pass kernel board revision information
|
||||
* returns:(bit[0-3] sub version, higher bit[7-4] is higher version)
|
||||
*/
|
||||
u32 get_board_rev(void)
|
||||
{
|
||||
return BOARD_REV_ID;
|
||||
}
|
||||
|
||||
/**
|
||||
* get_device_type(): tell if GP/HS/EMU/TST
|
||||
*/
|
||||
u32 get_device_type(void)
|
||||
{
|
||||
int mode;
|
||||
mode = readl(&cstat->statusreg) & (DEVICE_MASK);
|
||||
return mode >>= 8;
|
||||
}
|
||||
|
||||
/**
|
||||
* get_sysboot_value(void) - return SYS_BOOT[4:0]
|
||||
*/
|
||||
u32 get_sysboot_value(void)
|
||||
{
|
||||
int mode;
|
||||
mode = readl(&cstat->statusreg) & (SYSBOOT_MASK);
|
||||
return mode;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_DISPLAY_CPUINFO
|
||||
/**
|
||||
* Print CPU information
|
||||
*/
|
||||
int print_cpuinfo(void)
|
||||
{
|
||||
char *cpu_s, *sec_s;
|
||||
int arm_freq, ddr_freq;
|
||||
|
||||
switch (get_cpu_type()) {
|
||||
case AM335X:
|
||||
cpu_s = "AM335X";
|
||||
break;
|
||||
default:
|
||||
cpu_s = "Unknown cpu type";
|
||||
break;
|
||||
}
|
||||
|
||||
switch (get_device_type()) {
|
||||
case TST_DEVICE:
|
||||
sec_s = "TST";
|
||||
break;
|
||||
case EMU_DEVICE:
|
||||
sec_s = "EMU";
|
||||
break;
|
||||
case HS_DEVICE:
|
||||
sec_s = "HS";
|
||||
break;
|
||||
case GP_DEVICE:
|
||||
sec_s = "GP";
|
||||
break;
|
||||
default:
|
||||
sec_s = "?";
|
||||
}
|
||||
|
||||
printf("AM%s-%s rev %d\n",
|
||||
cpu_s, sec_s, get_cpu_rev());
|
||||
|
||||
/* TODO: Print ARM and DDR frequencies */
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif /* CONFIG_DISPLAY_CPUINFO */
|
|
@ -1,6 +1,6 @@
|
|||
#
|
||||
# (C) Copyright 2002
|
||||
# Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
|
||||
# (C) Copyright 2000-2006
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
|
@ -21,12 +21,26 @@
|
|||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float
|
||||
include $(TOPDIR)/config.mk
|
||||
|
||||
PLATFORM_CPPFLAGS += -march=armv5te
|
||||
# =========================================================================
|
||||
#
|
||||
# Supply options according to compiler version
|
||||
#
|
||||
# =========================================================================
|
||||
PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
|
||||
LIB = $(obj)lib$(SOC).o
|
||||
|
||||
COBJS := timer.o
|
||||
SOBJS :=
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
|
||||
|
||||
all: $(obj).depend $(LIB)
|
||||
|
||||
$(LIB): $(OBJS)
|
||||
$(call cmd_link_o_target, $(OBJS))
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk
|
||||
|
||||
sinclude $(obj).depend
|
||||
|
||||
#########################################################################
|
123
arch/arm/cpu/armv7/highbank/timer.c
Normal file
123
arch/arm/cpu/armv7/highbank/timer.c
Normal file
|
@ -0,0 +1,123 @@
|
|||
/*
|
||||
* Copyright 2010-2011 Calxeda, Inc.
|
||||
*
|
||||
* Based on arm926ejs/mx27/timer.c
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the Free
|
||||
* Software Foundation; either version 2 of the License, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <div64.h>
|
||||
#include <linux/types.h> /* for size_t */
|
||||
#include <linux/stddef.h> /* for NULL */
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch-armv7/systimer.h>
|
||||
|
||||
#undef SYSTIMER_BASE
|
||||
#define SYSTIMER_BASE 0xFFF34000 /* Timer 0 and 1 base */
|
||||
#define SYSTIMER_RATE 150000000
|
||||
|
||||
static ulong timestamp;
|
||||
static ulong lastinc;
|
||||
static struct systimer *systimer_base = (struct systimer *)SYSTIMER_BASE;
|
||||
|
||||
/*
|
||||
* Start the timer
|
||||
*/
|
||||
int timer_init(void)
|
||||
{
|
||||
/*
|
||||
* Setup timer0
|
||||
*/
|
||||
writel(SYSTIMER_RELOAD, &systimer_base->timer0load);
|
||||
writel(SYSTIMER_RELOAD, &systimer_base->timer0value);
|
||||
writel(SYSTIMER_EN | SYSTIMER_32BIT, &systimer_base->timer0control);
|
||||
|
||||
reset_timer_masked();
|
||||
|
||||
return 0;
|
||||
|
||||
}
|
||||
|
||||
#define TICK_PER_TIME ((SYSTIMER_RATE + CONFIG_SYS_HZ / 2) / CONFIG_SYS_HZ)
|
||||
#define NS_PER_TICK (1000000000 / SYSTIMER_RATE)
|
||||
|
||||
static inline unsigned long long tick_to_time(unsigned long long tick)
|
||||
{
|
||||
do_div(tick, TICK_PER_TIME);
|
||||
return tick;
|
||||
}
|
||||
|
||||
static inline unsigned long long time_to_tick(unsigned long long time)
|
||||
{
|
||||
return time * TICK_PER_TIME;
|
||||
}
|
||||
|
||||
static inline unsigned long long us_to_tick(unsigned long long us)
|
||||
{
|
||||
unsigned long long tick = us << 16;
|
||||
tick += NS_PER_TICK - 1;
|
||||
do_div(tick, NS_PER_TICK);
|
||||
return tick >> 16;
|
||||
}
|
||||
|
||||
unsigned long long get_ticks(void)
|
||||
{
|
||||
ulong now = ~readl(&systimer_base->timer0value);
|
||||
|
||||
if (now >= lastinc) /* normal mode (non roll) */
|
||||
/* move stamp forward with absolut diff ticks */
|
||||
timestamp += (now - lastinc);
|
||||
else /* we have rollover of incrementer */
|
||||
timestamp += (0xFFFFFFFF - lastinc) + now;
|
||||
lastinc = now;
|
||||
return timestamp;
|
||||
}
|
||||
|
||||
/*
|
||||
* Delay x useconds AND preserve advance timstamp value
|
||||
* assumes timer is ticking at 1 msec
|
||||
*/
|
||||
void __udelay(ulong usec)
|
||||
{
|
||||
unsigned long long tmp;
|
||||
ulong tmo;
|
||||
|
||||
tmo = us_to_tick(usec);
|
||||
tmp = get_ticks() + tmo; /* get current timestamp */
|
||||
|
||||
while (get_ticks() < tmp) /* loop till event */
|
||||
/*NOP*/;
|
||||
}
|
||||
|
||||
ulong get_timer(ulong base)
|
||||
{
|
||||
return get_timer_masked() - base;
|
||||
}
|
||||
|
||||
void reset_timer_masked(void)
|
||||
{
|
||||
lastinc = ~readl(&systimer_base->timer0value);
|
||||
timestamp = 0;
|
||||
}
|
||||
|
||||
void reset_timer(void)
|
||||
{
|
||||
reset_timer_masked();
|
||||
}
|
||||
|
||||
ulong get_timer_masked(void)
|
||||
{
|
||||
return tick_to_time(get_ticks());
|
||||
}
|
|
@ -26,6 +26,8 @@
|
|||
#include <common.h>
|
||||
#include <asm/arch/imx-regs.h>
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
|
||||
#include <asm/errno.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
|
@ -117,14 +119,6 @@ int print_cpuinfo(void)
|
|||
}
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Initializes on-chip ethernet controllers.
|
||||
* to override, implement board_eth_init()
|
||||
*/
|
||||
#if defined(CONFIG_FEC_MXC)
|
||||
extern int fecmxc_initialize(bd_t *bis);
|
||||
#endif
|
||||
|
||||
int cpu_eth_init(bd_t *bis)
|
||||
{
|
||||
int rc = -ENODEV;
|
||||
|
|
|
@ -29,7 +29,9 @@ SOBJS := reset.o
|
|||
|
||||
COBJS := timer.o
|
||||
COBJS += utils.o
|
||||
ifdef CONFIG_OMAP
|
||||
COBJS += gpio.o
|
||||
endif
|
||||
|
||||
ifdef CONFIG_SPL_BUILD
|
||||
COBJS += spl.o
|
||||
|
|
|
@ -237,11 +237,4 @@ int gpio_request(int gpio, const char *label)
|
|||
*/
|
||||
void gpio_free(unsigned gpio)
|
||||
{
|
||||
const struct gpio_bank *bank;
|
||||
|
||||
if (check_gpio(gpio) < 0)
|
||||
return;
|
||||
bank = get_gpio_bank(gpio);
|
||||
|
||||
_set_gpio_direction(bank, get_gpio_index(gpio), 1);
|
||||
}
|
||||
|
|
|
@ -34,6 +34,7 @@
|
|||
#include <asm/arch/mmc_host_def.h>
|
||||
#include <i2c.h>
|
||||
#include <image.h>
|
||||
#include <malloc.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
|
@ -105,6 +106,9 @@ void board_init_r(gd_t *id, ulong dummy)
|
|||
u32 boot_device;
|
||||
debug(">>spl:board_init_r()\n");
|
||||
|
||||
mem_malloc_init(CONFIG_SYS_SPL_MALLOC_START,
|
||||
CONFIG_SYS_SPL_MALLOC_SIZE);
|
||||
|
||||
timer_init();
|
||||
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
|
||||
|
||||
|
@ -160,3 +164,11 @@ void preloader_console_init(void)
|
|||
omap_rev_string(rev_string_buffer);
|
||||
printf("Texas Instruments %s\n", rev_string_buffer);
|
||||
}
|
||||
|
||||
void __omap_rev_string(char *str)
|
||||
{
|
||||
sprintf(str, "Revision detection unimplemented");
|
||||
}
|
||||
|
||||
void omap_rev_string(char *str)
|
||||
__attribute__((weak, alias("__omap_rev_string")));
|
||||
|
|
|
@ -450,9 +450,3 @@ void enable_caches(void)
|
|||
dcache_enable();
|
||||
}
|
||||
#endif
|
||||
|
||||
void omap_rev_string(char *omap_rev_string)
|
||||
{
|
||||
sprintf(omap_rev_string, "OMAP3, sorry revision detection" \
|
||||
" unimplemented");
|
||||
}
|
||||
|
|
|
@ -152,9 +152,11 @@ static void set_muxconf_regs_essential(void)
|
|||
sizeof(wkup_padconf_array_essential) /
|
||||
sizeof(struct pad_conf_entry));
|
||||
|
||||
/* gpio_wk7 is used for controlling TPS on 4460 */
|
||||
if (omap_revision() >= OMAP4460_ES1_0)
|
||||
writew(M3, CONTROL_WKUP_PAD1_FREF_CLK4_REQ);
|
||||
do_set_mux(CONTROL_PADCONF_WKUP,
|
||||
wkup_padconf_array_essential_4460,
|
||||
sizeof(wkup_padconf_array_essential_4460) /
|
||||
sizeof(struct pad_conf_entry));
|
||||
}
|
||||
|
||||
static void set_mux_conf_regs(void)
|
||||
|
@ -200,13 +202,13 @@ static void init_omap4_revision(void)
|
|||
break;
|
||||
case MIDR_CORTEX_A9_R1P2:
|
||||
switch (readl(CONTROL_ID_CODE)) {
|
||||
case OMAP4_CONTROL_ID_CODE_ES2_0:
|
||||
case OMAP4430_CONTROL_ID_CODE_ES2_0:
|
||||
*omap4_revision = OMAP4430_ES2_0;
|
||||
break;
|
||||
case OMAP4_CONTROL_ID_CODE_ES2_1:
|
||||
case OMAP4430_CONTROL_ID_CODE_ES2_1:
|
||||
*omap4_revision = OMAP4430_ES2_1;
|
||||
break;
|
||||
case OMAP4_CONTROL_ID_CODE_ES2_2:
|
||||
case OMAP4430_CONTROL_ID_CODE_ES2_2:
|
||||
*omap4_revision = OMAP4430_ES2_2;
|
||||
break;
|
||||
default:
|
||||
|
@ -218,7 +220,17 @@ static void init_omap4_revision(void)
|
|||
*omap4_revision = OMAP4430_ES2_3;
|
||||
break;
|
||||
case MIDR_CORTEX_A9_R2P10:
|
||||
*omap4_revision = OMAP4460_ES1_0;
|
||||
switch (readl(CONTROL_ID_CODE)) {
|
||||
case OMAP4460_CONTROL_ID_CODE_ES1_0:
|
||||
*omap4_revision = OMAP4460_ES1_0;
|
||||
break;
|
||||
case OMAP4460_CONTROL_ID_CODE_ES1_1:
|
||||
*omap4_revision = OMAP4460_ES1_1;
|
||||
break;
|
||||
default:
|
||||
*omap4_revision = OMAP4460_ES1_0;
|
||||
break;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
*omap4_revision = OMAP4430_SILICON_ID_INVALID;
|
||||
|
|
|
@ -73,4 +73,11 @@ const struct pad_conf_entry wkup_padconf_array_essential[] = {
|
|||
|
||||
};
|
||||
|
||||
const struct pad_conf_entry wkup_padconf_array_essential_4460[] = {
|
||||
|
||||
{PAD1_FREF_CLK4_REQ, (M3)}, /* gpio_wk7, TPS */
|
||||
|
||||
};
|
||||
|
||||
|
||||
#endif /* _OMAP4_MUX_DATA_H_ */
|
||||
|
|
|
@ -36,7 +36,7 @@ u32 s_first_boot = 1;
|
|||
void init_pllx(void)
|
||||
{
|
||||
struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
|
||||
struct clk_pll *pll = &clkrst->crc_pll[CLOCK_PLL_ID_XCPU];
|
||||
struct clk_pll *pll = &clkrst->crc_pll[CLOCK_ID_XCPU];
|
||||
u32 reg;
|
||||
|
||||
/* If PLLX is already enabled, just return */
|
||||
|
@ -189,7 +189,6 @@ static void reset_A9_cpu(int reset)
|
|||
|
||||
static void clock_enable_coresight(int enable)
|
||||
{
|
||||
struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
|
||||
u32 rst, src;
|
||||
|
||||
clock_set_enable(PERIPH_ID_CORESIGHT, enable);
|
||||
|
@ -203,7 +202,7 @@ static void clock_enable_coresight(int enable)
|
|||
* (bits 7:0), so 00000001b == 1.5 (n+1 + .5)
|
||||
*/
|
||||
src = CLK_DIVIDER(NVBL_PLLP_KHZ, 144000);
|
||||
writel(src, &clkrst->crc_clk_src_csite);
|
||||
clock_ll_set_source_divisor(PERIPH_ID_CSI, 0, src);
|
||||
|
||||
/* Unlock the CPU CoreSight interfaces */
|
||||
rst = 0xC5ACCE55;
|
||||
|
|
|
@ -27,6 +27,371 @@
|
|||
#include <asm/arch/timer.h>
|
||||
#include <asm/arch/tegra2.h>
|
||||
#include <common.h>
|
||||
#include <div64.h>
|
||||
|
||||
/*
|
||||
* This is our record of the current clock rate of each clock. We don't
|
||||
* fill all of these in since we are only really interested in clocks which
|
||||
* we use as parents.
|
||||
*/
|
||||
static unsigned pll_rate[CLOCK_ID_COUNT];
|
||||
|
||||
/*
|
||||
* The oscillator frequency is fixed to one of four set values. Based on this
|
||||
* the other clocks are set up appropriately.
|
||||
*/
|
||||
static unsigned osc_freq[CLOCK_OSC_FREQ_COUNT] = {
|
||||
13000000,
|
||||
19200000,
|
||||
12000000,
|
||||
26000000,
|
||||
};
|
||||
|
||||
/*
|
||||
* Clock types that we can use as a source. The Tegra2 has muxes for the
|
||||
* peripheral clocks, and in most cases there are four options for the clock
|
||||
* source. This gives us a clock 'type' and exploits what commonality exists
|
||||
* in the device.
|
||||
*
|
||||
* Letters are obvious, except for T which means CLK_M, and S which means the
|
||||
* clock derived from 32KHz. Beware that CLK_M (also called OSC in the
|
||||
* datasheet) and PLL_M are different things. The former is the basic
|
||||
* clock supplied to the SOC from an external oscillator. The latter is the
|
||||
* memory clock PLL.
|
||||
*
|
||||
* See definitions in clock_id in the header file.
|
||||
*/
|
||||
enum clock_type_id {
|
||||
CLOCK_TYPE_AXPT, /* PLL_A, PLL_X, PLL_P, CLK_M */
|
||||
CLOCK_TYPE_MCPA, /* and so on */
|
||||
CLOCK_TYPE_MCPT,
|
||||
CLOCK_TYPE_PCM,
|
||||
CLOCK_TYPE_PCMT,
|
||||
CLOCK_TYPE_PCXTS,
|
||||
CLOCK_TYPE_PDCT,
|
||||
|
||||
CLOCK_TYPE_COUNT,
|
||||
CLOCK_TYPE_NONE = -1, /* invalid clock type */
|
||||
};
|
||||
|
||||
/* return 1 if a peripheral ID is in range */
|
||||
#define clock_type_id_isvalid(id) ((id) >= 0 && \
|
||||
(id) < CLOCK_TYPE_COUNT)
|
||||
|
||||
char pllp_valid = 1; /* PLLP is set up correctly */
|
||||
|
||||
enum {
|
||||
CLOCK_MAX_MUX = 4 /* number of source options for each clock */
|
||||
};
|
||||
|
||||
/*
|
||||
* Clock source mux for each clock type. This just converts our enum into
|
||||
* a list of mux sources for use by the code. Note that CLOCK_TYPE_PCXTS
|
||||
* is special as it has 5 sources. Since it also has a different number of
|
||||
* bits in its register for the source, we just handle it with a special
|
||||
* case in the code.
|
||||
*/
|
||||
#define CLK(x) CLOCK_ID_ ## x
|
||||
static enum clock_id clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX] = {
|
||||
{ CLK(AUDIO), CLK(XCPU), CLK(PERIPH), CLK(OSC) },
|
||||
{ CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(AUDIO) },
|
||||
{ CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC) },
|
||||
{ CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(NONE) },
|
||||
{ CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC) },
|
||||
{ CLK(PERIPH), CLK(CGENERAL), CLK(XCPU), CLK(OSC) },
|
||||
{ CLK(PERIPH), CLK(DISPLAY), CLK(CGENERAL), CLK(OSC) },
|
||||
};
|
||||
|
||||
/*
|
||||
* Clock peripheral IDs which sadly don't match up with PERIPH_ID. This is
|
||||
* not in the header file since it is for purely internal use - we want
|
||||
* callers to use the PERIPH_ID for all access to peripheral clocks to avoid
|
||||
* confusion bewteen PERIPH_ID_... and PERIPHC_...
|
||||
*
|
||||
* We don't call this CLOCK_PERIPH_ID or PERIPH_CLOCK_ID as it would just be
|
||||
* confusing.
|
||||
*
|
||||
* Note to SOC vendors: perhaps define a unified numbering for peripherals and
|
||||
* use it for reset, clock enable, clock source/divider and even pinmuxing
|
||||
* if you can.
|
||||
*/
|
||||
enum periphc_internal_id {
|
||||
/* 0x00 */
|
||||
PERIPHC_I2S1,
|
||||
PERIPHC_I2S2,
|
||||
PERIPHC_SPDIF_OUT,
|
||||
PERIPHC_SPDIF_IN,
|
||||
PERIPHC_PWM,
|
||||
PERIPHC_SPI1,
|
||||
PERIPHC_SPI2,
|
||||
PERIPHC_SPI3,
|
||||
|
||||
/* 0x08 */
|
||||
PERIPHC_XIO,
|
||||
PERIPHC_I2C1,
|
||||
PERIPHC_DVC_I2C,
|
||||
PERIPHC_TWC,
|
||||
PERIPHC_0c,
|
||||
PERIPHC_10, /* PERIPHC_SPI1, what is this really? */
|
||||
PERIPHC_DISP1,
|
||||
PERIPHC_DISP2,
|
||||
|
||||
/* 0x10 */
|
||||
PERIPHC_CVE,
|
||||
PERIPHC_IDE0,
|
||||
PERIPHC_VI,
|
||||
PERIPHC_1c,
|
||||
PERIPHC_SDMMC1,
|
||||
PERIPHC_SDMMC2,
|
||||
PERIPHC_G3D,
|
||||
PERIPHC_G2D,
|
||||
|
||||
/* 0x18 */
|
||||
PERIPHC_NDFLASH,
|
||||
PERIPHC_SDMMC4,
|
||||
PERIPHC_VFIR,
|
||||
PERIPHC_EPP,
|
||||
PERIPHC_MPE,
|
||||
PERIPHC_MIPI,
|
||||
PERIPHC_UART1,
|
||||
PERIPHC_UART2,
|
||||
|
||||
/* 0x20 */
|
||||
PERIPHC_HOST1X,
|
||||
PERIPHC_21,
|
||||
PERIPHC_TVO,
|
||||
PERIPHC_HDMI,
|
||||
PERIPHC_24,
|
||||
PERIPHC_TVDAC,
|
||||
PERIPHC_I2C2,
|
||||
PERIPHC_EMC,
|
||||
|
||||
/* 0x28 */
|
||||
PERIPHC_UART3,
|
||||
PERIPHC_29,
|
||||
PERIPHC_VI_SENSOR,
|
||||
PERIPHC_2b,
|
||||
PERIPHC_2c,
|
||||
PERIPHC_SPI4,
|
||||
PERIPHC_I2C3,
|
||||
PERIPHC_SDMMC3,
|
||||
|
||||
/* 0x30 */
|
||||
PERIPHC_UART4,
|
||||
PERIPHC_UART5,
|
||||
PERIPHC_VDE,
|
||||
PERIPHC_OWR,
|
||||
PERIPHC_NOR,
|
||||
PERIPHC_CSITE,
|
||||
|
||||
PERIPHC_COUNT,
|
||||
|
||||
PERIPHC_NONE = -1,
|
||||
};
|
||||
|
||||
/* return 1 if a periphc_internal_id is in range */
|
||||
#define periphc_internal_id_isvalid(id) ((id) >= 0 && \
|
||||
(id) < PERIPHC_COUNT)
|
||||
|
||||
/*
|
||||
* Clock type for each peripheral clock source. We put the name in each
|
||||
* record just so it is easy to match things up
|
||||
*/
|
||||
#define TYPE(name, type) type
|
||||
static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = {
|
||||
/* 0x00 */
|
||||
TYPE(PERIPHC_I2S1, CLOCK_TYPE_AXPT),
|
||||
TYPE(PERIPHC_I2S2, CLOCK_TYPE_AXPT),
|
||||
TYPE(PERIPHC_SPDIF_OUT, CLOCK_TYPE_AXPT),
|
||||
TYPE(PERIPHC_SPDIF_IN, CLOCK_TYPE_PCM),
|
||||
TYPE(PERIPHC_PWM, CLOCK_TYPE_PCXTS),
|
||||
TYPE(PERIPHC_SPI1, CLOCK_TYPE_PCMT),
|
||||
TYPE(PERIPHC_SPI22, CLOCK_TYPE_PCMT),
|
||||
TYPE(PERIPHC_SPI3, CLOCK_TYPE_PCMT),
|
||||
|
||||
/* 0x08 */
|
||||
TYPE(PERIPHC_XIO, CLOCK_TYPE_PCMT),
|
||||
TYPE(PERIPHC_I2C1, CLOCK_TYPE_PCMT),
|
||||
TYPE(PERIPHC_DVC_I2C, CLOCK_TYPE_PCMT),
|
||||
TYPE(PERIPHC_TWC, CLOCK_TYPE_PCMT),
|
||||
TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
|
||||
TYPE(PERIPHC_SPI1, CLOCK_TYPE_PCMT),
|
||||
TYPE(PERIPHC_DISP1, CLOCK_TYPE_PDCT),
|
||||
TYPE(PERIPHC_DISP2, CLOCK_TYPE_PDCT),
|
||||
|
||||
/* 0x10 */
|
||||
TYPE(PERIPHC_CVE, CLOCK_TYPE_PDCT),
|
||||
TYPE(PERIPHC_IDE0, CLOCK_TYPE_PCMT),
|
||||
TYPE(PERIPHC_VI, CLOCK_TYPE_MCPA),
|
||||
TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
|
||||
TYPE(PERIPHC_SDMMC1, CLOCK_TYPE_PCMT),
|
||||
TYPE(PERIPHC_SDMMC2, CLOCK_TYPE_PCMT),
|
||||
TYPE(PERIPHC_G3D, CLOCK_TYPE_MCPA),
|
||||
TYPE(PERIPHC_G2D, CLOCK_TYPE_MCPA),
|
||||
|
||||
/* 0x18 */
|
||||
TYPE(PERIPHC_NDFLASH, CLOCK_TYPE_PCMT),
|
||||
TYPE(PERIPHC_SDMMC4, CLOCK_TYPE_PCMT),
|
||||
TYPE(PERIPHC_VFIR, CLOCK_TYPE_PCMT),
|
||||
TYPE(PERIPHC_EPP, CLOCK_TYPE_MCPA),
|
||||
TYPE(PERIPHC_MPE, CLOCK_TYPE_MCPA),
|
||||
TYPE(PERIPHC_MIPI, CLOCK_TYPE_PCMT),
|
||||
TYPE(PERIPHC_UART1, CLOCK_TYPE_PCMT),
|
||||
TYPE(PERIPHC_UART2, CLOCK_TYPE_PCMT),
|
||||
|
||||
/* 0x20 */
|
||||
TYPE(PERIPHC_HOST1X, CLOCK_TYPE_MCPA),
|
||||
TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
|
||||
TYPE(PERIPHC_TVO, CLOCK_TYPE_PDCT),
|
||||
TYPE(PERIPHC_HDMI, CLOCK_TYPE_PDCT),
|
||||
TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
|
||||
TYPE(PERIPHC_TVDAC, CLOCK_TYPE_PDCT),
|
||||
TYPE(PERIPHC_I2C2, CLOCK_TYPE_PCMT),
|
||||
TYPE(PERIPHC_EMC, CLOCK_TYPE_MCPT),
|
||||
|
||||
/* 0x28 */
|
||||
TYPE(PERIPHC_UART3, CLOCK_TYPE_PCMT),
|
||||
TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
|
||||
TYPE(PERIPHC_VI, CLOCK_TYPE_MCPA),
|
||||
TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
|
||||
TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
|
||||
TYPE(PERIPHC_SPI4, CLOCK_TYPE_PCMT),
|
||||
TYPE(PERIPHC_I2C3, CLOCK_TYPE_PCMT),
|
||||
TYPE(PERIPHC_SDMMC3, CLOCK_TYPE_PCMT),
|
||||
|
||||
/* 0x30 */
|
||||
TYPE(PERIPHC_UART4, CLOCK_TYPE_PCMT),
|
||||
TYPE(PERIPHC_UART5, CLOCK_TYPE_PCMT),
|
||||
TYPE(PERIPHC_VDE, CLOCK_TYPE_PCMT),
|
||||
TYPE(PERIPHC_OWR, CLOCK_TYPE_PCMT),
|
||||
TYPE(PERIPHC_NOR, CLOCK_TYPE_PCMT),
|
||||
TYPE(PERIPHC_CSITE, CLOCK_TYPE_PCMT),
|
||||
};
|
||||
|
||||
/*
|
||||
* This array translates a periph_id to a periphc_internal_id
|
||||
*
|
||||
* Not present/matched up:
|
||||
* uint vi_sensor; _VI_SENSOR_0, 0x1A8
|
||||
* SPDIF - which is both 0x08 and 0x0c
|
||||
*
|
||||
*/
|
||||
#define NONE(name) (-1)
|
||||
#define OFFSET(name, value) PERIPHC_ ## name
|
||||
static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = {
|
||||
/* Low word: 31:0 */
|
||||
NONE(CPU),
|
||||
NONE(RESERVED1),
|
||||
NONE(RESERVED2),
|
||||
NONE(AC97),
|
||||
NONE(RTC),
|
||||
NONE(TMR),
|
||||
PERIPHC_UART1,
|
||||
PERIPHC_UART2, /* and vfir 0x68 */
|
||||
|
||||
/* 0x08 */
|
||||
NONE(GPIO),
|
||||
PERIPHC_SDMMC2,
|
||||
NONE(SPDIF), /* 0x08 and 0x0c, unclear which to use */
|
||||
PERIPHC_I2S1,
|
||||
PERIPHC_I2C1,
|
||||
PERIPHC_NDFLASH,
|
||||
PERIPHC_SDMMC1,
|
||||
PERIPHC_SDMMC4,
|
||||
|
||||
/* 0x10 */
|
||||
PERIPHC_TWC,
|
||||
PERIPHC_PWM,
|
||||
PERIPHC_I2S2,
|
||||
PERIPHC_EPP,
|
||||
PERIPHC_VI,
|
||||
PERIPHC_G2D,
|
||||
NONE(USBD),
|
||||
NONE(ISP),
|
||||
|
||||
/* 0x18 */
|
||||
PERIPHC_G3D,
|
||||
PERIPHC_IDE0,
|
||||
PERIPHC_DISP2,
|
||||
PERIPHC_DISP1,
|
||||
PERIPHC_HOST1X,
|
||||
NONE(VCP),
|
||||
NONE(RESERVED30),
|
||||
NONE(CACHE2),
|
||||
|
||||
/* Middle word: 63:32 */
|
||||
NONE(MEM),
|
||||
NONE(AHBDMA),
|
||||
NONE(APBDMA),
|
||||
NONE(RESERVED35),
|
||||
NONE(KBC),
|
||||
NONE(STAT_MON),
|
||||
NONE(PMC),
|
||||
NONE(FUSE),
|
||||
|
||||
/* 0x28 */
|
||||
NONE(KFUSE),
|
||||
NONE(SBC1), /* SBC1, 0x34, is this SPI1? */
|
||||
PERIPHC_NOR,
|
||||
PERIPHC_SPI1,
|
||||
PERIPHC_SPI2,
|
||||
PERIPHC_XIO,
|
||||
PERIPHC_SPI3,
|
||||
PERIPHC_DVC_I2C,
|
||||
|
||||
/* 0x30 */
|
||||
NONE(DSI),
|
||||
PERIPHC_TVO, /* also CVE 0x40 */
|
||||
PERIPHC_MIPI,
|
||||
PERIPHC_HDMI,
|
||||
PERIPHC_CSITE,
|
||||
PERIPHC_TVDAC,
|
||||
PERIPHC_I2C2,
|
||||
PERIPHC_UART3,
|
||||
|
||||
/* 0x38 */
|
||||
NONE(RESERVED56),
|
||||
PERIPHC_EMC,
|
||||
NONE(USB2),
|
||||
NONE(USB3),
|
||||
PERIPHC_MPE,
|
||||
PERIPHC_VDE,
|
||||
NONE(BSEA),
|
||||
NONE(BSEV),
|
||||
|
||||
/* Upper word 95:64 */
|
||||
NONE(SPEEDO),
|
||||
PERIPHC_UART4,
|
||||
PERIPHC_UART5,
|
||||
PERIPHC_I2C3,
|
||||
PERIPHC_SPI4,
|
||||
PERIPHC_SDMMC3,
|
||||
NONE(PCIE),
|
||||
PERIPHC_OWR,
|
||||
|
||||
/* 0x48 */
|
||||
NONE(AFI),
|
||||
NONE(CORESIGHT),
|
||||
NONE(RESERVED74),
|
||||
NONE(AVPUCQ),
|
||||
NONE(RESERVED76),
|
||||
NONE(RESERVED77),
|
||||
NONE(RESERVED78),
|
||||
NONE(RESERVED79),
|
||||
|
||||
/* 0x50 */
|
||||
NONE(RESERVED80),
|
||||
NONE(RESERVED81),
|
||||
NONE(RESERVED82),
|
||||
NONE(RESERVED83),
|
||||
NONE(IRAMA),
|
||||
NONE(IRAMB),
|
||||
NONE(IRAMC),
|
||||
NONE(IRAMD),
|
||||
|
||||
/* 0x58 */
|
||||
NONE(CRAM2),
|
||||
};
|
||||
|
||||
/*
|
||||
* Get the oscillator frequency, from the corresponding hardware configuration
|
||||
|
@ -42,16 +407,21 @@ enum clock_osc_freq clock_get_osc_freq(void)
|
|||
return (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;
|
||||
}
|
||||
|
||||
unsigned long clock_start_pll(enum clock_pll_id clkid, u32 divm, u32 divn,
|
||||
u32 divp, u32 cpcon, u32 lfcon)
|
||||
/* Returns a pointer to the registers of the given pll */
|
||||
static struct clk_pll *get_pll(enum clock_id clkid)
|
||||
{
|
||||
struct clk_rst_ctlr *clkrst =
|
||||
(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
|
||||
u32 data;
|
||||
struct clk_pll *pll;
|
||||
|
||||
assert(clock_pll_id_isvalid(clkid));
|
||||
pll = &clkrst->crc_pll[clkid];
|
||||
assert(clock_id_isvalid(clkid));
|
||||
return &clkrst->crc_pll[clkid];
|
||||
}
|
||||
|
||||
unsigned long clock_start_pll(enum clock_id clkid, u32 divm, u32 divn,
|
||||
u32 divp, u32 cpcon, u32 lfcon)
|
||||
{
|
||||
struct clk_pll *pll = get_pll(clkid);
|
||||
u32 data;
|
||||
|
||||
/*
|
||||
* We cheat by treating all PLL (except PLLU) in the same fashion.
|
||||
|
@ -66,7 +436,7 @@ unsigned long clock_start_pll(enum clock_pll_id clkid, u32 divm, u32 divn,
|
|||
data = (divm << PLL_DIVM_SHIFT) | (divn << PLL_DIVN_SHIFT) |
|
||||
(0 << PLL_BYPASS_SHIFT) | (1 << PLL_ENABLE_SHIFT);
|
||||
|
||||
if (clkid == CLOCK_PLL_ID_USB)
|
||||
if (clkid == CLOCK_ID_USB)
|
||||
data |= divp << PLLU_VCO_FREQ_SHIFT;
|
||||
else
|
||||
data |= divp << PLL_DIVP_SHIFT;
|
||||
|
@ -76,6 +446,294 @@ unsigned long clock_start_pll(enum clock_pll_id clkid, u32 divm, u32 divn,
|
|||
return timer_get_us() + CLOCK_PLL_STABLE_DELAY_US;
|
||||
}
|
||||
|
||||
/* return 1 if a peripheral ID is in range and valid */
|
||||
static int clock_periph_id_isvalid(enum periph_id id)
|
||||
{
|
||||
if (id < PERIPH_ID_FIRST || id >= PERIPH_ID_COUNT)
|
||||
printf("Peripheral id %d out of range\n", id);
|
||||
else {
|
||||
switch (id) {
|
||||
case PERIPH_ID_RESERVED1:
|
||||
case PERIPH_ID_RESERVED2:
|
||||
case PERIPH_ID_RESERVED30:
|
||||
case PERIPH_ID_RESERVED35:
|
||||
case PERIPH_ID_RESERVED56:
|
||||
case PERIPH_ID_RESERVED74:
|
||||
case PERIPH_ID_RESERVED76:
|
||||
case PERIPH_ID_RESERVED77:
|
||||
case PERIPH_ID_RESERVED78:
|
||||
case PERIPH_ID_RESERVED79:
|
||||
case PERIPH_ID_RESERVED80:
|
||||
case PERIPH_ID_RESERVED81:
|
||||
case PERIPH_ID_RESERVED82:
|
||||
case PERIPH_ID_RESERVED83:
|
||||
printf("Peripheral id %d is reserved\n", id);
|
||||
break;
|
||||
default:
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Returns a pointer to the clock source register for a peripheral */
|
||||
static u32 *get_periph_source_reg(enum periph_id periph_id)
|
||||
{
|
||||
struct clk_rst_ctlr *clkrst =
|
||||
(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
|
||||
enum periphc_internal_id internal_id;
|
||||
|
||||
assert(clock_periph_id_isvalid(periph_id));
|
||||
internal_id = periph_id_to_internal_id[periph_id];
|
||||
assert(internal_id != -1);
|
||||
return &clkrst->crc_clk_src[internal_id];
|
||||
}
|
||||
|
||||
void clock_ll_set_source_divisor(enum periph_id periph_id, unsigned source,
|
||||
unsigned divisor)
|
||||
{
|
||||
u32 *reg = get_periph_source_reg(periph_id);
|
||||
u32 value;
|
||||
|
||||
value = readl(reg);
|
||||
|
||||
value &= ~OUT_CLK_SOURCE_MASK;
|
||||
value |= source << OUT_CLK_SOURCE_SHIFT;
|
||||
|
||||
value &= ~OUT_CLK_DIVISOR_MASK;
|
||||
value |= divisor << OUT_CLK_DIVISOR_SHIFT;
|
||||
|
||||
writel(value, reg);
|
||||
}
|
||||
|
||||
void clock_ll_set_source(enum periph_id periph_id, unsigned source)
|
||||
{
|
||||
u32 *reg = get_periph_source_reg(periph_id);
|
||||
|
||||
clrsetbits_le32(reg, OUT_CLK_SOURCE_MASK,
|
||||
source << OUT_CLK_SOURCE_SHIFT);
|
||||
}
|
||||
|
||||
/**
|
||||
* Given the parent's rate and the required rate for the children, this works
|
||||
* out the peripheral clock divider to use, in 7.1 binary format.
|
||||
*
|
||||
* @param parent_rate clock rate of parent clock in Hz
|
||||
* @param rate required clock rate for this clock
|
||||
* @return divider which should be used
|
||||
*/
|
||||
static int clk_div7_1_get_divider(unsigned long parent_rate,
|
||||
unsigned long rate)
|
||||
{
|
||||
u64 divider = parent_rate * 2;
|
||||
|
||||
divider += rate - 1;
|
||||
do_div(divider, rate);
|
||||
|
||||
if ((s64)divider - 2 < 0)
|
||||
return 0;
|
||||
|
||||
if ((s64)divider - 2 > 255)
|
||||
return -1;
|
||||
|
||||
return divider - 2;
|
||||
}
|
||||
|
||||
/**
|
||||
* Given the parent's rate and the divider in 7.1 format, this works out the
|
||||
* resulting peripheral clock rate.
|
||||
*
|
||||
* @param parent_rate clock rate of parent clock in Hz
|
||||
* @param divider which should be used in 7.1 format
|
||||
* @return effective clock rate of peripheral
|
||||
*/
|
||||
static unsigned long get_rate_from_divider(unsigned long parent_rate,
|
||||
int divider)
|
||||
{
|
||||
u64 rate;
|
||||
|
||||
rate = (u64)parent_rate * 2;
|
||||
do_div(rate, divider + 2);
|
||||
return rate;
|
||||
}
|
||||
|
||||
unsigned long clock_get_periph_rate(enum periph_id periph_id,
|
||||
enum clock_id parent)
|
||||
{
|
||||
u32 *reg = get_periph_source_reg(periph_id);
|
||||
|
||||
return get_rate_from_divider(pll_rate[parent],
|
||||
(readl(reg) & OUT_CLK_DIVISOR_MASK) >> OUT_CLK_DIVISOR_SHIFT);
|
||||
}
|
||||
|
||||
/**
|
||||
* Find the best available 7.1 format divisor given a parent clock rate and
|
||||
* required child clock rate. This function assumes that a second-stage
|
||||
* divisor is available which can divide by powers of 2 from 1 to 256.
|
||||
*
|
||||
* @param parent_rate clock rate of parent clock in Hz
|
||||
* @param rate required clock rate for this clock
|
||||
* @param extra_div value for the second-stage divisor (not set if this
|
||||
* function returns -1.
|
||||
* @return divider which should be used, or -1 if nothing is valid
|
||||
*
|
||||
*/
|
||||
static int find_best_divider(unsigned long parent_rate, unsigned long rate,
|
||||
int *extra_div)
|
||||
{
|
||||
int shift;
|
||||
int best_divider = -1;
|
||||
int best_error = rate;
|
||||
|
||||
/* try dividers from 1 to 256 and find closest match */
|
||||
for (shift = 0; shift <= 8 && best_error > 0; shift++) {
|
||||
unsigned divided_parent = parent_rate >> shift;
|
||||
int divider = clk_div7_1_get_divider(divided_parent, rate);
|
||||
unsigned effective_rate = get_rate_from_divider(divided_parent,
|
||||
divider);
|
||||
int error = rate - effective_rate;
|
||||
|
||||
/* Given a valid divider, look for the lowest error */
|
||||
if (divider != -1 && error < best_error) {
|
||||
best_error = error;
|
||||
*extra_div = 1 << shift;
|
||||
best_divider = divider;
|
||||
}
|
||||
}
|
||||
|
||||
/* return what we found - *extra_div will already be set */
|
||||
return best_divider;
|
||||
}
|
||||
|
||||
/**
|
||||
* Given a peripheral ID and the required source clock, this returns which
|
||||
* value should be programmed into the source mux for that peripheral.
|
||||
*
|
||||
* There is special code here to handle the one source type with 5 sources.
|
||||
*
|
||||
* @param periph_id peripheral to start
|
||||
* @param source PLL id of required parent clock
|
||||
* @param mux_bits Set to number of bits in mux register: 2 or 4
|
||||
* @return mux value (0-4, or -1 if not found)
|
||||
*/
|
||||
static int get_periph_clock_source(enum periph_id periph_id,
|
||||
enum clock_id parent, int *mux_bits)
|
||||
{
|
||||
enum clock_type_id type;
|
||||
enum periphc_internal_id internal_id;
|
||||
int mux;
|
||||
|
||||
assert(clock_periph_id_isvalid(periph_id));
|
||||
|
||||
internal_id = periph_id_to_internal_id[periph_id];
|
||||
assert(periphc_internal_id_isvalid(internal_id));
|
||||
|
||||
type = clock_periph_type[internal_id];
|
||||
assert(clock_type_id_isvalid(type));
|
||||
|
||||
/* Special case here for the clock with a 4-bit source mux */
|
||||
if (type == CLOCK_TYPE_PCXTS)
|
||||
*mux_bits = 4;
|
||||
else
|
||||
*mux_bits = 2;
|
||||
|
||||
for (mux = 0; mux < CLOCK_MAX_MUX; mux++)
|
||||
if (clock_source[type][mux] == parent)
|
||||
return mux;
|
||||
|
||||
/*
|
||||
* Not found: it might be looking for the 'S' in CLOCK_TYPE_PCXTS
|
||||
* which is not in our table. If not, then they are asking for a
|
||||
* source which this peripheral can't access through its mux.
|
||||
*/
|
||||
assert(type == CLOCK_TYPE_PCXTS);
|
||||
assert(parent == CLOCK_ID_SFROM32KHZ);
|
||||
if (type == CLOCK_TYPE_PCXTS && parent == CLOCK_ID_SFROM32KHZ)
|
||||
return 4; /* mux value for this clock */
|
||||
|
||||
/* if we get here, either us or the caller has made a mistake */
|
||||
printf("Caller requested bad clock: periph=%d, parent=%d\n", periph_id,
|
||||
parent);
|
||||
return -1;
|
||||
}
|
||||
|
||||
/**
|
||||
* Adjust peripheral PLL to use the given divider and source.
|
||||
*
|
||||
* @param periph_id peripheral to adjust
|
||||
* @param parent Required parent clock (for source mux)
|
||||
* @param divider Required divider in 7.1 format
|
||||
* @return 0 if ok, -1 on error (requesting a parent clock which is not valid
|
||||
* for this peripheral)
|
||||
*/
|
||||
static int adjust_periph_pll(enum periph_id periph_id,
|
||||
enum clock_id parent, unsigned divider)
|
||||
{
|
||||
u32 *reg = get_periph_source_reg(periph_id);
|
||||
unsigned source;
|
||||
int mux_bits;
|
||||
|
||||
clrsetbits_le32(reg, OUT_CLK_DIVISOR_MASK,
|
||||
divider << OUT_CLK_DIVISOR_SHIFT);
|
||||
udelay(1);
|
||||
|
||||
/* work out the source clock and set it */
|
||||
source = get_periph_clock_source(periph_id, parent, &mux_bits);
|
||||
if (source < 0)
|
||||
return -1;
|
||||
if (mux_bits == 4) {
|
||||
clrsetbits_le32(reg, OUT_CLK_SOURCE4_MASK,
|
||||
source << OUT_CLK_SOURCE4_SHIFT);
|
||||
} else {
|
||||
clrsetbits_le32(reg, OUT_CLK_SOURCE_MASK,
|
||||
source << OUT_CLK_SOURCE_SHIFT);
|
||||
}
|
||||
udelay(2);
|
||||
return 0;
|
||||
}
|
||||
|
||||
unsigned clock_adjust_periph_pll_div(enum periph_id periph_id,
|
||||
enum clock_id parent, unsigned rate, int *extra_div)
|
||||
{
|
||||
unsigned effective_rate;
|
||||
int divider;
|
||||
|
||||
if (extra_div)
|
||||
divider = find_best_divider(pll_rate[parent], rate, extra_div);
|
||||
else
|
||||
divider = clk_div7_1_get_divider(pll_rate[parent], rate);
|
||||
assert(divider >= 0);
|
||||
if (adjust_periph_pll(periph_id, parent, divider))
|
||||
return -1U;
|
||||
debug("periph %d, rate=%d, reg=%p = %x\n", periph_id, rate,
|
||||
get_periph_source_reg(periph_id),
|
||||
readl(get_periph_source_reg(periph_id)));
|
||||
|
||||
/* Check what we ended up with. This shouldn't matter though */
|
||||
effective_rate = clock_get_periph_rate(periph_id, parent);
|
||||
if (extra_div)
|
||||
effective_rate /= *extra_div;
|
||||
if (rate != effective_rate)
|
||||
debug("Requested clock rate %u not honored (got %u)\n",
|
||||
rate, effective_rate);
|
||||
return effective_rate;
|
||||
}
|
||||
|
||||
unsigned clock_start_periph_pll(enum periph_id periph_id,
|
||||
enum clock_id parent, unsigned rate)
|
||||
{
|
||||
unsigned effective_rate;
|
||||
|
||||
reset_set_enable(periph_id, 1);
|
||||
clock_enable(periph_id);
|
||||
|
||||
effective_rate = clock_adjust_periph_pll_div(periph_id, parent, rate,
|
||||
NULL);
|
||||
|
||||
reset_set_enable(periph_id, 0);
|
||||
return effective_rate;
|
||||
}
|
||||
|
||||
void clock_set_enable(enum periph_id periph_id, int enable)
|
||||
{
|
||||
struct clk_rst_ctlr *clkrst =
|
||||
|
@ -148,3 +806,156 @@ void reset_cmplx_set_enable(int cpu, int which, int reset)
|
|||
else
|
||||
writel(mask, &clkrst->crc_cpu_cmplx_clr);
|
||||
}
|
||||
|
||||
unsigned clock_get_rate(enum clock_id clkid)
|
||||
{
|
||||
struct clk_pll *pll;
|
||||
u32 base;
|
||||
u32 divm;
|
||||
u64 parent_rate;
|
||||
u64 rate;
|
||||
|
||||
parent_rate = osc_freq[clock_get_osc_freq()];
|
||||
if (clkid == CLOCK_ID_OSC)
|
||||
return parent_rate;
|
||||
|
||||
pll = get_pll(clkid);
|
||||
base = readl(&pll->pll_base);
|
||||
|
||||
/* Oh for bf_unpack()... */
|
||||
rate = parent_rate * ((base & PLL_DIVN_MASK) >> PLL_DIVN_SHIFT);
|
||||
divm = (base & PLL_DIVM_MASK) >> PLL_DIVM_SHIFT;
|
||||
if (clkid == CLOCK_ID_USB)
|
||||
divm <<= (base & PLLU_VCO_FREQ_MASK) >> PLLU_VCO_FREQ_SHIFT;
|
||||
else
|
||||
divm <<= (base & PLL_DIVP_MASK) >> PLL_DIVP_SHIFT;
|
||||
do_div(rate, divm);
|
||||
return rate;
|
||||
}
|
||||
|
||||
/**
|
||||
* Set the output frequency you want for each PLL clock.
|
||||
* PLL output frequencies are programmed by setting their N, M and P values.
|
||||
* The governing equations are:
|
||||
* VCO = (Fi / m) * n, Fo = VCO / (2^p)
|
||||
* where Fo is the output frequency from the PLL.
|
||||
* Example: Set the output frequency to 216Mhz(Fo) with 12Mhz OSC(Fi)
|
||||
* 216Mhz = ((12Mhz / m) * n) / (2^p) so n=432,m=12,p=1
|
||||
* Please see Tegra TRM section 5.3 to get the detail for PLL Programming
|
||||
*
|
||||
* @param n PLL feedback divider(DIVN)
|
||||
* @param m PLL input divider(DIVN)
|
||||
* @param p post divider(DIVP)
|
||||
* @param cpcon base PLL charge pump(CPCON)
|
||||
* @return 0 if ok, -1 on error (the requested PLL is incorrect and cannot
|
||||
* be overriden), 1 if PLL is already correct
|
||||
*/
|
||||
static int clock_set_rate(enum clock_id clkid, u32 n, u32 m, u32 p, u32 cpcon)
|
||||
{
|
||||
u32 base_reg;
|
||||
u32 misc_reg;
|
||||
struct clk_pll *pll;
|
||||
|
||||
pll = get_pll(clkid);
|
||||
|
||||
base_reg = readl(&pll->pll_base);
|
||||
|
||||
/* Set BYPASS, m, n and p to PLL_BASE */
|
||||
base_reg &= ~PLL_DIVM_MASK;
|
||||
base_reg |= m << PLL_DIVM_SHIFT;
|
||||
|
||||
base_reg &= ~PLL_DIVN_MASK;
|
||||
base_reg |= n << PLL_DIVN_SHIFT;
|
||||
|
||||
base_reg &= ~PLL_DIVP_MASK;
|
||||
base_reg |= p << PLL_DIVP_SHIFT;
|
||||
|
||||
if (clkid == CLOCK_ID_PERIPH) {
|
||||
/*
|
||||
* If the PLL is already set up, check that it is correct
|
||||
* and record this info for clock_verify() to check.
|
||||
*/
|
||||
if (base_reg & PLL_BASE_OVRRIDE_MASK) {
|
||||
base_reg |= PLL_ENABLE_MASK;
|
||||
if (base_reg != readl(&pll->pll_base))
|
||||
pllp_valid = 0;
|
||||
return pllp_valid ? 1 : -1;
|
||||
}
|
||||
base_reg |= PLL_BASE_OVRRIDE_MASK;
|
||||
}
|
||||
|
||||
base_reg |= PLL_BYPASS_MASK;
|
||||
writel(base_reg, &pll->pll_base);
|
||||
|
||||
/* Set cpcon to PLL_MISC */
|
||||
misc_reg = readl(&pll->pll_misc);
|
||||
misc_reg &= ~PLL_CPCON_MASK;
|
||||
misc_reg |= cpcon << PLL_CPCON_SHIFT;
|
||||
writel(misc_reg, &pll->pll_misc);
|
||||
|
||||
/* Enable PLL */
|
||||
base_reg |= PLL_ENABLE_MASK;
|
||||
writel(base_reg, &pll->pll_base);
|
||||
|
||||
/* Disable BYPASS */
|
||||
base_reg &= ~PLL_BYPASS_MASK;
|
||||
writel(base_reg, &pll->pll_base);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int clock_verify(void)
|
||||
{
|
||||
struct clk_pll *pll = get_pll(CLOCK_ID_PERIPH);
|
||||
u32 reg = readl(&pll->pll_base);
|
||||
|
||||
if (!pllp_valid) {
|
||||
printf("Warning: PLLP %x is not correct\n", reg);
|
||||
return -1;
|
||||
}
|
||||
debug("PLLX %x is correct\n", reg);
|
||||
return 0;
|
||||
}
|
||||
|
||||
void clock_early_init(void)
|
||||
{
|
||||
/*
|
||||
* PLLP output frequency set to 216MHz
|
||||
* PLLC output frequency set to 600Mhz
|
||||
*
|
||||
* TODO: Can we calculate these values instead of hard-coding?
|
||||
*/
|
||||
switch (clock_get_osc_freq()) {
|
||||
case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */
|
||||
clock_set_rate(CLOCK_ID_PERIPH, 432, 12, 1, 8);
|
||||
clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8);
|
||||
break;
|
||||
|
||||
case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */
|
||||
clock_set_rate(CLOCK_ID_PERIPH, 432, 26, 1, 8);
|
||||
clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8);
|
||||
break;
|
||||
|
||||
case CLOCK_OSC_FREQ_13_0:
|
||||
case CLOCK_OSC_FREQ_19_2:
|
||||
default:
|
||||
/*
|
||||
* These are not supported. It is too early to print a
|
||||
* message and the UART likely won't work anyway due to the
|
||||
* oscillator being wrong.
|
||||
*/
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
void clock_init(void)
|
||||
{
|
||||
pll_rate[CLOCK_ID_MEMORY] = clock_get_rate(CLOCK_ID_MEMORY);
|
||||
pll_rate[CLOCK_ID_PERIPH] = clock_get_rate(CLOCK_ID_PERIPH);
|
||||
pll_rate[CLOCK_ID_CGENERAL] = clock_get_rate(CLOCK_ID_CGENERAL);
|
||||
pll_rate[CLOCK_ID_OSC] = clock_get_rate(CLOCK_ID_OSC);
|
||||
pll_rate[CLOCK_ID_SFROM32KHZ] = 32768;
|
||||
debug("Osc = %d\n", pll_rate[CLOCK_ID_OSC]);
|
||||
debug("PLLM = %d\n", pll_rate[CLOCK_ID_MEMORY]);
|
||||
debug("PLLP = %d\n", pll_rate[CLOCK_ID_PERIPH]);
|
||||
}
|
||||
|
|
|
@ -27,9 +27,463 @@
|
|||
#include <common.h>
|
||||
|
||||
|
||||
void pinmux_set_tristate(enum pmux_pin pin, int enable)
|
||||
/*
|
||||
* This defines the order of the pin mux control bits in the registers. For
|
||||
* some reason there is no correspendence between the tristate, pin mux and
|
||||
* pullup/pulldown registers.
|
||||
*/
|
||||
enum pmux_ctlid {
|
||||
/* 0: APB_MISC_PP_PIN_MUX_CTL_A_0 */
|
||||
MUXCTL_UAA,
|
||||
MUXCTL_UAB,
|
||||
MUXCTL_UAC,
|
||||
MUXCTL_UAD,
|
||||
MUXCTL_UDA,
|
||||
MUXCTL_RESERVED5,
|
||||
MUXCTL_ATE,
|
||||
MUXCTL_RM,
|
||||
|
||||
MUXCTL_ATB,
|
||||
MUXCTL_RESERVED9,
|
||||
MUXCTL_ATD,
|
||||
MUXCTL_ATC,
|
||||
MUXCTL_ATA,
|
||||
MUXCTL_KBCF,
|
||||
MUXCTL_KBCE,
|
||||
MUXCTL_SDMMC1,
|
||||
|
||||
/* 16: APB_MISC_PP_PIN_MUX_CTL_B_0 */
|
||||
MUXCTL_GMA,
|
||||
MUXCTL_GMC,
|
||||
MUXCTL_HDINT,
|
||||
MUXCTL_SLXA,
|
||||
MUXCTL_OWC,
|
||||
MUXCTL_SLXC,
|
||||
MUXCTL_SLXD,
|
||||
MUXCTL_SLXK,
|
||||
|
||||
MUXCTL_UCA,
|
||||
MUXCTL_UCB,
|
||||
MUXCTL_DTA,
|
||||
MUXCTL_DTB,
|
||||
MUXCTL_RESERVED28,
|
||||
MUXCTL_DTC,
|
||||
MUXCTL_DTD,
|
||||
MUXCTL_DTE,
|
||||
|
||||
/* 32: APB_MISC_PP_PIN_MUX_CTL_C_0 */
|
||||
MUXCTL_DDC,
|
||||
MUXCTL_CDEV1,
|
||||
MUXCTL_CDEV2,
|
||||
MUXCTL_CSUS,
|
||||
MUXCTL_I2CP,
|
||||
MUXCTL_KBCA,
|
||||
MUXCTL_KBCB,
|
||||
MUXCTL_KBCC,
|
||||
|
||||
MUXCTL_IRTX,
|
||||
MUXCTL_IRRX,
|
||||
MUXCTL_DAP1,
|
||||
MUXCTL_DAP2,
|
||||
MUXCTL_DAP3,
|
||||
MUXCTL_DAP4,
|
||||
MUXCTL_GMB,
|
||||
MUXCTL_GMD,
|
||||
|
||||
/* 48: APB_MISC_PP_PIN_MUX_CTL_D_0 */
|
||||
MUXCTL_GME,
|
||||
MUXCTL_GPV,
|
||||
MUXCTL_GPU,
|
||||
MUXCTL_SPDO,
|
||||
MUXCTL_SPDI,
|
||||
MUXCTL_SDB,
|
||||
MUXCTL_SDC,
|
||||
MUXCTL_SDD,
|
||||
|
||||
MUXCTL_SPIH,
|
||||
MUXCTL_SPIG,
|
||||
MUXCTL_SPIF,
|
||||
MUXCTL_SPIE,
|
||||
MUXCTL_SPID,
|
||||
MUXCTL_SPIC,
|
||||
MUXCTL_SPIB,
|
||||
MUXCTL_SPIA,
|
||||
|
||||
/* 64: APB_MISC_PP_PIN_MUX_CTL_E_0 */
|
||||
MUXCTL_LPW0,
|
||||
MUXCTL_LPW1,
|
||||
MUXCTL_LPW2,
|
||||
MUXCTL_LSDI,
|
||||
MUXCTL_LSDA,
|
||||
MUXCTL_LSPI,
|
||||
MUXCTL_LCSN,
|
||||
MUXCTL_LDC,
|
||||
|
||||
MUXCTL_LSCK,
|
||||
MUXCTL_LSC0,
|
||||
MUXCTL_LSC1,
|
||||
MUXCTL_LHS,
|
||||
MUXCTL_LVS,
|
||||
MUXCTL_LM0,
|
||||
MUXCTL_LM1,
|
||||
MUXCTL_LVP0,
|
||||
|
||||
/* 80: APB_MISC_PP_PIN_MUX_CTL_F_0 */
|
||||
MUXCTL_LD0,
|
||||
MUXCTL_LD1,
|
||||
MUXCTL_LD2,
|
||||
MUXCTL_LD3,
|
||||
MUXCTL_LD4,
|
||||
MUXCTL_LD5,
|
||||
MUXCTL_LD6,
|
||||
MUXCTL_LD7,
|
||||
|
||||
MUXCTL_LD8,
|
||||
MUXCTL_LD9,
|
||||
MUXCTL_LD10,
|
||||
MUXCTL_LD11,
|
||||
MUXCTL_LD12,
|
||||
MUXCTL_LD13,
|
||||
MUXCTL_LD14,
|
||||
MUXCTL_LD15,
|
||||
|
||||
/* 96: APB_MISC_PP_PIN_MUX_CTL_G_0 */
|
||||
MUXCTL_LD16,
|
||||
MUXCTL_LD17,
|
||||
MUXCTL_LHP1,
|
||||
MUXCTL_LHP2,
|
||||
MUXCTL_LVP1,
|
||||
MUXCTL_LHP0,
|
||||
MUXCTL_RESERVED102,
|
||||
MUXCTL_LPP,
|
||||
|
||||
MUXCTL_LDI,
|
||||
MUXCTL_PMC,
|
||||
MUXCTL_CRTP,
|
||||
MUXCTL_PTA,
|
||||
MUXCTL_RESERVED108,
|
||||
MUXCTL_KBCD,
|
||||
MUXCTL_GPU7,
|
||||
MUXCTL_DTF,
|
||||
|
||||
MUXCTL_NONE = -1,
|
||||
};
|
||||
|
||||
/*
|
||||
* And this defines the order of the pullup/pulldown controls which are again
|
||||
* in a different order
|
||||
*/
|
||||
enum pmux_pullid {
|
||||
/* 0: APB_MISC_PP_PULLUPDOWN_REG_A_0 */
|
||||
PUCTL_ATA,
|
||||
PUCTL_ATB,
|
||||
PUCTL_ATC,
|
||||
PUCTL_ATD,
|
||||
PUCTL_ATE,
|
||||
PUCTL_DAP1,
|
||||
PUCTL_DAP2,
|
||||
PUCTL_DAP3,
|
||||
|
||||
PUCTL_DAP4,
|
||||
PUCTL_DTA,
|
||||
PUCTL_DTB,
|
||||
PUCTL_DTC,
|
||||
PUCTL_DTD,
|
||||
PUCTL_DTE,
|
||||
PUCTL_DTF,
|
||||
PUCTL_GPV,
|
||||
|
||||
/* 16: APB_MISC_PP_PULLUPDOWN_REG_B_0 */
|
||||
PUCTL_RM,
|
||||
PUCTL_I2CP,
|
||||
PUCTL_PTA,
|
||||
PUCTL_GPU7,
|
||||
PUCTL_KBCA,
|
||||
PUCTL_KBCB,
|
||||
PUCTL_KBCC,
|
||||
PUCTL_KBCD,
|
||||
|
||||
PUCTL_SPDI,
|
||||
PUCTL_SPDO,
|
||||
PUCTL_GPSLXAU,
|
||||
PUCTL_CRTP,
|
||||
PUCTL_SLXC,
|
||||
PUCTL_SLXD,
|
||||
PUCTL_SLXK,
|
||||
|
||||
/* 32: APB_MISC_PP_PULLUPDOWN_REG_C_0 */
|
||||
PUCTL_CDEV1,
|
||||
PUCTL_CDEV2,
|
||||
PUCTL_SPIA,
|
||||
PUCTL_SPIB,
|
||||
PUCTL_SPIC,
|
||||
PUCTL_SPID,
|
||||
PUCTL_SPIE,
|
||||
PUCTL_SPIF,
|
||||
|
||||
PUCTL_SPIG,
|
||||
PUCTL_SPIH,
|
||||
PUCTL_IRTX,
|
||||
PUCTL_IRRX,
|
||||
PUCTL_GME,
|
||||
PUCTL_RESERVED45,
|
||||
PUCTL_XM2D,
|
||||
PUCTL_XM2C,
|
||||
|
||||
/* 48: APB_MISC_PP_PULLUPDOWN_REG_D_0 */
|
||||
PUCTL_UAA,
|
||||
PUCTL_UAB,
|
||||
PUCTL_UAC,
|
||||
PUCTL_UAD,
|
||||
PUCTL_UCA,
|
||||
PUCTL_UCB,
|
||||
PUCTL_LD17,
|
||||
PUCTL_LD19_18,
|
||||
|
||||
PUCTL_LD21_20,
|
||||
PUCTL_LD23_22,
|
||||
PUCTL_LS,
|
||||
PUCTL_LC,
|
||||
PUCTL_CSUS,
|
||||
PUCTL_DDRC,
|
||||
PUCTL_SDC,
|
||||
PUCTL_SDD,
|
||||
|
||||
/* 64: APB_MISC_PP_PULLUPDOWN_REG_E_0 */
|
||||
PUCTL_KBCF,
|
||||
PUCTL_KBCE,
|
||||
PUCTL_PMCA,
|
||||
PUCTL_PMCB,
|
||||
PUCTL_PMCC,
|
||||
PUCTL_PMCD,
|
||||
PUCTL_PMCE,
|
||||
PUCTL_CK32,
|
||||
|
||||
PUCTL_UDA,
|
||||
PUCTL_SDMMC1,
|
||||
PUCTL_GMA,
|
||||
PUCTL_GMB,
|
||||
PUCTL_GMC,
|
||||
PUCTL_GMD,
|
||||
PUCTL_DDC,
|
||||
PUCTL_OWC,
|
||||
|
||||
PUCTL_NONE = -1
|
||||
};
|
||||
|
||||
struct tegra_pingroup_desc {
|
||||
const char *name;
|
||||
enum pmux_func funcs[4];
|
||||
enum pmux_func func_safe;
|
||||
enum pmux_vddio vddio;
|
||||
enum pmux_ctlid ctl_id;
|
||||
enum pmux_pullid pull_id;
|
||||
};
|
||||
|
||||
|
||||
/* Converts a pmux_pingrp number to a tristate register: 0=A, 1=B, 2=C, 3=D */
|
||||
#define TRISTATE_REG(pmux_pingrp) ((pmux_pingrp) >> 5)
|
||||
|
||||
/* Mask value for a tristate (within TRISTATE_REG(id)) */
|
||||
#define TRISTATE_MASK(pmux_pingrp) (1 << ((pmux_pingrp) & 0x1f))
|
||||
|
||||
/* Converts a PUCTL id to a pull register: 0=A, 1=B...4=E */
|
||||
#define PULL_REG(pmux_pullid) ((pmux_pullid) >> 4)
|
||||
|
||||
/* Converts a PUCTL id to a shift position */
|
||||
#define PULL_SHIFT(pmux_pullid) ((pmux_pullid << 1) & 0x1f)
|
||||
|
||||
/* Converts a MUXCTL id to a ctl register: 0=A, 1=B...6=G */
|
||||
#define MUXCTL_REG(pmux_ctlid) ((pmux_ctlid) >> 4)
|
||||
|
||||
/* Converts a MUXCTL id to a shift position */
|
||||
#define MUXCTL_SHIFT(pmux_ctlid) ((pmux_ctlid << 1) & 0x1f)
|
||||
|
||||
/* Convenient macro for defining pin group properties */
|
||||
#define PINALL(pg_name, vdd, f0, f1, f2, f3, f_safe, mux, pupd) \
|
||||
{ \
|
||||
.vddio = PMUX_VDDIO_ ## vdd, \
|
||||
.funcs = { \
|
||||
PMUX_FUNC_ ## f0, \
|
||||
PMUX_FUNC_ ## f1, \
|
||||
PMUX_FUNC_ ## f2, \
|
||||
PMUX_FUNC_ ## f3, \
|
||||
}, \
|
||||
.func_safe = PMUX_FUNC_ ## f_safe, \
|
||||
.ctl_id = mux, \
|
||||
.pull_id = pupd \
|
||||
}
|
||||
|
||||
/* A normal pin group where the mux name and pull-up name match */
|
||||
#define PIN(pg_name, vdd, f0, f1, f2, f3, f_safe) \
|
||||
PINALL(pg_name, vdd, f0, f1, f2, f3, f_safe, \
|
||||
MUXCTL_ ## pg_name, PUCTL_ ## pg_name)
|
||||
|
||||
/* A pin group where the pull-up name doesn't have a 1-1 mapping */
|
||||
#define PINP(pg_name, vdd, f0, f1, f2, f3, f_safe, pupd) \
|
||||
PINALL(pg_name, vdd, f0, f1, f2, f3, f_safe, \
|
||||
MUXCTL_ ## pg_name, PUCTL_ ## pupd)
|
||||
|
||||
/* A pin group number which is not used */
|
||||
#define PIN_RESERVED \
|
||||
PIN(NONE, NONE, NONE, NONE, NONE, NONE, NONE)
|
||||
|
||||
const struct tegra_pingroup_desc tegra_soc_pingroups[PINGRP_COUNT] = {
|
||||
PIN(ATA, NAND, IDE, NAND, GMI, RSVD, IDE),
|
||||
PIN(ATB, NAND, IDE, NAND, GMI, SDIO4, IDE),
|
||||
PIN(ATC, NAND, IDE, NAND, GMI, SDIO4, IDE),
|
||||
PIN(ATD, NAND, IDE, NAND, GMI, SDIO4, IDE),
|
||||
PIN(CDEV1, AUDIO, OSC, PLLA_OUT, PLLM_OUT1, AUDIO_SYNC, OSC),
|
||||
PIN(CDEV2, AUDIO, OSC, AHB_CLK, APB_CLK, PLLP_OUT4, OSC),
|
||||
PIN(CSUS, VI, PLLC_OUT1, PLLP_OUT2, PLLP_OUT3, VI_SENSOR_CLK,
|
||||
PLLC_OUT1),
|
||||
PIN(DAP1, AUDIO, DAP1, RSVD, GMI, SDIO2, DAP1),
|
||||
|
||||
PIN(DAP2, AUDIO, DAP2, TWC, RSVD, GMI, DAP2),
|
||||
PIN(DAP3, BB, DAP3, RSVD, RSVD, RSVD, DAP3),
|
||||
PIN(DAP4, UART, DAP4, RSVD, GMI, RSVD, DAP4),
|
||||
PIN(DTA, VI, RSVD, SDIO2, VI, RSVD, RSVD4),
|
||||
PIN(DTB, VI, RSVD, RSVD, VI, SPI1, RSVD1),
|
||||
PIN(DTC, VI, RSVD, RSVD, VI, RSVD, RSVD1),
|
||||
PIN(DTD, VI, RSVD, SDIO2, VI, RSVD, RSVD1),
|
||||
PIN(DTE, VI, RSVD, RSVD, VI, SPI1, RSVD1),
|
||||
|
||||
PINP(GPU, UART, PWM, UARTA, GMI, RSVD, RSVD4,
|
||||
GPSLXAU),
|
||||
PIN(GPV, SD, PCIE, RSVD, RSVD, RSVD, PCIE),
|
||||
PIN(I2CP, SYS, I2C, RSVD, RSVD, RSVD, RSVD4),
|
||||
PIN(IRTX, UART, UARTA, UARTB, GMI, SPI4, UARTB),
|
||||
PIN(IRRX, UART, UARTA, UARTB, GMI, SPI4, UARTB),
|
||||
PIN(KBCB, SYS, KBC, NAND, SDIO2, MIO, KBC),
|
||||
PIN(KBCA, SYS, KBC, NAND, SDIO2, EMC_TEST0_DLL, KBC),
|
||||
PINP(PMC, SYS, PWR_ON, PWR_INTR, RSVD, RSVD, PWR_ON, NONE),
|
||||
|
||||
PIN(PTA, NAND, I2C2, HDMI, GMI, RSVD, RSVD4),
|
||||
PIN(RM, UART, I2C, RSVD, RSVD, RSVD, RSVD4),
|
||||
PIN(KBCE, SYS, KBC, NAND, OWR, RSVD, KBC),
|
||||
PIN(KBCF, SYS, KBC, NAND, TRACE, MIO, KBC),
|
||||
PIN(GMA, NAND, UARTE, SPI3, GMI, SDIO4, SPI3),
|
||||
PIN(GMC, NAND, UARTD, SPI4, GMI, SFLASH, SPI4),
|
||||
PIN(SDMMC1, BB, SDIO1, RSVD, UARTE, UARTA, RSVD2),
|
||||
PIN(OWC, SYS, OWR, RSVD, RSVD, RSVD, OWR),
|
||||
|
||||
PIN(GME, NAND, RSVD, DAP5, GMI, SDIO4, GMI),
|
||||
PIN(SDC, SD, PWM, TWC, SDIO3, SPI3, TWC),
|
||||
PIN(SDD, SD, UARTA, PWM, SDIO3, SPI3, PWM),
|
||||
PIN_RESERVED,
|
||||
PINP(SLXA, SD, PCIE, SPI4, SDIO3, SPI2, PCIE, CRTP),
|
||||
PIN(SLXC, SD, SPDIF, SPI4, SDIO3, SPI2, SPI4),
|
||||
PIN(SLXD, SD, SPDIF, SPI4, SDIO3, SPI2, SPI4),
|
||||
PIN(SLXK, SD, PCIE, SPI4, SDIO3, SPI2, PCIE),
|
||||
|
||||
PIN(SPDI, AUDIO, SPDIF, RSVD, I2C, SDIO2, RSVD2),
|
||||
PIN(SPDO, AUDIO, SPDIF, RSVD, I2C, SDIO2, RSVD2),
|
||||
PIN(SPIA, AUDIO, SPI1, SPI2, SPI3, GMI, GMI),
|
||||
PIN(SPIB, AUDIO, SPI1, SPI2, SPI3, GMI, GMI),
|
||||
PIN(SPIC, AUDIO, SPI1, SPI2, SPI3, GMI, GMI),
|
||||
PIN(SPID, AUDIO, SPI2, SPI1, SPI2_ALT, GMI, GMI),
|
||||
PIN(SPIE, AUDIO, SPI2, SPI1, SPI2_ALT, GMI, GMI),
|
||||
PIN(SPIF, AUDIO, SPI3, SPI1, SPI2, RSVD, RSVD4),
|
||||
|
||||
PIN(SPIG, AUDIO, SPI3, SPI2, SPI2_ALT, I2C, SPI2_ALT),
|
||||
PIN(SPIH, AUDIO, SPI3, SPI2, SPI2_ALT, I2C, SPI2_ALT),
|
||||
PIN(UAA, BB, SPI3, MIPI_HS, UARTA, ULPI, MIPI_HS),
|
||||
PIN(UAB, BB, SPI2, MIPI_HS, UARTA, ULPI, MIPI_HS),
|
||||
PIN(UAC, BB, OWR, RSVD, RSVD, RSVD, RSVD4),
|
||||
PIN(UAD, UART, IRDA, SPDIF, UARTA, SPI4, SPDIF),
|
||||
PIN(UCA, UART, UARTC, RSVD, GMI, RSVD, RSVD4),
|
||||
PIN(UCB, UART, UARTC, PWM, GMI, RSVD, RSVD4),
|
||||
|
||||
PIN_RESERVED,
|
||||
PIN(ATE, NAND, IDE, NAND, GMI, RSVD, IDE),
|
||||
PIN(KBCC, SYS, KBC, NAND, TRACE, EMC_TEST1_DLL, KBC),
|
||||
PIN_RESERVED,
|
||||
PIN_RESERVED,
|
||||
PIN(GMB, NAND, IDE, NAND, GMI, GMI_INT, GMI),
|
||||
PIN(GMD, NAND, RSVD, NAND, GMI, SFLASH, GMI),
|
||||
PIN(DDC, LCD, I2C2, RSVD, RSVD, RSVD, RSVD4),
|
||||
|
||||
/* 64 */
|
||||
PINP(LD0, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
|
||||
PINP(LD1, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
|
||||
PINP(LD2, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
|
||||
PINP(LD3, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
|
||||
PINP(LD4, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
|
||||
PINP(LD5, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
|
||||
PINP(LD6, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
|
||||
PINP(LD7, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
|
||||
|
||||
PINP(LD8, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
|
||||
PINP(LD9, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
|
||||
PINP(LD10, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
|
||||
PINP(LD11, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
|
||||
PINP(LD12, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
|
||||
PINP(LD13, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
|
||||
PINP(LD14, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
|
||||
PINP(LD15, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
|
||||
|
||||
PINP(LD16, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
|
||||
PINP(LD17, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LD17),
|
||||
PINP(LHP0, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LD21_20),
|
||||
PINP(LHP1, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LD19_18),
|
||||
PINP(LHP2, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LD19_18),
|
||||
PINP(LVP0, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LC),
|
||||
PINP(LVP1, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LD21_20),
|
||||
PINP(HDINT, LCD, HDMI, RSVD, RSVD, RSVD, HDMI , LC),
|
||||
|
||||
PINP(LM0, LCD, DISPA, DISPB, SPI3, RSVD, RSVD4, LC),
|
||||
PINP(LM1, LCD, DISPA, DISPB, RSVD, CRT, RSVD3, LC),
|
||||
PINP(LVS, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LC),
|
||||
PINP(LSC0, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LC),
|
||||
PINP(LSC1, LCD, DISPA, DISPB, SPI3, HDMI, DISPA, LS),
|
||||
PINP(LSCK, LCD, DISPA, DISPB, SPI3, HDMI, DISPA, LS),
|
||||
PINP(LDC, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LS),
|
||||
PINP(LCSN, LCD, DISPA, DISPB, SPI3, RSVD, RSVD4, LS),
|
||||
|
||||
/* 96 */
|
||||
PINP(LSPI, LCD, DISPA, DISPB, XIO, HDMI, DISPA, LC),
|
||||
PINP(LSDA, LCD, DISPA, DISPB, SPI3, HDMI, DISPA, LS),
|
||||
PINP(LSDI, LCD, DISPA, DISPB, SPI3, RSVD, DISPA, LS),
|
||||
PINP(LPW0, LCD, DISPA, DISPB, SPI3, HDMI, DISPA, LS),
|
||||
PINP(LPW1, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LS),
|
||||
PINP(LPW2, LCD, DISPA, DISPB, SPI3, HDMI, DISPA, LS),
|
||||
PINP(LDI, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LD23_22),
|
||||
PINP(LHS, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LC),
|
||||
|
||||
PINP(LPP, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LD23_22),
|
||||
PIN_RESERVED,
|
||||
PIN(KBCD, SYS, KBC, NAND, SDIO2, MIO, KBC),
|
||||
PIN(GPU7, SYS, RTCK, RSVD, RSVD, RSVD, RTCK),
|
||||
PIN(DTF, VI, I2C3, RSVD, VI, RSVD, RSVD4),
|
||||
PIN(UDA, BB, SPI1, RSVD, UARTD, ULPI, RSVD2),
|
||||
PIN(CRTP, LCD, CRT, RSVD, RSVD, RSVD, RSVD),
|
||||
PINP(SDB, SD, UARTA, PWM, SDIO3, SPI2, PWM, NONE),
|
||||
|
||||
/* these pin groups only have pullup and pull down control */
|
||||
PINALL(CK32, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE,
|
||||
PUCTL_NONE),
|
||||
PINALL(DDRC, DDR, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE,
|
||||
PUCTL_NONE),
|
||||
PINALL(PMCA, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE,
|
||||
PUCTL_NONE),
|
||||
PINALL(PMCB, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE,
|
||||
PUCTL_NONE),
|
||||
PINALL(PMCC, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE,
|
||||
PUCTL_NONE),
|
||||
PINALL(PMCD, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE,
|
||||
PUCTL_NONE),
|
||||
PINALL(PMCE, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE,
|
||||
PUCTL_NONE),
|
||||
PINALL(XM2C, DDR, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE,
|
||||
PUCTL_NONE),
|
||||
PINALL(XM2D, DDR, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE,
|
||||
PUCTL_NONE),
|
||||
};
|
||||
|
||||
void pinmux_set_tristate(enum pmux_pingrp pin, int enable)
|
||||
{
|
||||
struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
|
||||
struct pmux_tri_ctlr *pmt =
|
||||
(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
|
||||
u32 *tri = &pmt->pmt_tri[TRISTATE_REG(pin)];
|
||||
u32 reg;
|
||||
|
||||
|
@ -41,12 +495,78 @@ void pinmux_set_tristate(enum pmux_pin pin, int enable)
|
|||
writel(reg, tri);
|
||||
}
|
||||
|
||||
void pinmux_tristate_enable(enum pmux_pin pin)
|
||||
void pinmux_tristate_enable(enum pmux_pingrp pin)
|
||||
{
|
||||
pinmux_set_tristate(pin, 1);
|
||||
}
|
||||
|
||||
void pinmux_tristate_disable(enum pmux_pin pin)
|
||||
void pinmux_tristate_disable(enum pmux_pingrp pin)
|
||||
{
|
||||
pinmux_set_tristate(pin, 0);
|
||||
}
|
||||
|
||||
void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd)
|
||||
{
|
||||
struct pmux_tri_ctlr *pmt =
|
||||
(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
|
||||
enum pmux_pullid pull_id = tegra_soc_pingroups[pin].pull_id;
|
||||
u32 *pull = &pmt->pmt_pull[PULL_REG(pull_id)];
|
||||
u32 mask_bit;
|
||||
u32 reg;
|
||||
mask_bit = PULL_SHIFT(pull_id);
|
||||
|
||||
reg = readl(pull);
|
||||
reg &= ~(0x3 << mask_bit);
|
||||
reg |= pupd << mask_bit;
|
||||
writel(reg, pull);
|
||||
}
|
||||
|
||||
void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func)
|
||||
{
|
||||
struct pmux_tri_ctlr *pmt =
|
||||
(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
|
||||
enum pmux_ctlid mux_id = tegra_soc_pingroups[pin].ctl_id;
|
||||
u32 *muxctl = &pmt->pmt_ctl[MUXCTL_REG(mux_id)];
|
||||
u32 mask_bit;
|
||||
int i, mux = -1;
|
||||
u32 reg;
|
||||
|
||||
assert(pmux_func_isvalid(func));
|
||||
|
||||
/* Handle special values */
|
||||
if (func >= PMUX_FUNC_RSVD1) {
|
||||
mux = (func - PMUX_FUNC_RSVD1) & 0x3;
|
||||
} else {
|
||||
/* Search for the appropriate function */
|
||||
for (i = 0; i < 4; i++) {
|
||||
if (tegra_soc_pingroups[pin].funcs[i] == func) {
|
||||
mux = i;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
assert(mux != -1);
|
||||
|
||||
mask_bit = MUXCTL_SHIFT(mux_id);
|
||||
reg = readl(muxctl);
|
||||
reg &= ~(0x3 << mask_bit);
|
||||
reg |= mux << mask_bit;
|
||||
writel(reg, muxctl);
|
||||
}
|
||||
|
||||
void pinmux_config_pingroup(struct pingroup_config *config)
|
||||
{
|
||||
enum pmux_pingrp pin = config->pingroup;
|
||||
|
||||
pinmux_set_func(pin, config->func);
|
||||
pinmux_set_pullupdown(pin, config->pull);
|
||||
pinmux_set_tristate(pin, config->tristate);
|
||||
}
|
||||
|
||||
void pinmux_config_table(struct pingroup_config *config, int len)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < len; i++)
|
||||
pinmux_config_pingroup(&config[i]);
|
||||
}
|
||||
|
|
24
arch/arm/include/asm/arch-am33xx/clock.h
Normal file
24
arch/arm/include/asm/arch-am33xx/clock.h
Normal file
|
@ -0,0 +1,24 @@
|
|||
/*
|
||||
* clock.h
|
||||
*
|
||||
* clock header
|
||||
*
|
||||
* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef _CLOCKS_H_
|
||||
#define _CLOCKS_H_
|
||||
|
||||
#include <asm/arch/clocks_am33xx.h>
|
||||
|
||||
#endif
|
55
arch/arm/include/asm/arch-am33xx/clocks_am33xx.h
Normal file
55
arch/arm/include/asm/arch-am33xx/clocks_am33xx.h
Normal file
|
@ -0,0 +1,55 @@
|
|||
/*
|
||||
* clocks_am33xx.h
|
||||
*
|
||||
* AM33xx clock define
|
||||
*
|
||||
* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef _CLOCKS_AM33XX_H_
|
||||
#define _CLOCKS_AM33XX_H_
|
||||
|
||||
#define OSC 24
|
||||
|
||||
/* MAIN PLL Fdll = 550 MHZ, */
|
||||
#define MPUPLL_M 550
|
||||
#define MPUPLL_N 23
|
||||
#define MPUPLL_M2 1
|
||||
|
||||
/* Core PLL Fdll = 1 GHZ, */
|
||||
#define COREPLL_M 1000
|
||||
#define COREPLL_N 23
|
||||
|
||||
#define COREPLL_M4 10 /* CORE_CLKOUTM4 = 200 MHZ */
|
||||
#define COREPLL_M5 8 /* CORE_CLKOUTM5 = 250 MHZ */
|
||||
#define COREPLL_M6 4 /* CORE_CLKOUTM6 = 500 MHZ */
|
||||
|
||||
/*
|
||||
* USB PHY clock is 960 MHZ. Since, this comes directly from Fdll, Fdll
|
||||
* frequency needs to be set to 960 MHZ. Hence,
|
||||
* For clkout = 192 MHZ, Fdll = 960 MHZ, divider values are given below
|
||||
*/
|
||||
#define PERPLL_M 960
|
||||
#define PERPLL_N 23
|
||||
#define PERPLL_M2 5
|
||||
|
||||
/* DDR Freq is 266 MHZ for now */
|
||||
/* Set Fdll = 400 MHZ , Fdll = M * 2 * CLKINP/ N + 1; clkout = Fdll /(2 * M2) */
|
||||
#define DDRPLL_M 266
|
||||
#define DDRPLL_N 23
|
||||
#define DDRPLL_M2 1
|
||||
|
||||
extern void pll_init(void);
|
||||
extern void enable_emif_clocks(void);
|
||||
|
||||
#endif /* endif _CLOCKS_AM33XX_H_ */
|
218
arch/arm/include/asm/arch-am33xx/cpu.h
Normal file
218
arch/arm/include/asm/arch-am33xx/cpu.h
Normal file
|
@ -0,0 +1,218 @@
|
|||
/*
|
||||
* cpu.h
|
||||
*
|
||||
* AM33xx specific header file
|
||||
*
|
||||
* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef _AM33XX_CPU_H
|
||||
#define _AM33XX_CPU_H
|
||||
|
||||
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
|
||||
#include <asm/types.h>
|
||||
#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
|
||||
|
||||
#include <asm/arch/hardware.h>
|
||||
|
||||
#define BIT(x) (1 << x)
|
||||
#define CL_BIT(x) (0 << x)
|
||||
|
||||
/* Timer register bits */
|
||||
#define TCLR_ST BIT(0) /* Start=1 Stop=0 */
|
||||
#define TCLR_AR BIT(1) /* Auto reload */
|
||||
#define TCLR_PRE BIT(5) /* Pre-scaler enable */
|
||||
#define TCLR_PTV_SHIFT (2) /* Pre-scaler shift value */
|
||||
#define TCLR_PRE_DISABLE CL_BIT(5) /* Pre-scalar disable */
|
||||
|
||||
/* device type */
|
||||
#define DEVICE_MASK (BIT(8) | BIT(9) | BIT(10))
|
||||
#define TST_DEVICE 0x0
|
||||
#define EMU_DEVICE 0x1
|
||||
#define HS_DEVICE 0x2
|
||||
#define GP_DEVICE 0x3
|
||||
|
||||
/* cpu-id for AM33XX family */
|
||||
#define AM335X 0xB944
|
||||
#define DEVICE_ID 0x44E10600
|
||||
|
||||
/* This gives the status of the boot mode pins on the evm */
|
||||
#define SYSBOOT_MASK (BIT(0) | BIT(1) | BIT(2)\
|
||||
| BIT(3) | BIT(4))
|
||||
|
||||
/* Reset control */
|
||||
#ifdef CONFIG_AM335X
|
||||
#define PRM_RSTCTRL 0x44E00F00
|
||||
#endif
|
||||
#define PRM_RSTCTRL_RESET 0x01
|
||||
|
||||
#ifndef __KERNEL_STRICT_NAMES
|
||||
#ifndef __ASSEMBLY__
|
||||
/* Encapsulating core pll registers */
|
||||
struct cm_wkuppll {
|
||||
unsigned int wkclkstctrl; /* offset 0x00 */
|
||||
unsigned int wkctrlclkctrl; /* offset 0x04 */
|
||||
unsigned int resv1[1];
|
||||
unsigned int wkl4wkclkctrl; /* offset 0x0c */
|
||||
unsigned int resv2[4];
|
||||
unsigned int idlestdpllmpu; /* offset 0x20 */
|
||||
unsigned int resv3[2];
|
||||
unsigned int clkseldpllmpu; /* offset 0x2c */
|
||||
unsigned int resv4[1];
|
||||
unsigned int idlestdpllddr; /* offset 0x34 */
|
||||
unsigned int resv5[2];
|
||||
unsigned int clkseldpllddr; /* offset 0x40 */
|
||||
unsigned int resv6[4];
|
||||
unsigned int clkseldplldisp; /* offset 0x54 */
|
||||
unsigned int resv7[1];
|
||||
unsigned int idlestdpllcore; /* offset 0x5c */
|
||||
unsigned int resv8[2];
|
||||
unsigned int clkseldpllcore; /* offset 0x68 */
|
||||
unsigned int resv9[1];
|
||||
unsigned int idlestdpllper; /* offset 0x70 */
|
||||
unsigned int resv10[3];
|
||||
unsigned int divm4dpllcore; /* offset 0x80 */
|
||||
unsigned int divm5dpllcore; /* offset 0x84 */
|
||||
unsigned int clkmoddpllmpu; /* offset 0x88 */
|
||||
unsigned int clkmoddpllper; /* offset 0x8c */
|
||||
unsigned int clkmoddpllcore; /* offset 0x90 */
|
||||
unsigned int clkmoddpllddr; /* offset 0x94 */
|
||||
unsigned int clkmoddplldisp; /* offset 0x98 */
|
||||
unsigned int clkseldpllper; /* offset 0x9c */
|
||||
unsigned int divm2dpllddr; /* offset 0xA0 */
|
||||
unsigned int divm2dplldisp; /* offset 0xA4 */
|
||||
unsigned int divm2dpllmpu; /* offset 0xA8 */
|
||||
unsigned int divm2dpllper; /* offset 0xAC */
|
||||
unsigned int resv11[1];
|
||||
unsigned int wkup_uart0ctrl; /* offset 0xB4 */
|
||||
unsigned int resv12[8];
|
||||
unsigned int divm6dpllcore; /* offset 0xD8 */
|
||||
};
|
||||
|
||||
/**
|
||||
* Encapsulating peripheral functional clocks
|
||||
* pll registers
|
||||
*/
|
||||
struct cm_perpll {
|
||||
unsigned int l4lsclkstctrl; /* offset 0x00 */
|
||||
unsigned int l3sclkstctrl; /* offset 0x04 */
|
||||
unsigned int l4fwclkstctrl; /* offset 0x08 */
|
||||
unsigned int l3clkstctrl; /* offset 0x0c */
|
||||
unsigned int resv1[6];
|
||||
unsigned int emifclkctrl; /* offset 0x28 */
|
||||
unsigned int ocmcramclkctrl; /* offset 0x2c */
|
||||
unsigned int resv2[12];
|
||||
unsigned int l4lsclkctrl; /* offset 0x60 */
|
||||
unsigned int l4fwclkctrl; /* offset 0x64 */
|
||||
unsigned int resv3[6];
|
||||
unsigned int timer2clkctrl; /* offset 0x80 */
|
||||
unsigned int resv4[19];
|
||||
unsigned int emiffwclkctrl; /* offset 0xD0 */
|
||||
unsigned int resv5[2];
|
||||
unsigned int l3instrclkctrl; /* offset 0xDC */
|
||||
unsigned int l3clkctrl; /* Offset 0xE0 */
|
||||
unsigned int resv6[14];
|
||||
unsigned int l4hsclkstctrl; /* offset 0x11C */
|
||||
unsigned int l4hsclkctrl; /* offset 0x120 */
|
||||
};
|
||||
|
||||
/* Encapsulating Display pll registers */
|
||||
struct cm_dpll {
|
||||
unsigned int resv1[2];
|
||||
unsigned int clktimer2clk; /* offset 0x08 */
|
||||
};
|
||||
|
||||
/* Watchdog timer registers */
|
||||
struct wd_timer {
|
||||
unsigned int resv1[4];
|
||||
unsigned int wdtwdsc; /* offset 0x010 */
|
||||
unsigned int wdtwdst; /* offset 0x014 */
|
||||
unsigned int wdtwisr; /* offset 0x018 */
|
||||
unsigned int wdtwier; /* offset 0x01C */
|
||||
unsigned int wdtwwer; /* offset 0x020 */
|
||||
unsigned int wdtwclr; /* offset 0x024 */
|
||||
unsigned int wdtwcrr; /* offset 0x028 */
|
||||
unsigned int wdtwldr; /* offset 0x02C */
|
||||
unsigned int wdtwtgr; /* offset 0x030 */
|
||||
unsigned int wdtwwps; /* offset 0x034 */
|
||||
unsigned int resv2[3];
|
||||
unsigned int wdtwdly; /* offset 0x044 */
|
||||
unsigned int wdtwspr; /* offset 0x048 */
|
||||
unsigned int resv3[1];
|
||||
unsigned int wdtwqeoi; /* offset 0x050 */
|
||||
unsigned int wdtwqstar; /* offset 0x054 */
|
||||
unsigned int wdtwqsta; /* offset 0x058 */
|
||||
unsigned int wdtwqens; /* offset 0x05C */
|
||||
unsigned int wdtwqenc; /* offset 0x060 */
|
||||
unsigned int resv4[39];
|
||||
unsigned int wdt_unfr; /* offset 0x100 */
|
||||
};
|
||||
|
||||
/* Timer Registers */
|
||||
struct timer_reg {
|
||||
unsigned int resv1[4];
|
||||
unsigned int tiocpcfgreg; /* offset 0x10 */
|
||||
unsigned int resv2[9];
|
||||
unsigned int tclrreg; /* offset 0x38 */
|
||||
unsigned int tcrrreg; /* offset 0x3C */
|
||||
unsigned int tldrreg; /* offset 0x40 */
|
||||
unsigned int resv3[4];
|
||||
unsigned int tsicrreg; /* offset 0x54 */
|
||||
};
|
||||
|
||||
/* Timer 32 bit registers */
|
||||
struct gptimer {
|
||||
unsigned int tidr; /* offset 0x00 */
|
||||
unsigned int res1[0xc];
|
||||
unsigned int tiocp_cfg; /* offset 0x10 */
|
||||
unsigned int res2[0xc];
|
||||
unsigned int tier; /* offset 0x20 */
|
||||
unsigned int tistatr; /* offset 0x24 */
|
||||
unsigned int tistat; /* offset 0x28 */
|
||||
unsigned int tisr; /* offset 0x2c */
|
||||
unsigned int tcicr; /* offset 0x30 */
|
||||
unsigned int twer; /* offset 0x34 */
|
||||
unsigned int tclr; /* offset 0x38 */
|
||||
unsigned int tcrr; /* offset 0x3c */
|
||||
unsigned int tldr; /* offset 0x40 */
|
||||
unsigned int ttgr; /* offset 0x44 */
|
||||
unsigned int twpc; /* offset 0x48 */
|
||||
unsigned int tmar; /* offset 0x4c */
|
||||
unsigned int tcar1; /* offset 0x50 */
|
||||
unsigned int tscir; /* offset 0x54 */
|
||||
unsigned int tcar2; /* offset 0x58 */
|
||||
};
|
||||
|
||||
/* UART Registers */
|
||||
struct uart_sys {
|
||||
unsigned int resv1[21];
|
||||
unsigned int uartsyscfg; /* offset 0x54 */
|
||||
unsigned int uartsyssts; /* offset 0x58 */
|
||||
};
|
||||
|
||||
/* VTP Registers */
|
||||
struct vtp_reg {
|
||||
unsigned int vtp0ctrlreg;
|
||||
};
|
||||
|
||||
/* Control Status Register */
|
||||
struct ctrl_stat {
|
||||
unsigned int resv1[16];
|
||||
unsigned int statusreg; /* ofset 0x40 */
|
||||
};
|
||||
|
||||
void init_timer(void);
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __KERNEL_STRICT_NAMES */
|
||||
|
||||
#endif /* _AM33XX_CPU_H */
|
264
arch/arm/include/asm/arch-am33xx/ddr_defs.h
Normal file
264
arch/arm/include/asm/arch-am33xx/ddr_defs.h
Normal file
|
@ -0,0 +1,264 @@
|
|||
/*
|
||||
* ddr_defs.h
|
||||
*
|
||||
* ddr specific header
|
||||
*
|
||||
* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef _DDR_DEFS_H
|
||||
#define _DDR_DEFS_H
|
||||
|
||||
#include <asm/arch/hardware.h>
|
||||
|
||||
/* AM335X EMIF Register values */
|
||||
#define EMIF_SDMGT 0x80000000
|
||||
#define EMIF_SDRAM 0x00004650
|
||||
#define EMIF_PHYCFG 0x2
|
||||
#define DDR_PHY_RESET (0x1 << 10)
|
||||
#define DDR_FUNCTIONAL_MODE_EN 0x1
|
||||
#define DDR_PHY_READY (0x1 << 2)
|
||||
#define VTP_CTRL_READY (0x1 << 5)
|
||||
#define VTP_CTRL_ENABLE (0x1 << 6)
|
||||
#define VTP_CTRL_LOCK_EN (0x1 << 4)
|
||||
#define VTP_CTRL_START_EN (0x1)
|
||||
#define DDR2_RATIO 0x80
|
||||
#define CMD_FORCE 0x00
|
||||
#define CMD_DELAY 0x00
|
||||
|
||||
#define EMIF_READ_LATENCY 0x04
|
||||
#define EMIF_TIM1 0x0666B3D6
|
||||
#define EMIF_TIM2 0x143731DA
|
||||
#define EMIF_TIM3 0x00000347
|
||||
#define EMIF_SDCFG 0x43805332
|
||||
#define EMIF_SDREF 0x0000081a
|
||||
#define DDR2_DLL_LOCK_DIFF 0x0
|
||||
#define DDR2_RD_DQS 0x12
|
||||
#define DDR2_PHY_FIFO_WE 0x80
|
||||
|
||||
#define DDR2_INVERT_CLKOUT 0x00
|
||||
#define DDR2_WR_DQS 0x00
|
||||
#define DDR2_PHY_WRLVL 0x00
|
||||
#define DDR2_PHY_GATELVL 0x00
|
||||
#define DDR2_PHY_WR_DATA 0x40
|
||||
#define PHY_RANK0_DELAY 0x01
|
||||
#define PHY_DLL_LOCK_DIFF 0x0
|
||||
#define DDR_IOCTRL_VALUE 0x18B
|
||||
|
||||
/**
|
||||
* This structure represents the EMIF registers on AM33XX devices.
|
||||
*/
|
||||
struct emif_regs {
|
||||
unsigned int sdrrev; /* offset 0x00 */
|
||||
unsigned int sdrstat; /* offset 0x04 */
|
||||
unsigned int sdrcr; /* offset 0x08 */
|
||||
unsigned int sdrcr2; /* offset 0x0C */
|
||||
unsigned int sdrrcr; /* offset 0x10 */
|
||||
unsigned int sdrrcsr; /* offset 0x14 */
|
||||
unsigned int sdrtim1; /* offset 0x18 */
|
||||
unsigned int sdrtim1sr; /* offset 0x1C */
|
||||
unsigned int sdrtim2; /* offset 0x20 */
|
||||
unsigned int sdrtim2sr; /* offset 0x24 */
|
||||
unsigned int sdrtim3; /* offset 0x28 */
|
||||
unsigned int sdrtim3sr; /* offset 0x2C */
|
||||
unsigned int res1[2];
|
||||
unsigned int sdrmcr; /* offset 0x38 */
|
||||
unsigned int sdrmcsr; /* offset 0x3C */
|
||||
unsigned int res2[8];
|
||||
unsigned int sdritr; /* offset 0x60 */
|
||||
unsigned int res3[20];
|
||||
unsigned int ddrphycr; /* offset 0xE4 */
|
||||
unsigned int ddrphycsr; /* offset 0xE8 */
|
||||
unsigned int ddrphycr2; /* offset 0xEC */
|
||||
};
|
||||
|
||||
/**
|
||||
* Encapsulates DDR PHY control and corresponding shadow registers.
|
||||
*/
|
||||
struct ddr_phy_control {
|
||||
unsigned long reg;
|
||||
unsigned long reg_sh;
|
||||
unsigned long reg2;
|
||||
};
|
||||
|
||||
/**
|
||||
* Encapsulates SDRAM timing and corresponding shadow registers.
|
||||
*/
|
||||
struct sdram_timing {
|
||||
unsigned long time1;
|
||||
unsigned long time1_sh;
|
||||
unsigned long time2;
|
||||
unsigned long time2_sh;
|
||||
unsigned long time3;
|
||||
unsigned long time3_sh;
|
||||
};
|
||||
|
||||
/**
|
||||
* Encapsulates SDRAM configuration.
|
||||
* (Includes refresh control registers) */
|
||||
struct sdram_config {
|
||||
unsigned long sdrcr;
|
||||
unsigned long sdrcr2;
|
||||
unsigned long refresh;
|
||||
unsigned long refresh_sh;
|
||||
};
|
||||
|
||||
/**
|
||||
* Configure SDRAM
|
||||
*/
|
||||
int config_sdram(struct sdram_config *cfg);
|
||||
|
||||
/**
|
||||
* Set SDRAM timings
|
||||
*/
|
||||
int set_sdram_timings(struct sdram_timing *val);
|
||||
|
||||
/**
|
||||
* Configure DDR PHY
|
||||
*/
|
||||
int config_ddr_phy(struct ddr_phy_control *cfg);
|
||||
|
||||
/**
|
||||
* This structure represents the DDR registers on AM33XX devices.
|
||||
*/
|
||||
struct ddr_regs {
|
||||
unsigned int resv0[7];
|
||||
unsigned int cm0csratio; /* offset 0x01C */
|
||||
unsigned int cm0csforce; /* offset 0x020 */
|
||||
unsigned int cm0csdelay; /* offset 0x024 */
|
||||
unsigned int cm0dldiff; /* offset 0x028 */
|
||||
unsigned int cm0iclkout; /* offset 0x02C */
|
||||
unsigned int resv1[8];
|
||||
unsigned int cm1csratio; /* offset 0x050 */
|
||||
unsigned int cm1csforce; /* offset 0x054 */
|
||||
unsigned int cm1csdelay; /* offset 0x058 */
|
||||
unsigned int cm1dldiff; /* offset 0x05C */
|
||||
unsigned int cm1iclkout; /* offset 0x060 */
|
||||
unsigned int resv2[8];
|
||||
unsigned int cm2csratio; /* offset 0x084 */
|
||||
unsigned int cm2csforce; /* offset 0x088 */
|
||||
unsigned int cm2csdelay; /* offset 0x08C */
|
||||
unsigned int cm2dldiff; /* offset 0x090 */
|
||||
unsigned int cm2iclkout; /* offset 0x094 */
|
||||
unsigned int resv3[12];
|
||||
unsigned int dt0rdsratio0; /* offset 0x0C8 */
|
||||
unsigned int dt0rdsratio1; /* offset 0x0CC */
|
||||
unsigned int resv4[3];
|
||||
unsigned int dt0wdsratio0; /* offset 0x0DC */
|
||||
unsigned int dt0wdsratio1; /* offset 0x0E0 */
|
||||
unsigned int resv5[3];
|
||||
unsigned int dt0wiratio0; /* offset 0x0F0 */
|
||||
unsigned int dt0wiratio1; /* offset 0x0F4 */
|
||||
unsigned int dt0giratio0; /* offset 0x0FC */
|
||||
unsigned int dt0giratio1; /* offset 0x100 */
|
||||
unsigned int resv6[2];
|
||||
unsigned int dt0fwsratio0; /* offset 0x108 */
|
||||
unsigned int dt0fwsratio1; /* offset 0x10C */
|
||||
unsigned int resv7[5];
|
||||
unsigned int dt0wrsratio0; /* offset 0x120 */
|
||||
unsigned int dt0wrsratio1; /* offset 0x124 */
|
||||
unsigned int resv8[3];
|
||||
unsigned int dt0rdelays0; /* offset 0x134 */
|
||||
unsigned int dt0dldiff0; /* offset 0x138 */
|
||||
unsigned int resv9[39];
|
||||
unsigned int dt1rdelays0; /* offset 0x1D8 */
|
||||
};
|
||||
|
||||
/**
|
||||
* Encapsulates DDR CMD control registers.
|
||||
*/
|
||||
struct cmd_control {
|
||||
unsigned long cmd0csratio;
|
||||
unsigned long cmd0csforce;
|
||||
unsigned long cmd0csdelay;
|
||||
unsigned long cmd0dldiff;
|
||||
unsigned long cmd0iclkout;
|
||||
unsigned long cmd1csratio;
|
||||
unsigned long cmd1csforce;
|
||||
unsigned long cmd1csdelay;
|
||||
unsigned long cmd1dldiff;
|
||||
unsigned long cmd1iclkout;
|
||||
unsigned long cmd2csratio;
|
||||
unsigned long cmd2csforce;
|
||||
unsigned long cmd2csdelay;
|
||||
unsigned long cmd2dldiff;
|
||||
unsigned long cmd2iclkout;
|
||||
};
|
||||
|
||||
/**
|
||||
* Encapsulates DDR DATA registers.
|
||||
*/
|
||||
struct ddr_data {
|
||||
unsigned long datardsratio0;
|
||||
unsigned long datardsratio1;
|
||||
unsigned long datawdsratio0;
|
||||
unsigned long datawdsratio1;
|
||||
unsigned long datawiratio0;
|
||||
unsigned long datawiratio1;
|
||||
unsigned long datagiratio0;
|
||||
unsigned long datagiratio1;
|
||||
unsigned long datafwsratio0;
|
||||
unsigned long datafwsratio1;
|
||||
unsigned long datawrsratio0;
|
||||
unsigned long datawrsratio1;
|
||||
unsigned long datadldiff0;
|
||||
};
|
||||
|
||||
/**
|
||||
* Configure DDR CMD control registers
|
||||
*/
|
||||
int config_cmd_ctrl(struct cmd_control *cmd);
|
||||
|
||||
/**
|
||||
* Configure DDR DATA registers
|
||||
*/
|
||||
int config_ddr_data(int data_macrono, struct ddr_data *data);
|
||||
|
||||
/**
|
||||
* This structure represents the DDR io control on AM33XX devices.
|
||||
*/
|
||||
struct ddr_cmdtctrl {
|
||||
unsigned int resv1[1];
|
||||
unsigned int cm0ioctl;
|
||||
unsigned int cm1ioctl;
|
||||
unsigned int cm2ioctl;
|
||||
unsigned int resv2[12];
|
||||
unsigned int dt0ioctl;
|
||||
unsigned int dt1ioctl;
|
||||
};
|
||||
|
||||
/**
|
||||
* Encapsulates DDR CMD & DATA io control registers.
|
||||
*/
|
||||
struct ddr_ioctrl {
|
||||
unsigned long cmd1ctl;
|
||||
unsigned long cmd2ctl;
|
||||
unsigned long cmd3ctl;
|
||||
unsigned long data1ctl;
|
||||
unsigned long data2ctl;
|
||||
};
|
||||
|
||||
/**
|
||||
* Configure DDR io control registers
|
||||
*/
|
||||
int config_io_ctrl(struct ddr_ioctrl *ioctrl);
|
||||
|
||||
struct ddr_ctrl {
|
||||
unsigned int ddrioctrl;
|
||||
unsigned int resv1[325];
|
||||
unsigned int ddrckectrl;
|
||||
};
|
||||
|
||||
void config_ddr(void);
|
||||
|
||||
#endif /* _DDR_DEFS_H */
|
81
arch/arm/include/asm/arch-am33xx/hardware.h
Normal file
81
arch/arm/include/asm/arch-am33xx/hardware.h
Normal file
|
@ -0,0 +1,81 @@
|
|||
/*
|
||||
* hardware.h
|
||||
*
|
||||
* hardware specific header
|
||||
*
|
||||
* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef __AM33XX_HARDWARE_H
|
||||
#define __AM33XX_HARDWARE_H
|
||||
|
||||
/* Module base addresses */
|
||||
#define LOW_LEVEL_SRAM_STACK 0x4030B7FC
|
||||
#define UART0_BASE 0x44E09000
|
||||
|
||||
/* DM Timer base addresses */
|
||||
#define DM_TIMER0_BASE 0x4802C000
|
||||
#define DM_TIMER1_BASE 0x4802E000
|
||||
#define DM_TIMER2_BASE 0x48040000
|
||||
#define DM_TIMER3_BASE 0x48042000
|
||||
#define DM_TIMER4_BASE 0x48044000
|
||||
#define DM_TIMER5_BASE 0x48046000
|
||||
#define DM_TIMER6_BASE 0x48048000
|
||||
#define DM_TIMER7_BASE 0x4804A000
|
||||
|
||||
/* GPIO Base address */
|
||||
#define GPIO0_BASE 0x48032000
|
||||
#define GPIO1_BASE 0x4804C000
|
||||
#define GPIO2_BASE 0x481AC000
|
||||
|
||||
/* BCH Error Location Module */
|
||||
#define ELM_BASE 0x48080000
|
||||
|
||||
/* Watchdog Timer */
|
||||
#define WDT_BASE 0x44E35000
|
||||
|
||||
/* Control Module Base Address */
|
||||
#define CTRL_BASE 0x44E10000
|
||||
|
||||
/* PRCM Base Address */
|
||||
#define PRCM_BASE 0x44E00000
|
||||
|
||||
/* EMIF Base address */
|
||||
#define EMIF4_0_CFG_BASE 0x4C000000
|
||||
#define EMIF4_1_CFG_BASE 0x4D000000
|
||||
#define DMM_BASE 0x4E000000
|
||||
|
||||
/* PLL related registers */
|
||||
#define CM_PER 0x44E00000
|
||||
#define CM_WKUP 0x44E00400
|
||||
#define CM_DPLL 0x44E00500
|
||||
#define CM_DEVICE 0x44E00700
|
||||
#define CM_CEFUSE 0x44E00A00
|
||||
#define PRM_DEVICE 0x44E00F00
|
||||
|
||||
/* VTP Base address */
|
||||
#define VTP0_CTRL_ADDR 0x44E10E0C
|
||||
|
||||
/* DDR Base address */
|
||||
#define DDR_CTRL_ADDR 0x44E10E04
|
||||
#define DDR_CONTROL_BASE_ADDR 0x44E11404
|
||||
#define DDR_PHY_BASE_ADDR 0x44E12000
|
||||
#define DDR_PHY_BASE_ADDR2 0x44E120A4
|
||||
|
||||
/* UART */
|
||||
#define DEFAULT_UART_BASE UART0_BASE
|
||||
|
||||
#define DDRPHY_0_CONFIG_BASE (CTRL_BASE + 0x1400)
|
||||
#define DDRPHY_CONFIG_BASE DDRPHY_0_CONFIG_BASE
|
||||
|
||||
#endif /* __AM33XX_HARDWARE_H */
|
39
arch/arm/include/asm/arch-am33xx/sys_proto.h
Normal file
39
arch/arm/include/asm/arch-am33xx/sys_proto.h
Normal file
|
@ -0,0 +1,39 @@
|
|||
/*
|
||||
* sys_proto.h
|
||||
*
|
||||
* System information header
|
||||
*
|
||||
* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef _SYS_PROTO_H_
|
||||
#define _SYS_PROTO_H_
|
||||
|
||||
#define BOARD_REV_ID 0x0
|
||||
struct {
|
||||
u32 board_type_v1;
|
||||
u32 board_type_v2;
|
||||
u32 mtype;
|
||||
char *board_string;
|
||||
char *nand_string;
|
||||
} board_sysinfo;
|
||||
|
||||
u32 get_cpu_rev(void);
|
||||
u32 get_sysboot_value(void);
|
||||
|
||||
#ifdef CONFIG_DISPLAY_CPUINFO
|
||||
int print_cpuinfo(void);
|
||||
#endif
|
||||
|
||||
u32 get_device_type(void);
|
||||
#endif
|
|
@ -26,13 +26,7 @@
|
|||
#ifndef _ASM_ARCH_ARMADA100_H
|
||||
#define _ASM_ARCH_ARMADA100_H
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#include <asm/types.h>
|
||||
#include <asm/io.h>
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#if defined (CONFIG_ARMADA100)
|
||||
#include <asm/arch/cpu.h>
|
||||
|
||||
/* Common APB clock register bit definitions */
|
||||
#define APBC_APBCLK (1<<0) /* APB Bus Clock Enable */
|
||||
|
@ -45,6 +39,10 @@
|
|||
#define FE_CLK_RST 0x1
|
||||
#define FE_CLK_ENA 0x8
|
||||
|
||||
/* SSP2 Clock Control */
|
||||
#define SSP2_APBCLK 0x01
|
||||
#define SSP2_FNCLK 0x02
|
||||
|
||||
/* Register Base Addresses */
|
||||
#define ARMD1_DRAM_BASE 0xB0000000
|
||||
#define ARMD1_FEC_BASE 0xC0800000
|
||||
|
@ -65,115 +63,5 @@
|
|||
#define ARMD1_APMU_BASE 0xD4282800
|
||||
#define ARMD1_CPU_BASE 0xD4282C00
|
||||
|
||||
/*
|
||||
* Main Power Management (MPMU) Registers
|
||||
* Refer Datasheet Appendix A.8
|
||||
*/
|
||||
struct armd1mpmu_registers {
|
||||
u8 pad0[0x08 - 0x00];
|
||||
u32 fccr; /*0x0008*/
|
||||
u32 pocr; /*0x000c*/
|
||||
u32 posr; /*0x0010*/
|
||||
u32 succr; /*0x0014*/
|
||||
u8 pad1[0x030 - 0x014 - 4];
|
||||
u32 gpcr; /*0x0030*/
|
||||
u8 pad2[0x200 - 0x030 - 4];
|
||||
u32 wdtpcr; /*0x0200*/
|
||||
u8 pad3[0x1000 - 0x200 - 4];
|
||||
u32 apcr; /*0x1000*/
|
||||
u32 apsr; /*0x1004*/
|
||||
u8 pad4[0x1020 - 0x1004 - 4];
|
||||
u32 aprr; /*0x1020*/
|
||||
u32 acgr; /*0x1024*/
|
||||
u32 arsr; /*0x1028*/
|
||||
};
|
||||
|
||||
/*
|
||||
* Application Subsystem Power Management
|
||||
* Refer Datasheet Appendix A.9
|
||||
*/
|
||||
struct armd1apmu_registers {
|
||||
u32 pcr; /* 0x000 */
|
||||
u32 ccr; /* 0x004 */
|
||||
u32 pad1;
|
||||
u32 ccsr; /* 0x00C */
|
||||
u32 fc_timer; /* 0x010 */
|
||||
u32 pad2;
|
||||
u32 ideal_cfg; /* 0x018 */
|
||||
u8 pad3[0x04C - 0x018 - 4];
|
||||
u32 lcdcrc; /* 0x04C */
|
||||
u32 cciccrc; /* 0x050 */
|
||||
u32 sd1crc; /* 0x054 */
|
||||
u32 sd2crc; /* 0x058 */
|
||||
u32 usbcrc; /* 0x05C */
|
||||
u32 nfccrc; /* 0x060 */
|
||||
u32 dmacrc; /* 0x064 */
|
||||
u32 pad4;
|
||||
u32 buscrc; /* 0x06C */
|
||||
u8 pad5[0x07C - 0x06C - 4];
|
||||
u32 wake_clr; /* 0x07C */
|
||||
u8 pad6[0x090 - 0x07C - 4];
|
||||
u32 core_status; /* 0x090 */
|
||||
u32 rfsc; /* 0x094 */
|
||||
u32 imr; /* 0x098 */
|
||||
u32 irwc; /* 0x09C */
|
||||
u32 isr; /* 0x0A0 */
|
||||
u8 pad7[0x0B0 - 0x0A0 - 4];
|
||||
u32 mhst; /* 0x0B0 */
|
||||
u32 msr; /* 0x0B4 */
|
||||
u8 pad8[0x0C0 - 0x0B4 - 4];
|
||||
u32 msst; /* 0x0C0 */
|
||||
u32 pllss; /* 0x0C4 */
|
||||
u32 smb; /* 0x0C8 */
|
||||
u32 gccrc; /* 0x0CC */
|
||||
u8 pad9[0x0D4 - 0x0CC - 4];
|
||||
u32 smccrc; /* 0x0D4 */
|
||||
u32 pad10;
|
||||
u32 xdcrc; /* 0x0DC */
|
||||
u32 sd3crc; /* 0x0E0 */
|
||||
u32 sd4crc; /* 0x0E4 */
|
||||
u8 pad11[0x0F0 - 0x0E4 - 4];
|
||||
u32 cfcrc; /* 0x0F0 */
|
||||
u32 mspcrc; /* 0x0F4 */
|
||||
u32 cmucrc; /* 0x0F8 */
|
||||
u32 fecrc; /* 0x0FC */
|
||||
u32 pciecrc; /* 0x100 */
|
||||
u32 epdcrc; /* 0x104 */
|
||||
};
|
||||
|
||||
/*
|
||||
* APB1 Clock Reset/Control Registers
|
||||
* Refer Datasheet Appendix A.10
|
||||
*/
|
||||
struct armd1apb1_registers {
|
||||
u32 uart1; /*0x000*/
|
||||
u32 uart2; /*0x004*/
|
||||
u32 gpio; /*0x008*/
|
||||
u32 pwm1; /*0x00c*/
|
||||
u32 pwm2; /*0x010*/
|
||||
u32 pwm3; /*0x014*/
|
||||
u32 pwm4; /*0x018*/
|
||||
u8 pad0[0x028 - 0x018 - 4];
|
||||
u32 rtc; /*0x028*/
|
||||
u32 twsi0; /*0x02c*/
|
||||
u32 kpc; /*0x030*/
|
||||
u32 timers; /*0x034*/
|
||||
u8 pad1[0x03c - 0x034 - 4];
|
||||
u32 aib; /*0x03c*/
|
||||
u32 sw_jtag; /*0x040*/
|
||||
u32 timer1; /*0x044*/
|
||||
u32 onewire; /*0x048*/
|
||||
u8 pad2[0x050 - 0x048 - 4];
|
||||
u32 asfar; /*0x050 AIB Secure First Access Reg*/
|
||||
u32 assar; /*0x054 AIB Secure Second Access Reg*/
|
||||
u8 pad3[0x06c - 0x054 - 4];
|
||||
u32 twsi1; /*0x06c*/
|
||||
u32 uart3; /*0x070*/
|
||||
u8 pad4[0x07c - 0x070 - 4];
|
||||
u32 timer2; /*0x07C*/
|
||||
u8 pad5[0x084 - 0x07c - 4];
|
||||
u32 ac97; /*0x084*/
|
||||
};
|
||||
|
||||
#endif /* CONFIG_ARMADA100 */
|
||||
#endif /* _ASM_ARCH_ARMADA100_H */
|
||||
|
|
|
@ -31,6 +31,7 @@
|
|||
#ifndef _ARMD1_CONFIG_H
|
||||
#define _ARMD1_CONFIG_H
|
||||
|
||||
#include <asm/arch/armada100.h>
|
||||
#define CONFIG_ARM926EJS 1 /* Basic Architecture */
|
||||
|
||||
#define CONFIG_SYS_TCLK (14745600) /* NS16550 clk config */
|
||||
|
|
|
@ -28,6 +28,131 @@
|
|||
#include <asm/io.h>
|
||||
#include <asm/system.h>
|
||||
|
||||
/*
|
||||
* Main Power Management (MPMU) Registers
|
||||
* Refer Datasheet Appendix A.8
|
||||
*/
|
||||
struct armd1mpmu_registers {
|
||||
u8 pad0[0x08 - 0x00];
|
||||
u32 fccr; /*0x0008*/
|
||||
u32 pocr; /*0x000c*/
|
||||
u32 posr; /*0x0010*/
|
||||
u32 succr; /*0x0014*/
|
||||
u8 pad1[0x030 - 0x014 - 4];
|
||||
u32 gpcr; /*0x0030*/
|
||||
u8 pad2[0x200 - 0x030 - 4];
|
||||
u32 wdtpcr; /*0x0200*/
|
||||
u8 pad3[0x1000 - 0x200 - 4];
|
||||
u32 apcr; /*0x1000*/
|
||||
u32 apsr; /*0x1004*/
|
||||
u8 pad4[0x1020 - 0x1004 - 4];
|
||||
u32 aprr; /*0x1020*/
|
||||
u32 acgr; /*0x1024*/
|
||||
u32 arsr; /*0x1028*/
|
||||
};
|
||||
|
||||
/*
|
||||
* Application Subsystem Power Management
|
||||
* Refer Datasheet Appendix A.9
|
||||
*/
|
||||
struct armd1apmu_registers {
|
||||
u32 pcr; /* 0x000 */
|
||||
u32 ccr; /* 0x004 */
|
||||
u32 pad1;
|
||||
u32 ccsr; /* 0x00C */
|
||||
u32 fc_timer; /* 0x010 */
|
||||
u32 pad2;
|
||||
u32 ideal_cfg; /* 0x018 */
|
||||
u8 pad3[0x04C - 0x018 - 4];
|
||||
u32 lcdcrc; /* 0x04C */
|
||||
u32 cciccrc; /* 0x050 */
|
||||
u32 sd1crc; /* 0x054 */
|
||||
u32 sd2crc; /* 0x058 */
|
||||
u32 usbcrc; /* 0x05C */
|
||||
u32 nfccrc; /* 0x060 */
|
||||
u32 dmacrc; /* 0x064 */
|
||||
u32 pad4;
|
||||
u32 buscrc; /* 0x06C */
|
||||
u8 pad5[0x07C - 0x06C - 4];
|
||||
u32 wake_clr; /* 0x07C */
|
||||
u8 pad6[0x090 - 0x07C - 4];
|
||||
u32 core_status; /* 0x090 */
|
||||
u32 rfsc; /* 0x094 */
|
||||
u32 imr; /* 0x098 */
|
||||
u32 irwc; /* 0x09C */
|
||||
u32 isr; /* 0x0A0 */
|
||||
u8 pad7[0x0B0 - 0x0A0 - 4];
|
||||
u32 mhst; /* 0x0B0 */
|
||||
u32 msr; /* 0x0B4 */
|
||||
u8 pad8[0x0C0 - 0x0B4 - 4];
|
||||
u32 msst; /* 0x0C0 */
|
||||
u32 pllss; /* 0x0C4 */
|
||||
u32 smb; /* 0x0C8 */
|
||||
u32 gccrc; /* 0x0CC */
|
||||
u8 pad9[0x0D4 - 0x0CC - 4];
|
||||
u32 smccrc; /* 0x0D4 */
|
||||
u32 pad10;
|
||||
u32 xdcrc; /* 0x0DC */
|
||||
u32 sd3crc; /* 0x0E0 */
|
||||
u32 sd4crc; /* 0x0E4 */
|
||||
u8 pad11[0x0F0 - 0x0E4 - 4];
|
||||
u32 cfcrc; /* 0x0F0 */
|
||||
u32 mspcrc; /* 0x0F4 */
|
||||
u32 cmucrc; /* 0x0F8 */
|
||||
u32 fecrc; /* 0x0FC */
|
||||
u32 pciecrc; /* 0x100 */
|
||||
u32 epdcrc; /* 0x104 */
|
||||
};
|
||||
|
||||
/*
|
||||
* APB1 Clock Reset/Control Registers
|
||||
* Refer Datasheet Appendix A.10
|
||||
*/
|
||||
struct armd1apb1_registers {
|
||||
u32 uart1; /*0x000*/
|
||||
u32 uart2; /*0x004*/
|
||||
u32 gpio; /*0x008*/
|
||||
u32 pwm1; /*0x00c*/
|
||||
u32 pwm2; /*0x010*/
|
||||
u32 pwm3; /*0x014*/
|
||||
u32 pwm4; /*0x018*/
|
||||
u8 pad0[0x028 - 0x018 - 4];
|
||||
u32 rtc; /*0x028*/
|
||||
u32 twsi0; /*0x02c*/
|
||||
u32 kpc; /*0x030*/
|
||||
u32 timers; /*0x034*/
|
||||
u8 pad1[0x03c - 0x034 - 4];
|
||||
u32 aib; /*0x03c*/
|
||||
u32 sw_jtag; /*0x040*/
|
||||
u32 timer1; /*0x044*/
|
||||
u32 onewire; /*0x048*/
|
||||
u8 pad2[0x050 - 0x048 - 4];
|
||||
u32 asfar; /*0x050 AIB Secure First Access Reg*/
|
||||
u32 assar; /*0x054 AIB Secure Second Access Reg*/
|
||||
u8 pad3[0x06c - 0x054 - 4];
|
||||
u32 twsi1; /*0x06c*/
|
||||
u32 uart3; /*0x070*/
|
||||
u8 pad4[0x07c - 0x070 - 4];
|
||||
u32 timer2; /*0x07C*/
|
||||
u8 pad5[0x084 - 0x07c - 4];
|
||||
u32 ac97; /*0x084*/
|
||||
};
|
||||
|
||||
/*
|
||||
* APB2 Clock Reset/Control Registers
|
||||
* Refer Datasheet Appendix A.11
|
||||
*/
|
||||
struct armd1apb2_registers {
|
||||
u32 pad1[0x01C - 0x000];
|
||||
u32 ssp1_clkrst; /* 0x01C */
|
||||
u32 ssp2_clkrst; /* 0x020 */
|
||||
u32 pad2[0x04C - 0x020 - 4];
|
||||
u32 ssp3_clkrst; /* 0x04C */
|
||||
u32 pad3[0x058 - 0x04C - 4];
|
||||
u32 ssp4_clkrst; /* 0x058 */
|
||||
u32 ssp5_clkrst; /* 0x05C */
|
||||
};
|
||||
|
||||
/*
|
||||
* CPU Interface Registers
|
||||
* Refer Datasheet Appendix A.2
|
||||
|
|
|
@ -83,6 +83,12 @@
|
|||
#define MFP101_ETH_MDIO (MFP_REG(0x194) | MFP_AF5 | MFP_DRIVE_MEDIUM)
|
||||
#define MFP103_ETH_RXDV (MFP_REG(0x19C) | MFP_AF5 | MFP_DRIVE_MEDIUM)
|
||||
|
||||
/* SPI */
|
||||
#define MFP107_SSP2_RXD (MFP_REG(0x1AC) | MFP_AF4 | MFP_DRIVE_MEDIUM)
|
||||
#define MFP108_SSP2_TXD (MFP_REG(0x1B0) | MFP_AF4 | MFP_DRIVE_MEDIUM)
|
||||
#define MFP110_SSP2_CS (MFP_REG(0x1B8) | MFP_AF0 | MFP_DRIVE_MEDIUM)
|
||||
#define MFP111_SSP2_CLK (MFP_REG(0x1BC) | MFP_AF4 | MFP_DRIVE_MEDIUM)
|
||||
|
||||
/* More macros can be defined here... */
|
||||
|
||||
#define MFP_PIN_MAX 117
|
||||
|
|
95
arch/arm/include/asm/arch-armada100/spi.h
Normal file
95
arch/arm/include/asm/arch-armada100/spi.h
Normal file
|
@ -0,0 +1,95 @@
|
|||
/*
|
||||
* (C) Copyright 2011
|
||||
* eInfochips Ltd. <www.einfochips.com>
|
||||
* Written-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
|
||||
*
|
||||
* (C) Copyright 2010
|
||||
* Marvell Semiconductor <www.marvell.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
|
||||
* MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#ifndef __ARMADA100_SPI_H_
|
||||
#define __ARMADA100_SPI_H_
|
||||
|
||||
#include <asm/arch/armada100.h>
|
||||
|
||||
#define CAT_BASE_ADDR(x) ARMD1_SSP ## x ## _BASE
|
||||
#define SSP_REG_BASE(x) CAT_BASE_ADDR(x)
|
||||
|
||||
/*
|
||||
* SSP Serial Port Registers
|
||||
* refer Appendix A.26
|
||||
*/
|
||||
struct ssp_reg {
|
||||
u32 sscr0; /* SSP Control Register 0 - 0x000 */
|
||||
u32 sscr1; /* SSP Control Register 1 - 0x004 */
|
||||
u32 sssr; /* SSP Status Register - 0x008 */
|
||||
u32 ssitr; /* SSP Interrupt Test Register - 0x00C */
|
||||
u32 ssdr; /* SSP Data Register - 0x010 */
|
||||
u32 pad1[5];
|
||||
u32 ssto; /* SSP Timeout Register - 0x028 */
|
||||
u32 sspsp; /* SSP Programmable Serial Protocol Register - 0x02C */
|
||||
u32 sstsa; /* SSP TX Timeslot Active Register - 0x030 */
|
||||
u32 ssrsa; /* SSP RX Timeslot Active Register - 0x034 */
|
||||
u32 sstss; /* SSP Timeslot Status Register - 0x038 */
|
||||
};
|
||||
|
||||
#define DEFAULT_WORD_LEN 8
|
||||
#define SSP_FLUSH_NUM 0x2000
|
||||
#define RX_THRESH_DEF 8
|
||||
#define TX_THRESH_DEF 8
|
||||
#define TIMEOUT_DEF 1000
|
||||
|
||||
#define SSCR1_RIE (1 << 0) /* Receive FIFO Interrupt Enable */
|
||||
#define SSCR1_TIE (1 << 1) /* Transmit FIFO Interrupt Enable */
|
||||
#define SSCR1_LBM (1 << 2) /* Loop-Back Mode */
|
||||
#define SSCR1_SPO (1 << 3) /* Motorola SPI SSPSCLK polarity
|
||||
setting */
|
||||
#define SSCR1_SPH (1 << 4) /* Motorola SPI SSPSCLK phase setting */
|
||||
#define SSCR1_MWDS (1 << 5) /* Microwire Transmit Data Size */
|
||||
#define SSCR1_TFT 0x03c0 /* Transmit FIFO Threshold (mask) */
|
||||
#define SSCR1_RFT 0x3c00 /* Receive FIFO Threshold (mask) */
|
||||
|
||||
#define SSCR1_TXTRESH(x) ((x - 1) << 6) /* level [1..16] */
|
||||
#define SSCR1_RXTRESH(x) ((x - 1) << 10) /* level [1..16] */
|
||||
#define SSCR1_TINTE (1 << 19) /* Receiver Time-out
|
||||
Interrupt enable */
|
||||
|
||||
#define SSCR0_DSS 0x0f /* Data Size Select (mask) */
|
||||
#define SSCR0_DATASIZE(x) (x - 1) /* Data Size Select [4..16] */
|
||||
#define SSCR0_FRF 0x30 /* FRame Format (mask) */
|
||||
#define SSCR0_MOTO (0x0 << 4) /* Motorola's Serial
|
||||
Peripheral Interface */
|
||||
#define SSCR0_TI (0x1 << 4) /* TI's Synchronous
|
||||
Serial Protocol (SSP) */
|
||||
#define SSCR0_NATIONAL (0x2 << 4) /* National Microwire */
|
||||
#define SSCR0_ECS (1 << 6) /* External clock select */
|
||||
#define SSCR0_SSE (1 << 7) /* Synchronous Serial Port
|
||||
Enable */
|
||||
|
||||
#define SSSR_TNF (1 << 2) /* Transmit FIFO Not Full */
|
||||
#define SSSR_RNE (1 << 3) /* Receive FIFO Not Empty */
|
||||
#define SSSR_BSY (1 << 4) /* SSP Busy */
|
||||
#define SSSR_TFS (1 << 5) /* Transmit FIFO Service Request */
|
||||
#define SSSR_RFS (1 << 6) /* Receive FIFO Service Request */
|
||||
#define SSSR_ROR (1 << 7) /* Receive FIFO Overrun */
|
||||
#define SSSR_TINT (1 << 19) /* Receiver Time-out Interrupt */
|
||||
|
||||
#endif /* __ARMADA100_SPI_H_ */
|
|
@ -84,10 +84,6 @@
|
|||
#define EMAC_MDIO_CLOCK_FREQ 2000000 /* 2.0 MHz */
|
||||
#endif
|
||||
|
||||
/* PHY mask - set only those phy number bits where phy is/can be connected */
|
||||
#define EMAC_MDIO_PHY_NUM CONFIG_EMAC_MDIO_PHY_NUM
|
||||
#define EMAC_MDIO_PHY_MASK (1 << EMAC_MDIO_PHY_NUM)
|
||||
|
||||
/* Ethernet Min/Max packet size */
|
||||
#define EMAC_MIN_ETHERNET_PKT_SIZE 60
|
||||
#define EMAC_MAX_ETHERNET_PKT_SIZE 1518
|
||||
|
|
|
@ -260,6 +260,7 @@ typedef volatile unsigned int * dv_reg_p;
|
|||
#define DAVINCI_LPSC_UART2 (DAVINCI_LPSC_PSC1_BASE + 13)
|
||||
#define DAVINCI_LPSC_LCDC (DAVINCI_LPSC_PSC1_BASE + 16)
|
||||
#define DAVINCI_LPSC_ePWM (DAVINCI_LPSC_PSC1_BASE + 17)
|
||||
#define DAVINCI_LPSC_MMCSD1 (DAVINCI_LPSC_PSC1_BASE + 18)
|
||||
#define DAVINCI_LPSC_eCAP (DAVINCI_LPSC_PSC1_BASE + 20)
|
||||
#define DAVINCI_LPSC_L3_CBA_RAM (DAVINCI_LPSC_PSC1_BASE + 31)
|
||||
|
||||
|
@ -356,6 +357,8 @@ struct davinci_psc_regs {
|
|||
|
||||
#endif /* CONFIG_SOC_DA8XX */
|
||||
|
||||
#define PSC_MDSTAT_STATE 0x3f
|
||||
|
||||
#ifndef CONFIG_SOC_DA8XX
|
||||
|
||||
/* Miscellania... */
|
||||
|
|
|
@ -39,6 +39,7 @@
|
|||
#error "SOC Name not defined"
|
||||
#endif /* CONFIG_KW88F6281 */
|
||||
|
||||
#include <asm/arch/kirkwood.h>
|
||||
#define CONFIG_ARM926EJS 1 /* Basic Architecture */
|
||||
|
||||
#define CONFIG_MD5 /* get_random_hex on krikwood needs MD5 support */
|
||||
|
|
|
@ -27,13 +27,7 @@
|
|||
#ifndef _ASM_ARCH_KIRKWOOD_H
|
||||
#define _ASM_ARCH_KIRKWOOD_H
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#include <asm/types.h>
|
||||
#include <asm/io.h>
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#if defined (CONFIG_FEROCEON_88FR131) || defined (CONFIG_SHEEVA_88SV131)
|
||||
#include <asm/arch/cpu.h>
|
||||
|
||||
/* SOC specific definations */
|
||||
#define INTREG_BASE 0xd0000000
|
||||
|
|
|
@ -472,6 +472,18 @@ enum iomux_pins {
|
|||
#define CCM_RCSR_NF16B (1 << 31)
|
||||
#define CCM_RCSR_NFMS (1 << 30)
|
||||
|
||||
/* WEIM CS control registers */
|
||||
struct mx31_weim_cscr {
|
||||
u32 upper;
|
||||
u32 lower;
|
||||
u32 additional;
|
||||
u32 reserved;
|
||||
};
|
||||
|
||||
struct mx31_weim {
|
||||
struct mx31_weim_cscr cscr[6];
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
#define __REG(x) (*((volatile u32 *)(x)))
|
||||
|
@ -550,10 +562,27 @@ enum iomux_pins {
|
|||
#define ESDCTL_BL(x) ((x) << 7)
|
||||
#define ESDCTL_PRCT(x) ((x) << 0)
|
||||
|
||||
/* 13 fields of the upper CS control register */
|
||||
#define CSCR_U(sp, wp, bcd, bcs, psz, pme, sync, dol, \
|
||||
cnc, wsc, ew, wws, edc) \
|
||||
((sp) << 31 | (wp) << 30 | (bcd) << 28 | (psz) << 22 | (pme) << 21 |\
|
||||
(sync) << 20 | (dol) << 16 | (cnc) << 14 | (wsc) << 8 | (ew) << 7 |\
|
||||
(wws) << 4 | (edc) << 0)
|
||||
/* 12 fields of the lower CS control register */
|
||||
#define CSCR_L(oea, oen, ebwa, ebwn, \
|
||||
csa, ebc, dsz, csn, psr, cre, wrap, csen) \
|
||||
((oea) << 28 | (oen) << 24 | (ebwa) << 20 | (ebwn) << 16 |\
|
||||
(csa) << 12 | (ebc) << 11 | (dsz) << 8 | (csn) << 4 |\
|
||||
(psr) << 3 | (cre) << 2 | (wrap) << 1 | (csen) << 0)
|
||||
/* 14 fields of the additional CS control register */
|
||||
#define CSCR_A(ebra, ebrn, rwa, rwn, mum, lah, lbn, lba, dww, dct, \
|
||||
wwu, age, cnc2, fce) \
|
||||
((ebra) << 28 | (ebrn) << 24 | (rwa) << 20 | (rwn) << 16 |\
|
||||
(mum) << 15 | (lah) << 13 | (lbn) << 10 | (lba) << 8 |\
|
||||
(dww) << 6 | (dct) << 4 | (wwu) << 3 |\
|
||||
(age) << 2 | (cnc2) << 1 | (fce) << 0)
|
||||
|
||||
#define WEIM_BASE 0xb8002000
|
||||
#define CSCR_U(x) (WEIM_BASE + (x) * 0x10)
|
||||
#define CSCR_L(x) (WEIM_BASE + 4 + (x) * 0x10)
|
||||
#define CSCR_A(x) (WEIM_BASE + 8 + (x) * 0x10)
|
||||
|
||||
#define IOMUXC_BASE 0x43FAC000
|
||||
#define IOMUXC_GPR (IOMUXC_BASE + 0x8)
|
||||
|
|
35
arch/arm/include/asm/arch-mx31/sys_proto.h
Normal file
35
arch/arm/include/asm/arch-mx31/sys_proto.h
Normal file
|
@ -0,0 +1,35 @@
|
|||
/*
|
||||
* (C) Copyright 2011
|
||||
* Helmut Raiger, HALE electronic GmbH, helmut.raiger@hale.at
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef _SYS_PROTO_H_
|
||||
#define _SYS_PROTO_H_
|
||||
|
||||
struct mxc_weimcs {
|
||||
u32 upper;
|
||||
u32 lower;
|
||||
u32 additional;
|
||||
};
|
||||
|
||||
void mxc_setup_weimcs(int cs, const struct mxc_weimcs *weimcs);
|
||||
|
||||
#endif
|
|
@ -28,4 +28,12 @@ u32 get_cpu_rev(void);
|
|||
#define is_soc_rev(rev) ((get_cpu_rev() & 0xFF) - rev)
|
||||
void sdelay(unsigned long);
|
||||
void set_chipselect_size(int const);
|
||||
|
||||
/*
|
||||
* Initializes on-chip ethernet controllers.
|
||||
* to override, implement board_eth_init()
|
||||
*/
|
||||
|
||||
int fecmxc_initialize(bd_t *bis);
|
||||
|
||||
#endif
|
||||
|
|
|
@ -218,6 +218,7 @@ struct sdrc {
|
|||
|
||||
/* EMIF4 */
|
||||
typedef struct emif4 {
|
||||
unsigned int emif_mod_id_rev;
|
||||
unsigned int sdram_sts;
|
||||
unsigned int sdram_config;
|
||||
unsigned int res1;
|
||||
|
@ -282,6 +283,51 @@ typedef struct emif4 {
|
|||
#define SMART_IDLE (0x2 << 3)
|
||||
#define REF_ON_IDLE (0x1 << 6)
|
||||
|
||||
/* DMA */
|
||||
#ifndef __KERNEL_STRICT_NAMES
|
||||
#ifndef __ASSEMBLY__
|
||||
struct dma4_chan {
|
||||
u32 ccr;
|
||||
u32 clnk_ctrl;
|
||||
u32 cicr;
|
||||
u32 csr;
|
||||
u32 csdp;
|
||||
u32 cen;
|
||||
u32 cfn;
|
||||
u32 cssa;
|
||||
u32 cdsa;
|
||||
u32 csel;
|
||||
u32 csfl;
|
||||
u32 cdel;
|
||||
u32 cdfl;
|
||||
u32 csac;
|
||||
u32 cdac;
|
||||
u32 ccen;
|
||||
u32 ccfn;
|
||||
u32 color;
|
||||
};
|
||||
|
||||
struct dma4 {
|
||||
u32 revision;
|
||||
u8 res1[0x4];
|
||||
u32 irqstatus_l[0x4];
|
||||
u32 irqenable_l[0x4];
|
||||
u32 sysstatus;
|
||||
u32 ocp_sysconfig;
|
||||
u8 res2[0x34];
|
||||
u32 caps_0;
|
||||
u8 res3[0x4];
|
||||
u32 caps_2;
|
||||
u32 caps_3;
|
||||
u32 caps_4;
|
||||
u32 gcr;
|
||||
u8 res4[0x4];
|
||||
struct dma4_chan chan[32];
|
||||
};
|
||||
|
||||
#endif /*__ASSEMBLY__ */
|
||||
#endif /* __KERNEL_STRICT_NAMES */
|
||||
|
||||
/* timer regs offsets (32 bit regs) */
|
||||
|
||||
#ifndef __KERNEL_STRICT_NAMES
|
||||
|
|
77
arch/arm/include/asm/arch-omap3/dma.h
Normal file
77
arch/arm/include/asm/arch-omap3/dma.h
Normal file
|
@ -0,0 +1,77 @@
|
|||
#ifndef __SDMA_H
|
||||
#define __SDMA_H
|
||||
|
||||
/* Copyright (C) 2011
|
||||
* Corscience GmbH & Co. KG - Simon Schwarz <schwarz@corscience.de>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/* Functions */
|
||||
void omap3_dma_init(void);
|
||||
int omap3_dma_conf_transfer(uint32_t chan, uint32_t *src, uint32_t *dst,
|
||||
uint32_t sze);
|
||||
int omap3_dma_start_transfer(uint32_t chan);
|
||||
int omap3_dma_wait_for_transfer(uint32_t chan);
|
||||
int omap3_dma_conf_chan(uint32_t chan, struct dma4_chan *config);
|
||||
int omap3_dma_get_conf_chan(uint32_t chan, struct dma4_chan *config);
|
||||
|
||||
/* Register settings */
|
||||
#define CSDP_DATA_TYPE_8BIT 0x0
|
||||
#define CSDP_DATA_TYPE_16BIT 0x1
|
||||
#define CSDP_DATA_TYPE_32BIT 0x2
|
||||
#define CSDP_SRC_BURST_SINGLE (0x0 << 7)
|
||||
#define CSDP_SRC_BURST_EN_16BYTES (0x1 << 7)
|
||||
#define CSDP_SRC_BURST_EN_32BYTES (0x2 << 7)
|
||||
#define CSDP_SRC_BURST_EN_64BYTES (0x3 << 7)
|
||||
#define CSDP_DST_BURST_SINGLE (0x0 << 14)
|
||||
#define CSDP_DST_BURST_EN_16BYTES (0x1 << 14)
|
||||
#define CSDP_DST_BURST_EN_32BYTES (0x2 << 14)
|
||||
#define CSDP_DST_BURST_EN_64BYTES (0x3 << 14)
|
||||
#define CSDP_DST_ENDIAN_LOCK_ADAPT (0x0 << 18)
|
||||
#define CSDP_DST_ENDIAN_LOCK_LOCK (0x1 << 18)
|
||||
#define CSDP_DST_ENDIAN_LITTLE (0x0 << 19)
|
||||
#define CSDP_DST_ENDIAN_BIG (0x1 << 19)
|
||||
#define CSDP_SRC_ENDIAN_LOCK_ADAPT (0x0 << 20)
|
||||
#define CSDP_SRC_ENDIAN_LOCK_LOCK (0x1 << 20)
|
||||
#define CSDP_SRC_ENDIAN_LITTLE (0x0 << 21)
|
||||
#define CSDP_SRC_ENDIAN_BIG (0x1 << 21)
|
||||
|
||||
#define CCR_READ_PRIORITY_LOW (0x0 << 6)
|
||||
#define CCR_READ_PRIORITY_HIGH (0x1 << 6)
|
||||
#define CCR_ENABLE_DISABLED (0x0 << 7)
|
||||
#define CCR_ENABLE_ENABLE (0x1 << 7)
|
||||
#define CCR_SRC_AMODE_CONSTANT (0x0 << 12)
|
||||
#define CCR_SRC_AMODE_POST_INC (0x1 << 12)
|
||||
#define CCR_SRC_AMODE_SINGLE_IDX (0x2 << 12)
|
||||
#define CCR_SRC_AMODE_DOUBLE_IDX (0x3 << 12)
|
||||
#define CCR_DST_AMODE_CONSTANT (0x0 << 14)
|
||||
#define CCR_DST_AMODE_POST_INC (0x1 << 14)
|
||||
#define CCR_DST_AMODE_SINGLE_IDX (0x2 << 14)
|
||||
#define CCR_DST_AMODE_SOUBLE_IDX (0x3 << 14)
|
||||
|
||||
#define CCR_RD_ACTIVE_MASK (1 << 9)
|
||||
#define CCR_WR_ACTIVE_MASK (1 << 10)
|
||||
|
||||
#define CSR_TRANS_ERR (1 << 8)
|
||||
#define CSR_SUPERVISOR_ERR (1 << 10)
|
||||
#define CSR_MISALIGNED_ADRS_ERR (1 << 11)
|
||||
|
||||
/* others */
|
||||
#define CHAN_NR_MIN 0
|
||||
#define CHAN_NR_MAX 31
|
||||
|
||||
#endif /* __SDMA_H */
|
|
@ -47,6 +47,9 @@
|
|||
#define OMAP34XX_L4_PER 0x49000000
|
||||
#define OMAP34XX_L4_IO_BASE OMAP34XX_CORE_L4_IO_BASE
|
||||
|
||||
/* DMA4/SDMA */
|
||||
#define OMAP34XX_DMA4_BASE 0x48056000
|
||||
|
||||
/* CONTROL */
|
||||
#define OMAP34XX_CTRL_BASE (OMAP34XX_L4_IO_BASE + 0x2000)
|
||||
|
||||
|
|
|
@ -71,5 +71,4 @@ void power_init_r(void);
|
|||
void dieid_num_r(void);
|
||||
void do_omap3_emu_romcode_call(u32 service_id, u32 parameters);
|
||||
void omap3_gp_romcode_call(u32 service_id, u32 parameter);
|
||||
void omap_rev_string(char *omap_rev_string);
|
||||
#endif
|
||||
|
|
|
@ -57,11 +57,16 @@
|
|||
/* CONTROL_ID_CODE */
|
||||
#define CONTROL_ID_CODE 0x4A002204
|
||||
|
||||
#define OMAP4_CONTROL_ID_CODE_ES1_0 0x0B85202F
|
||||
#define OMAP4_CONTROL_ID_CODE_ES2_0 0x1B85202F
|
||||
#define OMAP4_CONTROL_ID_CODE_ES2_1 0x3B95C02F
|
||||
#define OMAP4_CONTROL_ID_CODE_ES2_2 0x4B95C02F
|
||||
#define OMAP4_CONTROL_ID_CODE_ES2_3 0x6B95C02F
|
||||
/* 4430 */
|
||||
#define OMAP4430_CONTROL_ID_CODE_ES1_0 0x0B85202F
|
||||
#define OMAP4430_CONTROL_ID_CODE_ES2_0 0x1B85202F
|
||||
#define OMAP4430_CONTROL_ID_CODE_ES2_1 0x3B95C02F
|
||||
#define OMAP4430_CONTROL_ID_CODE_ES2_2 0x4B95C02F
|
||||
#define OMAP4430_CONTROL_ID_CODE_ES2_3 0x6B95C02F
|
||||
|
||||
/* 4460 */
|
||||
#define OMAP4460_CONTROL_ID_CODE_ES1_0 0x0B94E02F
|
||||
#define OMAP4460_CONTROL_ID_CODE_ES1_1 0x2B94E02F
|
||||
|
||||
/* UART */
|
||||
#define UART1_BASE (OMAP44XX_L4_PER_BASE + 0x6a000)
|
||||
|
@ -191,6 +196,7 @@ struct control_lpddr2io_regs {
|
|||
#define OMAP4430_ES2_2 0x44300220
|
||||
#define OMAP4430_ES2_3 0x44300230
|
||||
#define OMAP4460_ES1_0 0x44600100
|
||||
#define OMAP4460_ES1_1 0x44600110
|
||||
|
||||
/* ROM code defines */
|
||||
/* Boot device */
|
||||
|
|
|
@ -43,7 +43,6 @@ void sr32(void *, u32, u32, u32);
|
|||
u32 wait_on_value(u32, u32, void *, u32);
|
||||
void sdelay(unsigned long);
|
||||
void set_pl310_ctrl_reg(u32 val);
|
||||
void omap_rev_string(char *omap4_rev_string);
|
||||
void setup_clocks_for_console(void);
|
||||
void prcm_init(void);
|
||||
void bypass_dpll(u32 *const base);
|
||||
|
|
|
@ -30,13 +30,7 @@
|
|||
#ifndef _ASM_ARCH_ORION5X_H
|
||||
#define _ASM_ARCH_ORION5X_H
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#include <asm/types.h>
|
||||
#include <asm/io.h>
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#if defined(CONFIG_FEROCEON)
|
||||
#include <asm/arch/cpu.h>
|
||||
|
||||
/* SOC specific definations */
|
||||
#define ORION5X_REGISTER(x) (ORION5X_REGS_PHY_BASE + x)
|
||||
|
|
|
@ -25,6 +25,8 @@
|
|||
#ifndef _PANTHEON_CONFIG_H
|
||||
#define _PANTHEON_CONFIG_H
|
||||
|
||||
#include <asm/arch/pantheon.h>
|
||||
|
||||
#define CONFIG_ARM926EJS 1 /* Basic Architecture */
|
||||
|
||||
#define CONFIG_SYS_TCLK (14745600) /* NS16550 clk config */
|
||||
|
@ -45,4 +47,22 @@
|
|||
#define CONFIG_SYS_I2C_SLAVE 0xfe
|
||||
#endif
|
||||
|
||||
/*
|
||||
* MMC definition
|
||||
*/
|
||||
#ifdef CONFIG_CMD_MMC
|
||||
#define CONFIG_CMD_FAT 1
|
||||
#define CONFIG_MMC 1
|
||||
#define CONFIG_GENERIC_MMC 1
|
||||
#define CONFIG_SDHCI 1
|
||||
#define CONFIG_MMC_SDHCI_IO_ACCESSORS 1
|
||||
#define CONFIG_SYS_MMC_MAX_BLK_COUNT 0x1000
|
||||
#define CONFIG_MMC_SDMA 1
|
||||
#define CONFIG_MV_SDHCI 1
|
||||
#define CONFIG_DOS_PARTITION 1
|
||||
#define CONFIG_EFI_PARTITION 1
|
||||
#define CONFIG_SYS_MMC_NUM 2
|
||||
#define CONFIG_SYS_MMC_BASE {0xD4280000, 0xd4281000}
|
||||
#endif
|
||||
|
||||
#endif /* _PANTHEON_CONFIG_H */
|
||||
|
|
|
@ -42,6 +42,17 @@ struct panthmpmu_registers {
|
|||
u32 acgr; /*0x1024*/
|
||||
};
|
||||
|
||||
/*
|
||||
* Application Power Management (APMU) Registers
|
||||
* Refer Register Datasheet 9.2
|
||||
*/
|
||||
struct panthapmu_registers {
|
||||
u8 pad0[0x0054];
|
||||
u32 sd1; /*0x0054*/
|
||||
u8 pad1[0x00e0 - 0x054 - 4];
|
||||
u32 sd3; /*0x00e0*/
|
||||
};
|
||||
|
||||
/*
|
||||
* APB Clock Reset/Control Registers
|
||||
* Refer Register Datasheet 6.14
|
||||
|
@ -77,5 +88,6 @@ struct panthcpu_registers {
|
|||
*/
|
||||
u32 panth_sdram_base(int);
|
||||
u32 panth_sdram_size(int);
|
||||
int mv_sdh_init(u32 regbase, u32 max_clk, u32 min_clk, u32 quirks);
|
||||
|
||||
#endif /* _PANTHEON_CPU_H */
|
||||
|
|
|
@ -38,6 +38,18 @@
|
|||
#define MFP54_CI2C_SDA (MFP_REG(0x1b4) | MFP_AF2 | MFP_DRIVE_MEDIUM)
|
||||
|
||||
/* More macros can be defined here... */
|
||||
#define MFP_MMC1_DAT7 (MFP_REG(0x84) | MFP_AF0 | MFP_DRIVE_MEDIUM)
|
||||
#define MFP_MMC1_DAT6 (MFP_REG(0x88) | MFP_AF0 | MFP_DRIVE_MEDIUM)
|
||||
#define MFP_MMC1_DAT5 (MFP_REG(0x8c) | MFP_AF0 | MFP_DRIVE_MEDIUM)
|
||||
#define MFP_MMC1_DAT4 (MFP_REG(0x90) | MFP_AF0 | MFP_DRIVE_MEDIUM)
|
||||
#define MFP_MMC1_DAT3 (MFP_REG(0x94) | MFP_AF0 | MFP_DRIVE_FAST)
|
||||
#define MFP_MMC1_DAT2 (MFP_REG(0x98) | MFP_AF0 | MFP_DRIVE_FAST)
|
||||
#define MFP_MMC1_DAT1 (MFP_REG(0x9c) | MFP_AF0 | MFP_DRIVE_FAST)
|
||||
#define MFP_MMC1_DAT0 (MFP_REG(0xa0) | MFP_AF0 | MFP_DRIVE_FAST)
|
||||
#define MFP_MMC1_CMD (MFP_REG(0xa4) | MFP_AF0 | MFP_DRIVE_FAST)
|
||||
#define MFP_MMC1_CLK (MFP_REG(0xa8) | MFP_AF0 | MFP_DRIVE_FAST)
|
||||
#define MFP_MMC1_CD (MFP_REG(0xac) | MFP_AF0 | MFP_DRIVE_MEDIUM)
|
||||
#define MFP_MMC1_WP (MFP_REG(0xb0) | MFP_AF0 | MFP_DRIVE_MEDIUM)
|
||||
|
||||
#define MFP_PIN_MAX 117
|
||||
#endif
|
||||
|
|
|
@ -25,13 +25,6 @@
|
|||
#ifndef _PANTHEON_H
|
||||
#define _PANTHEON_H
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#include <asm/types.h>
|
||||
#include <asm/io.h>
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#include <asm/arch/cpu.h>
|
||||
|
||||
/* Common APB clock register bit definitions */
|
||||
#define APBC_APBCLK (1<<0) /* APB Bus Clock Enable */
|
||||
#define APBC_FNCLK (1<<1) /* Functional Clock Enable */
|
||||
|
@ -39,6 +32,12 @@
|
|||
/* Functional Clock Selection Mask */
|
||||
#define APBC_FNCLKSEL(x) (((x) & 0xf) << 4)
|
||||
|
||||
/* Common APMU register bit definitions */
|
||||
#define APMU_PERI_CLK (1<<4) /* Peripheral Clock Enable */
|
||||
#define APMU_AXI_CLK (1<<3) /* AXI Clock Enable*/
|
||||
#define APMU_PERI_RST (1<<1) /* Peripheral Reset */
|
||||
#define APMU_AXI_RST (1<<0) /* AXI Reset */
|
||||
|
||||
/* Register Base Addresses */
|
||||
#define PANTHEON_DRAM_BASE 0xB0000000
|
||||
#define PANTHEON_TIMER_BASE 0xD4014000
|
||||
|
@ -49,6 +48,7 @@
|
|||
#define PANTHEON_GPIO_BASE 0xD4019000
|
||||
#define PANTHEON_MFPR_BASE 0xD401E000
|
||||
#define PANTHEON_MPMU_BASE 0xD4050000
|
||||
#define PANTHEON_APMU_BASE 0xD4282800
|
||||
#define PANTHEON_CPU_BASE 0xD4282C00
|
||||
|
||||
#endif /* _PANTHEON_H */
|
||||
|
|
|
@ -43,9 +43,12 @@ struct clk_pll_simple {
|
|||
* structure for which we use clk_pll_simple. The reason for this non-
|
||||
* othogonal setup is not stated.
|
||||
*/
|
||||
#define TEGRA_CLK_PLLS 6
|
||||
#define TEGRA_CLK_SIMPLE_PLLS 3 /* Number of simple PLLs */
|
||||
#define TEGRA_CLK_REGS 3 /* Number of clock enable registers */
|
||||
enum {
|
||||
TEGRA_CLK_PLLS = 6, /* Number of normal PLLs */
|
||||
TEGRA_CLK_SIMPLE_PLLS = 3, /* Number of simple PLLs */
|
||||
TEGRA_CLK_REGS = 3, /* Number of clock enable registers */
|
||||
TEGRA_CLK_SOURCES = 64, /* Number of peripheral clock sources */
|
||||
};
|
||||
|
||||
/* Clock/Reset Controller (CLK_RST_CONTROLLER_) regs */
|
||||
struct clk_rst_ctlr {
|
||||
|
@ -79,65 +82,10 @@ struct clk_rst_ctlr {
|
|||
uint crc_reserved10; /* _reserved_10, 0xF8 */
|
||||
uint crc_reserved11; /* _reserved_11, 0xFC */
|
||||
|
||||
uint crc_clk_src_i2s1; /*_I2S1_0, 0x100 */
|
||||
uint crc_clk_src_i2s2; /*_I2S2_0, 0x104 */
|
||||
uint crc_clk_src_spdif_out; /*_SPDIF_OUT_0, 0x108 */
|
||||
uint crc_clk_src_spdif_in; /*_SPDIF_IN_0, 0x10C */
|
||||
uint crc_clk_src_pwm; /*_PWM_0, 0x110 */
|
||||
uint crc_clk_src_spi1; /*_SPI1_0, 0x114 */
|
||||
uint crc_clk_src_sbc2; /*_SBC2_0, 0x118 */
|
||||
uint crc_clk_src_sbc3; /*_SBC3_0, 0x11C */
|
||||
uint crc_clk_src_xio; /*_XIO_0, 0x120 */
|
||||
uint crc_clk_src_i2c1; /*_I2C1_0, 0x124 */
|
||||
uint crc_clk_src_dvc_i2c; /*_DVC_I2C_0, 0x128 */
|
||||
uint crc_clk_src_twc; /*_TWC_0, 0x12C */
|
||||
uint crc_reserved12; /* 0x130 */
|
||||
uint crc_clk_src_sbc1; /*_SBC1_0, 0x134 */
|
||||
uint crc_clk_src_disp1; /*_DISP1_0, 0x138 */
|
||||
uint crc_clk_src_disp2; /*_DISP2_0, 0x13C */
|
||||
uint crc_clk_src_cve; /*_CVE_0, 0x140 */
|
||||
uint crc_clk_src_ide; /*_IDE_0, 0x144 */
|
||||
uint crc_clk_src_vi; /*_VI_0, 0x148 */
|
||||
uint crc_reserved13; /* 0x14C */
|
||||
uint crc_clk_src_sdmmc1; /*_SDMMC1_0, 0x150 */
|
||||
uint crc_clk_src_sdmmc2; /*_SDMMC2_0, 0x154 */
|
||||
uint crc_clk_src_g3d; /*_G3D_0, 0x158 */
|
||||
uint crc_clk_src_g2d; /*_G2D_0, 0x15C */
|
||||
uint crc_clk_src_ndflash; /*_NDFLASH_0, 0x160 */
|
||||
uint crc_clk_src_sdmmc4; /*_SDMMC4_0, 0x164 */
|
||||
uint crc_clk_src_vfir; /*_VFIR_0, 0x168 */
|
||||
uint crc_clk_src_epp; /*_EPP_0, 0x16C */
|
||||
uint crc_clk_src_mp3; /*_MPE_0, 0x170 */
|
||||
uint crc_clk_src_mipi; /*_MIPI_0, 0x174 */
|
||||
uint crc_clk_src_uarta; /*_UARTA_0, 0x178 */
|
||||
uint crc_clk_src_uartb; /*_UARTB_0, 0x17C */
|
||||
uint crc_clk_src_host1x; /*_HOST1X_0, 0x180 */
|
||||
uint crc_reserved14; /* 0x184 */
|
||||
uint crc_clk_src_tvo; /*_TVO_0, 0x188 */
|
||||
uint crc_clk_src_hdmi; /*_HDMI_0, 0x18C */
|
||||
uint crc_reserved15; /* 0x190 */
|
||||
uint crc_clk_src_tvdac; /*_TVDAC_0, 0x194 */
|
||||
uint crc_clk_src_i2c2; /*_I2C2_0, 0x198 */
|
||||
uint crc_clk_src_emc; /*_EMC_0, 0x19C */
|
||||
uint crc_clk_src_uartc; /*_UARTC_0, 0x1A0 */
|
||||
uint crc_reserved16; /* 0x1A4 */
|
||||
uint crc_clk_src_vi_sensor; /*_VI_SENSOR_0, 0x1A8 */
|
||||
uint crc_reserved17; /* 0x1AC */
|
||||
uint crc_reserved18; /* 0x1B0 */
|
||||
uint crc_clk_src_sbc4; /*_SBC4_0, 0x1B4 */
|
||||
uint crc_clk_src_i2c3; /*_I2C3_0, 0x1B8 */
|
||||
uint crc_clk_src_sdmmc3; /*_SDMMC3_0, 0x1BC */
|
||||
uint crc_clk_src_uartd; /*_UARTD_0, 0x1C0 */
|
||||
uint crc_clk_src_uarte; /*_UARTE_0, 0x1C4 */
|
||||
uint crc_clk_src_vde; /*_VDE_0, 0x1C8 */
|
||||
uint crc_clk_src_owr; /*_OWR_0, 0x1CC */
|
||||
uint crc_clk_src_nor; /*_NOR_0, 0x1D0 */
|
||||
uint crc_clk_src_csite; /*_CSITE_0, 0x1D4 */
|
||||
uint crc_reserved19[9]; /* 0x1D8-1F8 */
|
||||
uint crc_clk_src_osc; /*_OSC_0, 0x1FC */
|
||||
uint crc_clk_src[TEGRA_CLK_SOURCES]; /*_I2S1_0... 0x100-1fc */
|
||||
uint crc_reserved20[80]; /* 0x200-33C */
|
||||
uint crc_cpu_cmplx_set; /* _CPU_CMPLX_SET_0, 0x340 */
|
||||
uint crc_cpu_cmplx_clr; /* _CPU_CMPLX_CLR_0, 0x344 */
|
||||
uint crc_cpu_cmplx_set; /* _CPU_CMPLX_SET_0, 0x340 */
|
||||
uint crc_cpu_cmplx_clr; /* _CPU_CMPLX_CLR_0, 0x344 */
|
||||
};
|
||||
|
||||
/* CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0 */
|
||||
|
@ -156,10 +104,13 @@ struct clk_rst_ctlr {
|
|||
#define PLL_BASE_OVRRIDE_MASK (1U << 28)
|
||||
|
||||
#define PLL_DIVP_SHIFT 20
|
||||
#define PLL_DIVP_MASK (7U << PLL_DIVP_SHIFT)
|
||||
|
||||
#define PLL_DIVN_SHIFT 8
|
||||
#define PLL_DIVN_MASK (0x3ffU << PLL_DIVN_SHIFT)
|
||||
|
||||
#define PLL_DIVM_SHIFT 0
|
||||
#define PLL_DIVM_MASK (0x1f << PLL_DIVM_SHIFT)
|
||||
|
||||
/* CLK_RST_CONTROLLER_PLLx_MISC_0 */
|
||||
#define PLL_CPCON_SHIFT 8
|
||||
|
@ -168,9 +119,20 @@ struct clk_rst_ctlr {
|
|||
#define PLL_LFCON_SHIFT 4
|
||||
|
||||
#define PLLU_VCO_FREQ_SHIFT 20
|
||||
#define PLLU_VCO_FREQ_MASK (1U << PLLU_VCO_FREQ_SHIFT)
|
||||
|
||||
/* CLK_RST_CONTROLLER_OSC_CTRL_0 */
|
||||
#define OSC_FREQ_SHIFT 30
|
||||
#define OSC_FREQ_MASK (3U << OSC_FREQ_SHIFT)
|
||||
|
||||
/* CLK_RST_CONTROLLER_CLK_SOURCE_x_OUT_0 */
|
||||
#define OUT_CLK_DIVISOR_SHIFT 0
|
||||
#define OUT_CLK_DIVISOR_MASK (255 << OUT_CLK_DIVISOR_SHIFT)
|
||||
|
||||
#define OUT_CLK_SOURCE_SHIFT 30
|
||||
#define OUT_CLK_SOURCE_MASK (3U << OUT_CLK_SOURCE_SHIFT)
|
||||
|
||||
#define OUT_CLK_SOURCE4_SHIFT 28
|
||||
#define OUT_CLK_SOURCE4_MASK (15U << OUT_CLK_SOURCE4_SHIFT)
|
||||
|
||||
#endif /* CLK_RST_H */
|
||||
|
|
|
@ -22,7 +22,7 @@
|
|||
/* Tegra2 clock control functions */
|
||||
|
||||
#ifndef _CLOCK_H
|
||||
|
||||
#define _CLOCK_H
|
||||
|
||||
/* Set of oscillator frequencies supported in the internal API. */
|
||||
enum clock_osc_freq {
|
||||
|
@ -36,22 +36,27 @@ enum clock_osc_freq {
|
|||
};
|
||||
|
||||
/* The PLLs supported by the hardware */
|
||||
enum clock_pll_id {
|
||||
CLOCK_PLL_ID_FIRST,
|
||||
CLOCK_PLL_ID_CGENERAL = CLOCK_PLL_ID_FIRST,
|
||||
CLOCK_PLL_ID_MEMORY,
|
||||
CLOCK_PLL_ID_PERIPH,
|
||||
CLOCK_PLL_ID_AUDIO,
|
||||
CLOCK_PLL_ID_USB,
|
||||
CLOCK_PLL_ID_DISPLAY,
|
||||
enum clock_id {
|
||||
CLOCK_ID_FIRST,
|
||||
CLOCK_ID_CGENERAL = CLOCK_ID_FIRST,
|
||||
CLOCK_ID_MEMORY,
|
||||
CLOCK_ID_PERIPH,
|
||||
CLOCK_ID_AUDIO,
|
||||
CLOCK_ID_USB,
|
||||
CLOCK_ID_DISPLAY,
|
||||
|
||||
/* now the simple ones */
|
||||
CLOCK_PLL_ID_FIRST_SIMPLE,
|
||||
CLOCK_PLL_ID_XCPU = CLOCK_PLL_ID_FIRST_SIMPLE,
|
||||
CLOCK_PLL_ID_EPCI,
|
||||
CLOCK_PLL_ID_SFROM32KHZ,
|
||||
CLOCK_ID_FIRST_SIMPLE,
|
||||
CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE,
|
||||
CLOCK_ID_EPCI,
|
||||
CLOCK_ID_SFROM32KHZ,
|
||||
|
||||
CLOCK_PLL_ID_COUNT,
|
||||
/* These are the base clocks (inputs to the Tegra SOC) */
|
||||
CLOCK_ID_32KHZ,
|
||||
CLOCK_ID_OSC,
|
||||
|
||||
CLOCK_ID_COUNT, /* number of clocks */
|
||||
CLOCK_ID_NONE = -1,
|
||||
};
|
||||
|
||||
/* The clocks supported by the hardware */
|
||||
|
@ -80,7 +85,7 @@ enum periph_id {
|
|||
|
||||
/* 16 */
|
||||
PERIPH_ID_TWC,
|
||||
PERIPH_ID_PWC,
|
||||
PERIPH_ID_PWM,
|
||||
PERIPH_ID_I2S2,
|
||||
PERIPH_ID_EPP,
|
||||
PERIPH_ID_VI,
|
||||
|
@ -181,12 +186,7 @@ enum periph_id {
|
|||
#define PERIPH_MASK(id) (1 << ((id) & 0x1f))
|
||||
|
||||
/* return 1 if a PLL ID is in range */
|
||||
#define clock_pll_id_isvalid(id) ((id) >= CLOCK_PLL_ID_FIRST && \
|
||||
(id) < CLOCK_PLL_ID_COUNT)
|
||||
|
||||
/* return 1 if a peripheral ID is in range */
|
||||
#define clock_periph_id_isvalid(id) ((id) >= PERIPH_ID_FIRST && \
|
||||
(id) < PERIPH_ID_COUNT)
|
||||
#define clock_id_isvalid(id) ((id) >= CLOCK_ID_FIRST && (id) < CLOCK_ID_COUNT)
|
||||
|
||||
/* PLL stabilization delay in usec */
|
||||
#define CLOCK_PLL_STABLE_DELAY_US 300
|
||||
|
@ -194,7 +194,7 @@ enum periph_id {
|
|||
/* return the current oscillator clock frequency */
|
||||
enum clock_osc_freq clock_get_osc_freq(void);
|
||||
|
||||
/*
|
||||
/**
|
||||
* Start PLL using the provided configuration parameters.
|
||||
*
|
||||
* @param id clock id
|
||||
|
@ -206,7 +206,7 @@ enum clock_osc_freq clock_get_osc_freq(void);
|
|||
*
|
||||
* @returns monotonic time in us that the PLL will be stable
|
||||
*/
|
||||
unsigned long clock_start_pll(enum clock_pll_id id, u32 divm, u32 divn,
|
||||
unsigned long clock_start_pll(enum clock_id id, u32 divm, u32 divn,
|
||||
u32 divp, u32 cpcon, u32 lfcon);
|
||||
|
||||
/*
|
||||
|
@ -216,6 +216,13 @@ unsigned long clock_start_pll(enum clock_pll_id id, u32 divm, u32 divn,
|
|||
*/
|
||||
void clock_enable(enum periph_id clkid);
|
||||
|
||||
/*
|
||||
* Disable a clock
|
||||
*
|
||||
* @param id clock id
|
||||
*/
|
||||
void clock_disable(enum periph_id clkid);
|
||||
|
||||
/*
|
||||
* Set whether a clock is enabled or disabled.
|
||||
*
|
||||
|
@ -224,7 +231,7 @@ void clock_enable(enum periph_id clkid);
|
|||
*/
|
||||
void clock_set_enable(enum periph_id clkid, int enable);
|
||||
|
||||
/*
|
||||
/**
|
||||
* Reset a peripheral. This puts it in reset, waits for a delay, then takes
|
||||
* it out of reset and waits for th delay again.
|
||||
*
|
||||
|
@ -233,7 +240,7 @@ void clock_set_enable(enum periph_id clkid, int enable);
|
|||
*/
|
||||
void reset_periph(enum periph_id periph_id, int us_delay);
|
||||
|
||||
/*
|
||||
/**
|
||||
* Put a peripheral into or out of reset.
|
||||
*
|
||||
* @param periph_id peripheral to reset
|
||||
|
@ -251,7 +258,7 @@ enum crc_reset_id {
|
|||
crc_rst_debug = 1 << 4,
|
||||
};
|
||||
|
||||
/*
|
||||
/**
|
||||
* Put parts of the CPU complex into or out of reset.\
|
||||
*
|
||||
* @param cpu cpu number (0 or 1 on Tegra2)
|
||||
|
@ -260,4 +267,94 @@ enum crc_reset_id {
|
|||
*/
|
||||
void reset_cmplx_set_enable(int cpu, int which, int reset);
|
||||
|
||||
/**
|
||||
* Set the source for a peripheral clock. This plus the divisor sets the
|
||||
* clock rate. You need to look up the datasheet to see the meaning of the
|
||||
* source parameter as it changes for each peripheral.
|
||||
*
|
||||
* Warning: This function is only for use pre-relocation. Please use
|
||||
* clock_start_periph_pll() instead.
|
||||
*
|
||||
* @param periph_id peripheral to adjust
|
||||
* @param source source clock (0, 1, 2 or 3)
|
||||
*/
|
||||
void clock_ll_set_source(enum periph_id periph_id, unsigned source);
|
||||
|
||||
/**
|
||||
* Set the source and divisor for a peripheral clock. This sets the
|
||||
* clock rate. You need to look up the datasheet to see the meaning of the
|
||||
* source parameter as it changes for each peripheral.
|
||||
*
|
||||
* Warning: This function is only for use pre-relocation. Please use
|
||||
* clock_start_periph_pll() instead.
|
||||
*
|
||||
* @param periph_id peripheral to adjust
|
||||
* @param source source clock (0, 1, 2 or 3)
|
||||
* @param divisor divisor value to use
|
||||
*/
|
||||
void clock_ll_set_source_divisor(enum periph_id periph_id, unsigned source,
|
||||
unsigned divisor);
|
||||
|
||||
/**
|
||||
* Start a peripheral PLL clock at the given rate. This also resets the
|
||||
* peripheral.
|
||||
*
|
||||
* @param periph_id peripheral to start
|
||||
* @param parent PLL id of required parent clock
|
||||
* @param rate Required clock rate in Hz
|
||||
* @return rate selected in Hz, or -1U if something went wrong
|
||||
*/
|
||||
unsigned clock_start_periph_pll(enum periph_id periph_id,
|
||||
enum clock_id parent, unsigned rate);
|
||||
|
||||
/**
|
||||
* Returns the rate of a peripheral clock in Hz. Since the caller almost
|
||||
* certainly knows the parent clock (having just set it) we require that
|
||||
* this be passed in so we don't need to work it out.
|
||||
*
|
||||
* @param periph_id peripheral to start
|
||||
* @param parent PLL id of parent clock (used to calculate rate, you
|
||||
* must know this!)
|
||||
* @return clock rate of peripheral in Hz
|
||||
*/
|
||||
unsigned long clock_get_periph_rate(enum periph_id periph_id,
|
||||
enum clock_id parent);
|
||||
|
||||
/**
|
||||
* Adjust peripheral PLL clock to the given rate. This does not reset the
|
||||
* peripheral. If a second stage divisor is not available, pass NULL for
|
||||
* extra_div. If it is available, then this parameter will return the
|
||||
* divisor selected (which will be a power of 2 from 1 to 256).
|
||||
*
|
||||
* @param periph_id peripheral to start
|
||||
* @param parent PLL id of required parent clock
|
||||
* @param rate Required clock rate in Hz
|
||||
* @param extra_div value for the second-stage divisor (NULL if one is
|
||||
not available)
|
||||
* @return rate selected in Hz, or -1U if something went wrong
|
||||
*/
|
||||
unsigned clock_adjust_periph_pll_div(enum periph_id periph_id,
|
||||
enum clock_id parent, unsigned rate, int *extra_div);
|
||||
|
||||
/**
|
||||
* Returns the clock rate of a specified clock, in Hz.
|
||||
*
|
||||
* @param parent PLL id of clock to check
|
||||
* @return rate of clock in Hz
|
||||
*/
|
||||
unsigned clock_get_rate(enum clock_id clkid);
|
||||
|
||||
/*
|
||||
* Checks that clocks are valid and prints a warning if not
|
||||
*
|
||||
* @return 0 if ok, -1 on error
|
||||
*/
|
||||
int clock_verify(void);
|
||||
|
||||
/* Initialize the clocks */
|
||||
void clock_init(void);
|
||||
|
||||
/* Initialize the PLLs */
|
||||
void clock_early_init(void);
|
||||
|
||||
#endif
|
||||
|
|
|
@ -24,173 +24,331 @@
|
|||
#ifndef _PINMUX_H_
|
||||
#define _PINMUX_H_
|
||||
|
||||
/* Pins which we can set to tristate or normal */
|
||||
enum pmux_pin {
|
||||
/*
|
||||
* Pin groups which we adjust. There are three basic attributes of each pin
|
||||
* group which use this enum:
|
||||
*
|
||||
* - function
|
||||
* - pullup / pulldown
|
||||
* - tristate or normal
|
||||
*/
|
||||
enum pmux_pingrp {
|
||||
/* APB_MISC_PP_TRISTATE_REG_A_0 */
|
||||
PIN_ATA,
|
||||
PIN_ATB,
|
||||
PIN_ATC,
|
||||
PIN_ATD,
|
||||
PIN_CDEV1,
|
||||
PIN_CDEV2,
|
||||
PIN_CSUS,
|
||||
PIN_DAP1,
|
||||
PINGRP_ATA,
|
||||
PINGRP_ATB,
|
||||
PINGRP_ATC,
|
||||
PINGRP_ATD,
|
||||
PINGRP_CDEV1,
|
||||
PINGRP_CDEV2,
|
||||
PINGRP_CSUS,
|
||||
PINGRP_DAP1,
|
||||
|
||||
PIN_DAP2,
|
||||
PIN_DAP3,
|
||||
PIN_DAP4,
|
||||
PIN_DTA,
|
||||
PIN_DTB,
|
||||
PIN_DTC,
|
||||
PIN_DTD,
|
||||
PIN_DTE,
|
||||
PINGRP_DAP2,
|
||||
PINGRP_DAP3,
|
||||
PINGRP_DAP4,
|
||||
PINGRP_DTA,
|
||||
PINGRP_DTB,
|
||||
PINGRP_DTC,
|
||||
PINGRP_DTD,
|
||||
PINGRP_DTE,
|
||||
|
||||
PIN_GPU,
|
||||
PIN_GPV,
|
||||
PIN_I2CP,
|
||||
PIN_IRTX,
|
||||
PIN_IRRX,
|
||||
PIN_KBCB,
|
||||
PIN_KBCA,
|
||||
PIN_PMC,
|
||||
PINGRP_GPU,
|
||||
PINGRP_GPV,
|
||||
PINGRP_I2CP,
|
||||
PINGRP_IRTX,
|
||||
PINGRP_IRRX,
|
||||
PINGRP_KBCB,
|
||||
PINGRP_KBCA,
|
||||
PINGRP_PMC,
|
||||
|
||||
PIN_PTA,
|
||||
PIN_RM,
|
||||
PIN_KBCE,
|
||||
PIN_KBCF,
|
||||
PIN_GMA,
|
||||
PIN_GMC,
|
||||
PIN_SDMMC1,
|
||||
PIN_OWC,
|
||||
PINGRP_PTA,
|
||||
PINGRP_RM,
|
||||
PINGRP_KBCE,
|
||||
PINGRP_KBCF,
|
||||
PINGRP_GMA,
|
||||
PINGRP_GMC,
|
||||
PINGRP_SDMMC1,
|
||||
PINGRP_OWC,
|
||||
|
||||
/* 32: APB_MISC_PP_TRISTATE_REG_B_0 */
|
||||
PIN_GME,
|
||||
PIN_SDC,
|
||||
PIN_SDD,
|
||||
PIN_RESERVED0,
|
||||
PIN_SLXA,
|
||||
PIN_SLXC,
|
||||
PIN_SLXD,
|
||||
PIN_SLXK,
|
||||
PINGRP_GME,
|
||||
PINGRP_SDC,
|
||||
PINGRP_SDD,
|
||||
PINGRP_RESERVED0,
|
||||
PINGRP_SLXA,
|
||||
PINGRP_SLXC,
|
||||
PINGRP_SLXD,
|
||||
PINGRP_SLXK,
|
||||
|
||||
PIN_SPDI,
|
||||
PIN_SPDO,
|
||||
PIN_SPIA,
|
||||
PIN_SPIB,
|
||||
PIN_SPIC,
|
||||
PIN_SPID,
|
||||
PIN_SPIE,
|
||||
PIN_SPIF,
|
||||
PINGRP_SPDI,
|
||||
PINGRP_SPDO,
|
||||
PINGRP_SPIA,
|
||||
PINGRP_SPIB,
|
||||
PINGRP_SPIC,
|
||||
PINGRP_SPID,
|
||||
PINGRP_SPIE,
|
||||
PINGRP_SPIF,
|
||||
|
||||
PIN_SPIG,
|
||||
PIN_SPIH,
|
||||
PIN_UAA,
|
||||
PIN_UAB,
|
||||
PIN_UAC,
|
||||
PIN_UAD,
|
||||
PIN_UCA,
|
||||
PIN_UCB,
|
||||
PINGRP_SPIG,
|
||||
PINGRP_SPIH,
|
||||
PINGRP_UAA,
|
||||
PINGRP_UAB,
|
||||
PINGRP_UAC,
|
||||
PINGRP_UAD,
|
||||
PINGRP_UCA,
|
||||
PINGRP_UCB,
|
||||
|
||||
PIN_RESERVED1,
|
||||
PIN_ATE,
|
||||
PIN_KBCC,
|
||||
PIN_RESERVED2,
|
||||
PIN_RESERVED3,
|
||||
PIN_GMB,
|
||||
PIN_GMD,
|
||||
PIN_DDC,
|
||||
PINGRP_RESERVED1,
|
||||
PINGRP_ATE,
|
||||
PINGRP_KBCC,
|
||||
PINGRP_RESERVED2,
|
||||
PINGRP_RESERVED3,
|
||||
PINGRP_GMB,
|
||||
PINGRP_GMD,
|
||||
PINGRP_DDC,
|
||||
|
||||
/* 64: APB_MISC_PP_TRISTATE_REG_C_0 */
|
||||
PIN_LD0,
|
||||
PIN_LD1,
|
||||
PIN_LD2,
|
||||
PIN_LD3,
|
||||
PIN_LD4,
|
||||
PIN_LD5,
|
||||
PIN_LD6,
|
||||
PIN_LD7,
|
||||
PINGRP_LD0,
|
||||
PINGRP_LD1,
|
||||
PINGRP_LD2,
|
||||
PINGRP_LD3,
|
||||
PINGRP_LD4,
|
||||
PINGRP_LD5,
|
||||
PINGRP_LD6,
|
||||
PINGRP_LD7,
|
||||
|
||||
PIN_LD8,
|
||||
PIN_LD9,
|
||||
PIN_LD10,
|
||||
PIN_LD11,
|
||||
PIN_LD12,
|
||||
PIN_LD13,
|
||||
PIN_LD14,
|
||||
PIN_LD15,
|
||||
PINGRP_LD8,
|
||||
PINGRP_LD9,
|
||||
PINGRP_LD10,
|
||||
PINGRP_LD11,
|
||||
PINGRP_LD12,
|
||||
PINGRP_LD13,
|
||||
PINGRP_LD14,
|
||||
PINGRP_LD15,
|
||||
|
||||
PIN_LD16,
|
||||
PIN_LD17,
|
||||
PIN_LHP0,
|
||||
PIN_LHP1,
|
||||
PIN_LHP2,
|
||||
PIN_LVP0,
|
||||
PIN_LVP1,
|
||||
PIN_HDINT,
|
||||
PINGRP_LD16,
|
||||
PINGRP_LD17,
|
||||
PINGRP_LHP0,
|
||||
PINGRP_LHP1,
|
||||
PINGRP_LHP2,
|
||||
PINGRP_LVP0,
|
||||
PINGRP_LVP1,
|
||||
PINGRP_HDINT,
|
||||
|
||||
PIN_LM0,
|
||||
PIN_LM1,
|
||||
PIN_LVS,
|
||||
PIN_LSC0,
|
||||
PIN_LSC1,
|
||||
PIN_LSCK,
|
||||
PIN_LDC,
|
||||
PIN_LCSN,
|
||||
PINGRP_LM0,
|
||||
PINGRP_LM1,
|
||||
PINGRP_LVS,
|
||||
PINGRP_LSC0,
|
||||
PINGRP_LSC1,
|
||||
PINGRP_LSCK,
|
||||
PINGRP_LDC,
|
||||
PINGRP_LCSN,
|
||||
|
||||
/* 96: APB_MISC_PP_TRISTATE_REG_D_0 */
|
||||
PIN_LSPI,
|
||||
PIN_LSDA,
|
||||
PIN_LSDI,
|
||||
PIN_LPW0,
|
||||
PIN_LPW1,
|
||||
PIN_LPW2,
|
||||
PIN_LDI,
|
||||
PIN_LHS,
|
||||
PINGRP_LSPI,
|
||||
PINGRP_LSDA,
|
||||
PINGRP_LSDI,
|
||||
PINGRP_LPW0,
|
||||
PINGRP_LPW1,
|
||||
PINGRP_LPW2,
|
||||
PINGRP_LDI,
|
||||
PINGRP_LHS,
|
||||
|
||||
PIN_LPP,
|
||||
PIN_RESERVED4,
|
||||
PIN_KBCD,
|
||||
PIN_GPU7,
|
||||
PIN_DTF,
|
||||
PIN_UDA,
|
||||
PIN_CRTP,
|
||||
PIN_SDB,
|
||||
PINGRP_LPP,
|
||||
PINGRP_RESERVED4,
|
||||
PINGRP_KBCD,
|
||||
PINGRP_GPU7,
|
||||
PINGRP_DTF,
|
||||
PINGRP_UDA,
|
||||
PINGRP_CRTP,
|
||||
PINGRP_SDB,
|
||||
|
||||
/* these pin groups only have pullup and pull down control */
|
||||
PINGRP_FIRST_NO_MUX,
|
||||
PINGRP_CK32 = PINGRP_FIRST_NO_MUX,
|
||||
PINGRP_DDRC,
|
||||
PINGRP_PMCA,
|
||||
PINGRP_PMCB,
|
||||
PINGRP_PMCC,
|
||||
PINGRP_PMCD,
|
||||
PINGRP_PMCE,
|
||||
PINGRP_XM2C,
|
||||
PINGRP_XM2D,
|
||||
|
||||
PINGRP_COUNT,
|
||||
};
|
||||
|
||||
/*
|
||||
* Functions which can be assigned to each of the pin groups. The values here
|
||||
* bear no relation to the values programmed into pinmux registers and are
|
||||
* purely a convenience. The translation is done through a table search.
|
||||
*/
|
||||
enum pmux_func {
|
||||
PMUX_FUNC_AHB_CLK,
|
||||
PMUX_FUNC_APB_CLK,
|
||||
PMUX_FUNC_AUDIO_SYNC,
|
||||
PMUX_FUNC_CRT,
|
||||
PMUX_FUNC_DAP1,
|
||||
PMUX_FUNC_DAP2,
|
||||
PMUX_FUNC_DAP3,
|
||||
PMUX_FUNC_DAP4,
|
||||
PMUX_FUNC_DAP5,
|
||||
PMUX_FUNC_DISPA,
|
||||
PMUX_FUNC_DISPB,
|
||||
PMUX_FUNC_EMC_TEST0_DLL,
|
||||
PMUX_FUNC_EMC_TEST1_DLL,
|
||||
PMUX_FUNC_GMI,
|
||||
PMUX_FUNC_GMI_INT,
|
||||
PMUX_FUNC_HDMI,
|
||||
PMUX_FUNC_I2C,
|
||||
PMUX_FUNC_I2C2,
|
||||
PMUX_FUNC_I2C3,
|
||||
PMUX_FUNC_IDE,
|
||||
PMUX_FUNC_IRDA,
|
||||
PMUX_FUNC_KBC,
|
||||
PMUX_FUNC_MIO,
|
||||
PMUX_FUNC_MIPI_HS,
|
||||
PMUX_FUNC_NAND,
|
||||
PMUX_FUNC_OSC,
|
||||
PMUX_FUNC_OWR,
|
||||
PMUX_FUNC_PCIE,
|
||||
PMUX_FUNC_PLLA_OUT,
|
||||
PMUX_FUNC_PLLC_OUT1,
|
||||
PMUX_FUNC_PLLM_OUT1,
|
||||
PMUX_FUNC_PLLP_OUT2,
|
||||
PMUX_FUNC_PLLP_OUT3,
|
||||
PMUX_FUNC_PLLP_OUT4,
|
||||
PMUX_FUNC_PWM,
|
||||
PMUX_FUNC_PWR_INTR,
|
||||
PMUX_FUNC_PWR_ON,
|
||||
PMUX_FUNC_RTCK,
|
||||
PMUX_FUNC_SDIO1,
|
||||
PMUX_FUNC_SDIO2,
|
||||
PMUX_FUNC_SDIO3,
|
||||
PMUX_FUNC_SDIO4,
|
||||
PMUX_FUNC_SFLASH,
|
||||
PMUX_FUNC_SPDIF,
|
||||
PMUX_FUNC_SPI1,
|
||||
PMUX_FUNC_SPI2,
|
||||
PMUX_FUNC_SPI2_ALT,
|
||||
PMUX_FUNC_SPI3,
|
||||
PMUX_FUNC_SPI4,
|
||||
PMUX_FUNC_TRACE,
|
||||
PMUX_FUNC_TWC,
|
||||
PMUX_FUNC_UARTA,
|
||||
PMUX_FUNC_UARTB,
|
||||
PMUX_FUNC_UARTC,
|
||||
PMUX_FUNC_UARTD,
|
||||
PMUX_FUNC_UARTE,
|
||||
PMUX_FUNC_ULPI,
|
||||
PMUX_FUNC_VI,
|
||||
PMUX_FUNC_VI_SENSOR_CLK,
|
||||
PMUX_FUNC_XIO,
|
||||
PMUX_FUNC_SAFE,
|
||||
|
||||
#define TEGRA_TRISTATE_REGS 4
|
||||
/* These don't have a name, but can be used in the table */
|
||||
PMUX_FUNC_RSVD1,
|
||||
PMUX_FUNC_RSVD2,
|
||||
PMUX_FUNC_RSVD3,
|
||||
PMUX_FUNC_RSVD4,
|
||||
PMUX_FUNC_RSVD, /* Not valid and should not be used */
|
||||
|
||||
PMUX_FUNC_COUNT,
|
||||
|
||||
PMUX_FUNC_NONE = -1,
|
||||
};
|
||||
|
||||
/* return 1 if a pmux_func is in range */
|
||||
#define pmux_func_isvalid(func) ((func) >= 0 && (func) < PMUX_FUNC_COUNT && \
|
||||
(func) != PMUX_FUNC_RSVD)
|
||||
|
||||
/* The pullup/pulldown state of a pin group */
|
||||
enum pmux_pull {
|
||||
PMUX_PULL_NORMAL = 0,
|
||||
PMUX_PULL_DOWN,
|
||||
PMUX_PULL_UP,
|
||||
};
|
||||
|
||||
/* Defines whether a pin group is tristated or in normal operation */
|
||||
enum pmux_tristate {
|
||||
PMUX_TRI_NORMAL = 0,
|
||||
PMUX_TRI_TRISTATE = 1,
|
||||
};
|
||||
|
||||
/* Available power domains used by pin groups */
|
||||
enum pmux_vddio {
|
||||
PMUX_VDDIO_BB = 0,
|
||||
PMUX_VDDIO_LCD,
|
||||
PMUX_VDDIO_VI,
|
||||
PMUX_VDDIO_UART,
|
||||
PMUX_VDDIO_DDR,
|
||||
PMUX_VDDIO_NAND,
|
||||
PMUX_VDDIO_SYS,
|
||||
PMUX_VDDIO_AUDIO,
|
||||
PMUX_VDDIO_SD,
|
||||
|
||||
PMUX_VDDIO_NONE
|
||||
};
|
||||
|
||||
enum {
|
||||
PMUX_TRISTATE_REGS = 4,
|
||||
PMUX_MUX_REGS = 7,
|
||||
PMUX_PULL_REGS = 5,
|
||||
};
|
||||
|
||||
/* APB MISC Pin Mux and Tristate (APB_MISC_PP_) registers */
|
||||
struct pmux_tri_ctlr {
|
||||
uint pmt_reserved0; /* ABP_MISC_PP_ reserved offset 00 */
|
||||
uint pmt_reserved1; /* ABP_MISC_PP_ reserved offset 04 */
|
||||
uint pmt_strap_opt_a; /* _STRAPPING_OPT_A_0, offset 08 */
|
||||
uint pmt_strap_opt_a; /* _STRAPPING_OPT_A_0, offset 08 */
|
||||
uint pmt_reserved2; /* ABP_MISC_PP_ reserved offset 0C */
|
||||
uint pmt_reserved3; /* ABP_MISC_PP_ reserved offset 10 */
|
||||
uint pmt_tri[TEGRA_TRISTATE_REGS]; /* _TRI_STATE_REG_A/B/C/D_0 14-20 */
|
||||
uint pmt_cfg_ctl; /* _CONFIG_CTL_0, offset 24 */
|
||||
uint pmt_tri[PMUX_TRISTATE_REGS];/* _TRI_STATE_REG_A/B/C/D_0 14-20 */
|
||||
uint pmt_cfg_ctl; /* _CONFIG_CTL_0, offset 24 */
|
||||
|
||||
uint pmt_reserved[22]; /* ABP_MISC_PP_ reserved offs 28-7C */
|
||||
|
||||
uint pmt_ctl_a; /* _PIN_MUX_CTL_A_0, offset 80 */
|
||||
uint pmt_ctl_b; /* _PIN_MUX_CTL_B_0, offset 84 */
|
||||
uint pmt_ctl_c; /* _PIN_MUX_CTL_C_0, offset 88 */
|
||||
uint pmt_ctl_d; /* _PIN_MUX_CTL_D_0, offset 8C */
|
||||
uint pmt_ctl_e; /* _PIN_MUX_CTL_E_0, offset 90 */
|
||||
uint pmt_ctl_f; /* _PIN_MUX_CTL_F_0, offset 94 */
|
||||
uint pmt_ctl_g; /* _PIN_MUX_CTL_G_0, offset 98 */
|
||||
uint pmt_ctl[PMUX_MUX_REGS]; /* _PIN_MUX_CTL_A-G_0, offset 80 */
|
||||
uint pmt_reserved4; /* ABP_MISC_PP_ reserved offset 9c */
|
||||
uint pmt_pull[PMUX_PULL_REGS]; /* APB_MISC_PP_PULLUPDOWN_REG_A-E */
|
||||
};
|
||||
|
||||
/* Converts a pin number to a tristate register: 0=A, 1=B, 2=C, 3=D */
|
||||
#define TRISTATE_REG(id) ((id) >> 5)
|
||||
/*
|
||||
* This defines the configuration for a pin, including the function assigned,
|
||||
* pull up/down settings and tristate settings. Having set up one of these
|
||||
* you can call pinmux_config_pingroup() to configure a pin in one step. Also
|
||||
* available is pinmux_config_table() to configure a list of pins.
|
||||
*/
|
||||
struct pingroup_config {
|
||||
enum pmux_pingrp pingroup; /* pin group PINGRP_... */
|
||||
enum pmux_func func; /* function to assign FUNC_... */
|
||||
enum pmux_pull pull; /* pull up/down/normal PMUX_PULL_...*/
|
||||
enum pmux_tristate tristate; /* tristate or normal PMUX_TRI_... */
|
||||
};
|
||||
|
||||
/* Mask value for a tristate (within TRISTATE_REG(id)) */
|
||||
#define TRISTATE_MASK(id) (1 << ((id) & 0x1f))
|
||||
/* Set a pin group to tristate */
|
||||
void pinmux_tristate_enable(enum pmux_pingrp pin);
|
||||
|
||||
/* Set a pin to tristate */
|
||||
void pinmux_tristate_enable(enum pmux_pin pin);
|
||||
/* Set a pin group to normal (non tristate) */
|
||||
void pinmux_tristate_disable(enum pmux_pingrp pin);
|
||||
|
||||
/* Set a pin to normal (non tristate) */
|
||||
void pinmux_tristate_disable(enum pmux_pin pin);
|
||||
/* Set the pull up/down feature for a pin group */
|
||||
void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd);
|
||||
|
||||
/* Set the mux function for a pin group */
|
||||
void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func);
|
||||
|
||||
/* Set the complete configuration for a pin group */
|
||||
void pinmux_config_pingroup(struct pingroup_config *config);
|
||||
|
||||
void pinmux_set_tristate(enum pmux_pingrp pin, int enable);
|
||||
|
||||
/**
|
||||
* Configuure a list of pin groups
|
||||
*
|
||||
* @param config List of config items
|
||||
* @param len Number of config items in list
|
||||
*/
|
||||
void pinmux_config_table(struct pingroup_config *config, int len);
|
||||
|
||||
#endif /* PINMUX_H */
|
||||
|
|
File diff suppressed because it is too large
Load diff
|
@ -77,6 +77,7 @@ u32 omap_boot_mode(void);
|
|||
|
||||
/* SPL common function s*/
|
||||
void spl_parse_image_header(const struct image_header *header);
|
||||
void omap_rev_string(char *omap_rev_string);
|
||||
|
||||
/* NAND SPL functions */
|
||||
void spl_nand_load_image(void);
|
||||
|
|
|
@ -82,7 +82,6 @@ extern void rtl8019_get_enetaddr (uchar * addr);
|
|||
#include <i2c.h>
|
||||
#endif
|
||||
|
||||
|
||||
/************************************************************************
|
||||
* Coloured LED functionality
|
||||
************************************************************************
|
||||
|
|
|
@ -25,6 +25,7 @@
|
|||
|
||||
#include <common.h>
|
||||
#include <mvmfp.h>
|
||||
#include <asm/arch/cpu.h>
|
||||
#include <asm/arch/mfp.h>
|
||||
#include <asm/arch/armada100.h>
|
||||
|
||||
|
|
|
@ -24,8 +24,12 @@
|
|||
|
||||
#include <common.h>
|
||||
#include <mvmfp.h>
|
||||
#include <i2c.h>
|
||||
#include <asm/arch/mfp.h>
|
||||
#include <asm/arch/cpu.h>
|
||||
#ifdef CONFIG_GENERIC_MMC
|
||||
#include <sdhci.h>
|
||||
#endif
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
|
@ -40,6 +44,20 @@ int board_early_init_f(void)
|
|||
MFP53_CI2C_SCL,
|
||||
MFP54_CI2C_SDA,
|
||||
|
||||
/* MMC1 */
|
||||
MFP_MMC1_DAT7,
|
||||
MFP_MMC1_DAT6,
|
||||
MFP_MMC1_DAT5,
|
||||
MFP_MMC1_DAT4,
|
||||
MFP_MMC1_DAT3,
|
||||
MFP_MMC1_DAT2,
|
||||
MFP_MMC1_DAT1,
|
||||
MFP_MMC1_DAT0,
|
||||
MFP_MMC1_CMD,
|
||||
MFP_MMC1_CLK,
|
||||
MFP_MMC1_CD,
|
||||
MFP_MMC1_WP,
|
||||
|
||||
MFP_EOC /*End of configureation*/
|
||||
};
|
||||
/* configure MFP's */
|
||||
|
@ -56,3 +74,28 @@ int board_init(void)
|
|||
gd->bd->bi_boot_params = panth_sdram_base(0) + 0x100;
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_GENERIC_MMC
|
||||
#define I2C_SLAVE_ADDR 0x34
|
||||
#define LDO13_REG 0x28
|
||||
#define LDO_V30 0x6
|
||||
#define LDO_VOLTAGE(x) ((x & 0x7) << 1)
|
||||
#define LDO_EN 0x1
|
||||
int board_mmc_init(bd_t *bd)
|
||||
{
|
||||
ulong mmc_base_address[CONFIG_SYS_MMC_NUM] = CONFIG_SYS_MMC_BASE;
|
||||
u8 i, data;
|
||||
|
||||
/* set LDO 13 to 3.0v */
|
||||
data = LDO_VOLTAGE(LDO_V30) | LDO_EN;
|
||||
i2c_write(I2C_SLAVE_ADDR, LDO13_REG, 1, &data, 1);
|
||||
|
||||
for (i = 0; i < CONFIG_SYS_MMC_NUM; i++) {
|
||||
if (mv_sdh_init(mmc_base_address[i], 0, 0,
|
||||
SDHCI_QUIRK_32BIT_DMA_ADDR))
|
||||
return 1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
|
54
board/Marvell/dreamplug/Makefile
Normal file
54
board/Marvell/dreamplug/Makefile
Normal file
|
@ -0,0 +1,54 @@
|
|||
#
|
||||
# (C) Copyright 2011
|
||||
# Jason Cooper <u-boot@lakedaemon.net>
|
||||
#
|
||||
# Based on work by:
|
||||
# Marvell Semiconductor <www.marvell.com>
|
||||
# Written-by: Siddarth Gore <gores@marvell.com>
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
|
||||
# MA 02110-1301 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
|
||||
LIB = $(obj)lib$(BOARD).o
|
||||
|
||||
COBJS := dreamplug.o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
SOBJS := $(addprefix $(obj),$(SOBJS))
|
||||
|
||||
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
|
||||
$(call cmd_link_o_target, $(OBJS) $(SOBJS))
|
||||
|
||||
clean:
|
||||
rm -f $(SOBJS) $(OBJS)
|
||||
|
||||
distclean: clean
|
||||
rm -f $(LIB) core *.bak .depend
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk
|
||||
|
||||
sinclude $(obj).depend
|
||||
|
||||
#########################################################################
|
151
board/Marvell/dreamplug/dreamplug.c
Normal file
151
board/Marvell/dreamplug/dreamplug.c
Normal file
|
@ -0,0 +1,151 @@
|
|||
/*
|
||||
* (C) Copyright 2011
|
||||
* Jason Cooper <u-boot@lakedaemon.net>
|
||||
*
|
||||
* Based on work by:
|
||||
* Marvell Semiconductor <www.marvell.com>
|
||||
* Written-by: Siddarth Gore <gores@marvell.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
|
||||
* MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <miiphy.h>
|
||||
#include <asm/arch/kirkwood.h>
|
||||
#include <asm/arch/mpp.h>
|
||||
#include "dreamplug.h"
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
/*
|
||||
* default gpio configuration
|
||||
* There are maximum 64 gpios controlled through 2 sets of registers
|
||||
* the below configuration configures mainly initial LED status
|
||||
*/
|
||||
kw_config_gpio(DREAMPLUG_OE_VAL_LOW,
|
||||
DREAMPLUG_OE_VAL_HIGH,
|
||||
DREAMPLUG_OE_LOW, DREAMPLUG_OE_HIGH);
|
||||
|
||||
/* Multi-Purpose Pins Functionality configuration */
|
||||
u32 kwmpp_config[] = {
|
||||
MPP0_SPI_SCn, /* SPI Flash */
|
||||
MPP1_SPI_MOSI,
|
||||
MPP2_SPI_SCK,
|
||||
MPP3_SPI_MISO,
|
||||
MPP4_NF_IO6,
|
||||
MPP5_NF_IO7,
|
||||
MPP6_SYSRST_OUTn,
|
||||
MPP7_GPO,
|
||||
MPP8_TW_SDA,
|
||||
MPP9_TW_SCK,
|
||||
MPP10_UART0_TXD, /* Serial */
|
||||
MPP11_UART0_RXD,
|
||||
MPP12_SD_CLK, /* SDIO Slot */
|
||||
MPP13_SD_CMD,
|
||||
MPP14_SD_D0,
|
||||
MPP15_SD_D1,
|
||||
MPP16_SD_D2,
|
||||
MPP17_SD_D3,
|
||||
MPP18_NF_IO0,
|
||||
MPP19_NF_IO1,
|
||||
MPP20_GE1_0, /* Gigabit Ethernet */
|
||||
MPP21_GE1_1,
|
||||
MPP22_GE1_2,
|
||||
MPP23_GE1_3,
|
||||
MPP24_GE1_4,
|
||||
MPP25_GE1_5,
|
||||
MPP26_GE1_6,
|
||||
MPP27_GE1_7,
|
||||
MPP28_GE1_8,
|
||||
MPP29_GE1_9,
|
||||
MPP30_GE1_10,
|
||||
MPP31_GE1_11,
|
||||
MPP32_GE1_12,
|
||||
MPP33_GE1_13,
|
||||
MPP34_GE1_14,
|
||||
MPP35_GE1_15,
|
||||
MPP36_GPIO, /* 7 external GPIO pins (36 - 45) */
|
||||
MPP37_GPIO,
|
||||
MPP38_GPIO,
|
||||
MPP39_GPIO,
|
||||
MPP40_TDM_SPI_SCK,
|
||||
MPP41_TDM_SPI_MISO,
|
||||
MPP42_TDM_SPI_MOSI,
|
||||
MPP43_GPIO,
|
||||
MPP44_GPIO,
|
||||
MPP45_GPIO,
|
||||
MPP46_GPIO,
|
||||
MPP47_GPIO, /* Bluetooth LED */
|
||||
MPP48_GPIO, /* Wifi LED */
|
||||
MPP49_GPIO, /* Wifi AP LED */
|
||||
0
|
||||
};
|
||||
kirkwood_mpp_conf(kwmpp_config);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
/* adress of boot parameters */
|
||||
gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_RESET_PHY_R
|
||||
void mv_phy_88e1116_init(char *name)
|
||||
{
|
||||
u16 reg;
|
||||
u16 devadr;
|
||||
|
||||
if (miiphy_set_current_dev(name))
|
||||
return;
|
||||
|
||||
/* command to read PHY dev address */
|
||||
if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
|
||||
printf("Err..%s could not read PHY dev address\n",
|
||||
__func__);
|
||||
return;
|
||||
}
|
||||
|
||||
/*
|
||||
* Enable RGMII delay on Tx and Rx for CPU port
|
||||
* Ref: sec 4.7.2 of chip datasheet
|
||||
*/
|
||||
miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
|
||||
miiphy_read(name, devadr, MV88E1116_MAC_CTRL2_REG, ®);
|
||||
reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
|
||||
miiphy_write(name, devadr, MV88E1116_MAC_CTRL2_REG, reg);
|
||||
miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
|
||||
|
||||
/* reset the phy */
|
||||
miiphy_reset(name, devadr);
|
||||
|
||||
printf("88E1116 Initialized on %s\n", name);
|
||||
}
|
||||
|
||||
void reset_phy(void)
|
||||
{
|
||||
/* configure and initialize both PHY's */
|
||||
mv_phy_88e1116_init("egiga0");
|
||||
mv_phy_88e1116_init("egiga1");
|
||||
}
|
||||
#endif /* CONFIG_RESET_PHY_R */
|
42
board/Marvell/dreamplug/dreamplug.h
Normal file
42
board/Marvell/dreamplug/dreamplug.h
Normal file
|
@ -0,0 +1,42 @@
|
|||
/*
|
||||
* (C) Copyright 2011
|
||||
* Jason Cooper <u-boot@lakedaemon.net>
|
||||
*
|
||||
* Based on work by:
|
||||
* Marvell Semiconductor <www.marvell.com>
|
||||
* Written-by: Siddarth Gore <gores@marvell.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
|
||||
* MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#ifndef __DREAMPLUG_H
|
||||
#define __DREAMPLUG_H
|
||||
|
||||
#define DREAMPLUG_OE_LOW (~(0))
|
||||
#define DREAMPLUG_OE_HIGH (~(0))
|
||||
#define DREAMPLUG_OE_VAL_LOW 0
|
||||
#define DREAMPLUG_OE_VAL_HIGH (0xf << 16) /* 4 LED Pins high */
|
||||
|
||||
/* PHY related */
|
||||
#define MV88E1116_MAC_CTRL2_REG 21
|
||||
#define MV88E1116_PGADR_REG 22
|
||||
#define MV88E1116_RGMII_TXTM_CTRL (1 << 4)
|
||||
#define MV88E1116_RGMII_RXTM_CTRL (1 << 5)
|
||||
|
||||
#endif /* __DREAMPLUG_H */
|
163
board/Marvell/dreamplug/kwbimage.cfg
Normal file
163
board/Marvell/dreamplug/kwbimage.cfg
Normal file
|
@ -0,0 +1,163 @@
|
|||
#
|
||||
# (C) Copyright 2011
|
||||
# Jason Cooper <u-boot@lakedaemon.net>
|
||||
#
|
||||
# Based on work by:
|
||||
# Marvell Semiconductor <www.marvell.com>
|
||||
# Written-by: Siddarth Gore <gores@marvell.com>
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
|
||||
# MA 02110-1301 USA
|
||||
#
|
||||
# Refer docs/README.kwimage for more details about how-to configure
|
||||
# and create kirkwood boot image
|
||||
#
|
||||
|
||||
# Boot Media configurations
|
||||
BOOT_FROM spi
|
||||
|
||||
# SOC registers configuration using bootrom header extension
|
||||
# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
|
||||
|
||||
# Configure RGMII-0/1 interface pad voltage to 1.8V
|
||||
DATA 0xFFD100e0 0x1b1b9b9b
|
||||
|
||||
#Dram initalization for SINGLE x16 CL=5 @ 400MHz
|
||||
DATA 0xFFD01400 0x43000c30 # DDR Configuration register
|
||||
# bit13-0: 0xc30 (3120 DDR2 clks refresh rate)
|
||||
# bit23-14: zero
|
||||
# bit24: 1= enable exit self refresh mode on DDR access
|
||||
# bit25: 1 required
|
||||
# bit29-26: zero
|
||||
# bit31-30: 01
|
||||
|
||||
DATA 0xFFD01404 0x37543000 # DDR Controller Control Low
|
||||
# bit 4: 0=addr/cmd in smame cycle
|
||||
# bit 5: 0=clk is driven during self refresh, we don't care for APX
|
||||
# bit 6: 0=use recommended falling edge of clk for addr/cmd
|
||||
# bit14: 0=input buffer always powered up
|
||||
# bit18: 1=cpu lock transaction enabled
|
||||
# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
|
||||
# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
|
||||
# bit30-28: 3 required
|
||||
# bit31: 0=no additional STARTBURST delay
|
||||
|
||||
DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1)
|
||||
# bit3-0: TRAS lsbs
|
||||
# bit7-4: TRCD
|
||||
# bit11- 8: TRP
|
||||
# bit15-12: TWR
|
||||
# bit19-16: TWTR
|
||||
# bit20: TRAS msb
|
||||
# bit23-21: 0x0
|
||||
# bit27-24: TRRD
|
||||
# bit31-28: TRTP
|
||||
|
||||
DATA 0xFFD0140C 0x00000a33 # DDR Timing (High)
|
||||
# bit6-0: TRFC
|
||||
# bit8-7: TR2R
|
||||
# bit10-9: TR2W
|
||||
# bit12-11: TW2W
|
||||
# bit31-13: zero required
|
||||
|
||||
DATA 0xFFD01410 0x000000cc # DDR Address Control
|
||||
# bit1-0: 01, Cs0width=x8
|
||||
# bit3-2: 10, Cs0size=1Gb
|
||||
# bit5-4: 01, Cs1width=x8
|
||||
# bit7-6: 10, Cs1size=1Gb
|
||||
# bit9-8: 00, Cs2width=nonexistent
|
||||
# bit11-10: 00, Cs2size =nonexistent
|
||||
# bit13-12: 00, Cs3width=nonexistent
|
||||
# bit15-14: 00, Cs3size =nonexistent
|
||||
# bit16: 0, Cs0AddrSel
|
||||
# bit17: 0, Cs1AddrSel
|
||||
# bit18: 0, Cs2AddrSel
|
||||
# bit19: 0, Cs3AddrSel
|
||||
# bit31-20: 0 required
|
||||
|
||||
DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
|
||||
# bit0: 0, OpenPage enabled
|
||||
# bit31-1: 0 required
|
||||
|
||||
DATA 0xFFD01418 0x00000000 # DDR Operation
|
||||
# bit3-0: 0x0, DDR cmd
|
||||
# bit31-4: 0 required
|
||||
|
||||
DATA 0xFFD0141C 0x00000C52 # DDR Mode
|
||||
# bit2-0: 2, BurstLen=2 required
|
||||
# bit3: 0, BurstType=0 required
|
||||
# bit6-4: 4, CL=5
|
||||
# bit7: 0, TestMode=0 normal
|
||||
# bit8: 0, DLL reset=0 normal
|
||||
# bit11-9: 6, auto-precharge write recovery ????????????
|
||||
# bit12: 0, PD must be zero
|
||||
# bit31-13: 0 required
|
||||
|
||||
DATA 0xFFD01420 0x00000040 # DDR Extended Mode
|
||||
# bit0: 0, DDR DLL enabled
|
||||
# bit1: 0, DDR drive strenght normal
|
||||
# bit2: 0, DDR ODT control lsd (disabled)
|
||||
# bit5-3: 000, required
|
||||
# bit6: 1, DDR ODT control msb, (disabled)
|
||||
# bit9-7: 000, required
|
||||
# bit10: 0, differential DQS enabled
|
||||
# bit11: 0, required
|
||||
# bit12: 0, DDR output buffer enabled
|
||||
# bit31-13: 0 required
|
||||
|
||||
DATA 0xFFD01424 0x0000F17F # DDR Controller Control High
|
||||
# bit2-0: 111, required
|
||||
# bit3 : 1 , MBUS Burst Chop disabled
|
||||
# bit6-4: 111, required
|
||||
# bit7 : 0
|
||||
# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
|
||||
# bit9 : 0 , no half clock cycle addition to dataout
|
||||
# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
|
||||
# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
|
||||
# bit15-12: 1111 required
|
||||
# bit31-16: 0 required
|
||||
|
||||
DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
|
||||
DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
|
||||
|
||||
DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
|
||||
DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size
|
||||
# bit0: 1, Window enabled
|
||||
# bit1: 0, Write Protect disabled
|
||||
# bit3-2: 00, CS0 hit selected
|
||||
# bit23-4: ones, required
|
||||
# bit31-24: 0x0F, Size (i.e. 256MB)
|
||||
|
||||
DATA 0xFFD01508 0x10000000 # CS[1]n Base address to 256Mb
|
||||
DATA 0xFFD0150C 0x0FFFFFF5 # CS[1]n Size 256Mb Window enabled for CS1
|
||||
|
||||
DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
|
||||
DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
|
||||
|
||||
DATA 0xFFD01494 0x00030000 # DDR ODT Control (Low)
|
||||
DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
|
||||
# bit1-0: 00, ODT0 controlled by ODT Control (low) register above
|
||||
# bit3-2: 01, ODT1 active NEVER!
|
||||
# bit31-4: zero, required
|
||||
|
||||
DATA 0xFFD0149C 0x0000E803 # CPU ODT Control
|
||||
DATA 0xFFD01480 0x00000001 # DDR Initialization Control
|
||||
#bit0=1, enable DDR init upon this register write
|
||||
|
||||
# End of Header extension
|
||||
DATA 0x0 0x0
|
|
@ -30,6 +30,7 @@
|
|||
|
||||
#include <common.h>
|
||||
#include <mvmfp.h>
|
||||
#include <asm/arch/cpu.h>
|
||||
#include <asm/arch/mfp.h>
|
||||
#include <asm/arch/armada100.h>
|
||||
#include <asm/gpio.h>
|
||||
|
@ -72,6 +73,12 @@ int board_early_init_f(void)
|
|||
MFP101_ETH_MDIO,
|
||||
MFP103_ETH_RXDV,
|
||||
|
||||
/* SSP2 */
|
||||
MFP107_SSP2_RXD,
|
||||
MFP108_SSP2_TXD,
|
||||
MFP110_SSP2_CS,
|
||||
MFP111_SSP2_CLK,
|
||||
|
||||
MFP_EOC /*End of configuration*/
|
||||
};
|
||||
/* configure MFP's */
|
||||
|
@ -81,6 +88,9 @@ int board_early_init_f(void)
|
|||
|
||||
int board_init(void)
|
||||
{
|
||||
struct armd1apb2_registers *apb2_regs =
|
||||
(struct armd1apb2_registers *)ARMD1_APBC2_BASE;
|
||||
|
||||
/* arch number of Board */
|
||||
gd->bd->bi_arch_number = MACH_TYPE_SHEEVAD;
|
||||
/* adress of boot parameters */
|
||||
|
@ -90,6 +100,9 @@ int board_init(void)
|
|||
udelay(10);
|
||||
/* Deassert PHY_RST# */
|
||||
gpio_set_value(CONFIG_SYS_GPIO_PHY_RST, GPIO_HIGH);
|
||||
|
||||
/* Enable SSP2 clock */
|
||||
writel(SSP2_APBCLK | SSP2_FNCLK, &apb2_regs->ssp2_clkrst);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
@ -24,6 +24,7 @@
|
|||
|
||||
#include <common.h>
|
||||
#include <miiphy.h>
|
||||
#include <asm/arch/cpu.h>
|
||||
#include <asm/arch/kirkwood.h>
|
||||
#include <asm/arch/mpp.h>
|
||||
#include "guruplug.h"
|
||||
|
|
|
@ -26,6 +26,7 @@
|
|||
|
||||
#include <common.h>
|
||||
#include <netdev.h>
|
||||
#include <asm/arch/cpu.h>
|
||||
#include <asm/arch/kirkwood.h>
|
||||
#include <asm/arch/mpp.h>
|
||||
#include "mv88f6281gtw_ge.h"
|
||||
|
|
|
@ -29,6 +29,7 @@
|
|||
|
||||
#include <common.h>
|
||||
#include <miiphy.h>
|
||||
#include <asm/arch/cpu.h>
|
||||
#include <asm/arch/kirkwood.h>
|
||||
#include <asm/arch/mpp.h>
|
||||
#include "openrd.h"
|
||||
|
|
|
@ -25,6 +25,7 @@
|
|||
#include <common.h>
|
||||
#include <miiphy.h>
|
||||
#include <netdev.h>
|
||||
#include <asm/arch/cpu.h>
|
||||
#include <asm/arch/kirkwood.h>
|
||||
#include <asm/arch/mpp.h>
|
||||
#include "rd6281a.h"
|
||||
|
|
|
@ -24,6 +24,7 @@
|
|||
|
||||
#include <common.h>
|
||||
#include <miiphy.h>
|
||||
#include <asm/arch/cpu.h>
|
||||
#include <asm/arch/kirkwood.h>
|
||||
#include <asm/arch/mpp.h>
|
||||
#include "sheevaplug.h"
|
||||
|
|
|
@ -25,8 +25,10 @@
|
|||
#include <netdev.h>
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/imx-regs.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <asm/io.h>
|
||||
#include <nand.h>
|
||||
#include <pmic.h>
|
||||
#include <fsl_pmic.h>
|
||||
#include <asm/gpio.h>
|
||||
#include "qong_fpga.h"
|
||||
|
@ -41,7 +43,7 @@ void hw_watchdog_reset(void)
|
|||
}
|
||||
#endif
|
||||
|
||||
int dram_init (void)
|
||||
int dram_init(void)
|
||||
{
|
||||
/* dram_init must store complete ramsize in gd->ram_size */
|
||||
gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
|
||||
|
@ -58,14 +60,20 @@ static void qong_fpga_reset(void)
|
|||
udelay(300);
|
||||
}
|
||||
|
||||
int board_early_init_f (void)
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
#ifdef CONFIG_QONG_FPGA
|
||||
/* CS1: FPGA/Network Controller/GPIO */
|
||||
/* 16-bit, no DTACK */
|
||||
__REG(CSCR_U(1)) = 0x00000A01;
|
||||
__REG(CSCR_L(1)) = 0x20040501;
|
||||
__REG(CSCR_A(1)) = 0x04020C00;
|
||||
/* CS1: FPGA/Network Controller/GPIO, 16-bit, no DTACK */
|
||||
static const struct mxc_weimcs cs1 = {
|
||||
/* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
|
||||
CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 0, 10, 0, 0, 1),
|
||||
/* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
|
||||
CSCR_L(2, 0, 0, 4, 0, 0, 5, 0, 0, 0, 0, 1),
|
||||
/* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
|
||||
CSCR_A(0, 4, 0, 2, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0)
|
||||
};
|
||||
|
||||
mxc_setup_weimcs(1, &cs1);
|
||||
|
||||
/* setup pins for FPGA */
|
||||
mx31_gpio_mux(IOMUX_MODE(0x76, MUX_CTL_GPIO));
|
||||
|
@ -141,55 +149,21 @@ int board_early_init_f (void)
|
|||
|
||||
}
|
||||
|
||||
int board_init (void)
|
||||
int board_init(void)
|
||||
{
|
||||
/* Chip selects */
|
||||
/* CS0: Nor Flash #0 - it must be init'ed when executing from DDR */
|
||||
/* Assumptions: HCLK = 133 MHz, tACC = 130ns */
|
||||
__REG(CSCR_U(0)) = ((0 << 31) | /* SP */
|
||||
(0 << 30) | /* WP */
|
||||
(0 << 28) | /* BCD */
|
||||
(0 << 24) | /* BCS */
|
||||
(0 << 22) | /* PSZ */
|
||||
(0 << 21) | /* PME */
|
||||
(0 << 20) | /* SYNC */
|
||||
(0 << 16) | /* DOL */
|
||||
(3 << 14) | /* CNC */
|
||||
(21 << 8) | /* WSC */
|
||||
(0 << 7) | /* EW */
|
||||
(0 << 4) | /* WWS */
|
||||
(6 << 0) /* EDC */
|
||||
);
|
||||
static const struct mxc_weimcs cs0 = {
|
||||
/* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
|
||||
CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 21, 0, 0, 6),
|
||||
/* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
|
||||
CSCR_L(0, 1, 3, 3, 1, 1, 5, 1, 0, 0, 0, 1),
|
||||
/* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
|
||||
CSCR_A(0, 1, 2, 2, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0)
|
||||
};
|
||||
|
||||
__REG(CSCR_L(0)) = ((2 << 28) | /* OEA */
|
||||
(1 << 24) | /* OEN */
|
||||
(3 << 20) | /* EBWA */
|
||||
(3 << 16) | /* EBWN */
|
||||
(1 << 12) | /* CSA */
|
||||
(1 << 11) | /* EBC */
|
||||
(5 << 8) | /* DSZ */
|
||||
(1 << 4) | /* CSN */
|
||||
(0 << 3) | /* PSR */
|
||||
(0 << 2) | /* CRE */
|
||||
(0 << 1) | /* WRAP */
|
||||
(1 << 0) /* CSEN */
|
||||
);
|
||||
|
||||
__REG(CSCR_A(0)) = ((2 << 28) | /* EBRA */
|
||||
(1 << 24) | /* EBRN */
|
||||
(2 << 20) | /* RWA */
|
||||
(2 << 16) | /* RWN */
|
||||
(0 << 15) | /* MUM */
|
||||
(0 << 13) | /* LAH */
|
||||
(2 << 10) | /* LBN */
|
||||
(0 << 8) | /* LBA */
|
||||
(0 << 6) | /* DWW */
|
||||
(0 << 4) | /* DCT */
|
||||
(0 << 3) | /* WWU */
|
||||
(0 << 2) | /* AGE */
|
||||
(0 << 1) | /* CNC2 */
|
||||
(0 << 0) /* FCE */
|
||||
);
|
||||
mxc_setup_weimcs(0, &cs0);
|
||||
|
||||
/* board id for linux */
|
||||
gd->bd->bi_arch_number = MACH_TYPE_QONG;
|
||||
|
@ -203,11 +177,15 @@ int board_init (void)
|
|||
int board_late_init(void)
|
||||
{
|
||||
u32 val;
|
||||
struct pmic *p;
|
||||
|
||||
pmic_init();
|
||||
p = get_pmic();
|
||||
|
||||
/* Enable RTC battery */
|
||||
val = pmic_reg_read(REG_POWER_CTL0);
|
||||
pmic_reg_write(REG_POWER_CTL0, val | COINCHEN);
|
||||
pmic_reg_write(REG_INT_STATUS1, RTCRSTI);
|
||||
pmic_reg_read(p, REG_POWER_CTL0, &val);
|
||||
pmic_reg_write(p, REG_POWER_CTL0, val | COINCHEN);
|
||||
pmic_reg_write(p, REG_INT_STATUS1, RTCRSTI);
|
||||
|
||||
#ifdef CONFIG_HW_WATCHDOG
|
||||
mxc_hw_watchdog_enable();
|
||||
|
@ -216,13 +194,13 @@ int board_late_init(void)
|
|||
return 0;
|
||||
}
|
||||
|
||||
int checkboard (void)
|
||||
int checkboard(void)
|
||||
{
|
||||
printf("Board: DAVE/DENX Qong\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
int misc_init_r (void)
|
||||
int misc_init_r(void)
|
||||
{
|
||||
#ifdef CONFIG_QONG_FPGA
|
||||
u32 tmp;
|
||||
|
@ -247,11 +225,18 @@ int board_eth_init(bd_t *bis)
|
|||
#if defined(CONFIG_QONG_FPGA) && defined(CONFIG_NAND_PLAT)
|
||||
static void board_nand_setup(void)
|
||||
{
|
||||
|
||||
/* CS3: NAND 8-bit */
|
||||
__REG(CSCR_U(3)) = 0x00004f00;
|
||||
__REG(CSCR_L(3)) = 0x20013b31;
|
||||
__REG(CSCR_A(3)) = 0x00020800;
|
||||
static const struct mxc_weimcs cs3 = {
|
||||
/* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
|
||||
CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 1, 15, 0, 0, 0),
|
||||
/* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
|
||||
CSCR_L(2, 0, 0, 1, 3, 1, 3, 3, 0, 0, 0, 1),
|
||||
/* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
|
||||
CSCR_A(0, 0, 0, 2, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0)
|
||||
};
|
||||
|
||||
mxc_setup_weimcs(3, &cs3);
|
||||
|
||||
__REG(IOMUXC_GPR) |= 1 << 13;
|
||||
|
||||
mx31_gpio_mux(IOMUX_MODE(MUX_CTL_NFC_WP, MUX_CTL_IN_GPIO));
|
||||
|
|
|
@ -40,6 +40,8 @@
|
|||
#include <asm/arch/emif_defs.h>
|
||||
#include <asm/arch/emac_defs.h>
|
||||
#include <asm/io.h>
|
||||
#include <nand.h>
|
||||
#include <asm/arch/nand_defs.h>
|
||||
#include <asm/arch/davinci_misc.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
@ -98,6 +100,56 @@ static const struct pinmux_config i2c_pins[] = {
|
|||
{ pinmux(8), 2, 4 }
|
||||
};
|
||||
|
||||
#ifdef CONFIG_USE_NAND
|
||||
/* NAND pin muxer settings */
|
||||
const struct pinmux_config aemif_pins[] = {
|
||||
{ pinmux(13), 1, 6 },
|
||||
{ pinmux(13), 1, 7 },
|
||||
{ pinmux(14), 1, 0 },
|
||||
{ pinmux(14), 1, 1 },
|
||||
{ pinmux(14), 1, 2 },
|
||||
{ pinmux(14), 1, 3 },
|
||||
{ pinmux(14), 1, 4 },
|
||||
{ pinmux(14), 1, 5 },
|
||||
{ pinmux(14), 1, 6 },
|
||||
{ pinmux(14), 1, 7 },
|
||||
{ pinmux(15), 1, 0 },
|
||||
{ pinmux(15), 1, 1 },
|
||||
{ pinmux(15), 1, 2 },
|
||||
{ pinmux(15), 1, 3 },
|
||||
{ pinmux(15), 1, 4 },
|
||||
{ pinmux(15), 1, 5 },
|
||||
{ pinmux(15), 1, 6 },
|
||||
{ pinmux(15), 1, 7 },
|
||||
{ pinmux(16), 1, 0 },
|
||||
{ pinmux(16), 1, 1 },
|
||||
{ pinmux(16), 1, 2 },
|
||||
{ pinmux(16), 1, 3 },
|
||||
{ pinmux(16), 1, 4 },
|
||||
{ pinmux(16), 1, 5 },
|
||||
{ pinmux(16), 1, 6 },
|
||||
{ pinmux(16), 1, 7 },
|
||||
{ pinmux(17), 1, 0 },
|
||||
{ pinmux(17), 1, 1 },
|
||||
{ pinmux(17), 1, 2 },
|
||||
{ pinmux(17), 1, 3 },
|
||||
{ pinmux(17), 1, 4 },
|
||||
{ pinmux(17), 1, 5 },
|
||||
{ pinmux(17), 1, 6 },
|
||||
{ pinmux(17), 1, 7 },
|
||||
{ pinmux(18), 1, 0 },
|
||||
{ pinmux(18), 1, 1 },
|
||||
{ pinmux(18), 1, 2 },
|
||||
{ pinmux(18), 1, 3 },
|
||||
{ pinmux(18), 1, 4 },
|
||||
{ pinmux(18), 1, 5 },
|
||||
{ pinmux(18), 1, 6 },
|
||||
{ pinmux(18), 1, 7 },
|
||||
{ pinmux(10), 1, 0 }
|
||||
};
|
||||
#endif
|
||||
|
||||
|
||||
/* USB0_DRVVBUS pin muxer settings */
|
||||
static const struct pinmux_config usb_pins[] = {
|
||||
{ pinmux(9), 1, 1 }
|
||||
|
@ -114,6 +166,7 @@ static const struct pinmux_resource pinmuxes[] = {
|
|||
#endif
|
||||
#ifdef CONFIG_USE_NAND
|
||||
PINMUX_ITEM(emifa_nand_pins),
|
||||
PINMUX_ITEM(aemif_pins),
|
||||
#endif
|
||||
#if defined(CONFIG_DRIVER_TI_EMAC)
|
||||
PINMUX_ITEM(emac_pins),
|
||||
|
@ -184,6 +237,16 @@ int board_init(void)
|
|||
return(0);
|
||||
}
|
||||
|
||||
|
||||
#ifdef CONFIG_NAND_DAVINCI
|
||||
int board_nand_init(struct nand_chip *nand)
|
||||
{
|
||||
davinci_nand_init(nand);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_DRIVER_TI_EMAC)
|
||||
|
||||
#define PHY_SW_I2C_ADDR 0x5f /* Address of PHY on i2c bus */
|
||||
|
|
|
@ -278,6 +278,20 @@ u32 get_board_rev(void)
|
|||
return rev;
|
||||
}
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
/*
|
||||
* Power on required peripherals
|
||||
* ARM does not have access by default to PSC0 and PSC1
|
||||
* assuming here that the DSP bootloader has set the IOPU
|
||||
* such that PSC access is available to ARM
|
||||
*/
|
||||
if (da8xx_configure_lpsc_items(lpsc, ARRAY_SIZE(lpsc)))
|
||||
return 1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
#ifdef CONFIG_USE_NOR
|
||||
|
@ -310,15 +324,6 @@ int board_init(void)
|
|||
/* address of boot parameters */
|
||||
gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
|
||||
|
||||
/*
|
||||
* Power on required peripherals
|
||||
* ARM does not have access by default to PSC0 and PSC1
|
||||
* assuming here that the DSP bootloader has set the IOPU
|
||||
* such that PSC access is available to ARM
|
||||
*/
|
||||
if (da8xx_configure_lpsc_items(lpsc, ARRAY_SIZE(lpsc)))
|
||||
return 1;
|
||||
|
||||
/* setup the SUSPSRC for ARM to control emulation suspend */
|
||||
writel(readl(&davinci_syscfg_regs->suspsrc) &
|
||||
~(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C |
|
||||
|
|
|
@ -34,6 +34,7 @@
|
|||
#include <i2c.h>
|
||||
#include <mmc.h>
|
||||
#include <fsl_esdhc.h>
|
||||
#include <pmic.h>
|
||||
#include <fsl_pmic.h>
|
||||
#include <mc13892.h>
|
||||
|
||||
|
@ -205,34 +206,38 @@ static void power_init(void)
|
|||
{
|
||||
unsigned int val;
|
||||
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
|
||||
struct pmic *p;
|
||||
|
||||
pmic_init();
|
||||
p = get_pmic();
|
||||
|
||||
/* Write needed to Power Gate 2 register */
|
||||
val = pmic_reg_read(REG_POWER_MISC);
|
||||
pmic_reg_read(p, REG_POWER_MISC, &val);
|
||||
val &= ~PWGT2SPIEN;
|
||||
pmic_reg_write(REG_POWER_MISC, val);
|
||||
pmic_reg_write(p, REG_POWER_MISC, val);
|
||||
|
||||
/* Externally powered */
|
||||
val = pmic_reg_read(REG_CHARGE);
|
||||
pmic_reg_read(p, REG_CHARGE, &val);
|
||||
val |= ICHRG0 | ICHRG1 | ICHRG2 | ICHRG3 | CHGAUTOB;
|
||||
pmic_reg_write(REG_CHARGE, val);
|
||||
pmic_reg_write(p, REG_CHARGE, val);
|
||||
|
||||
/* power up the system first */
|
||||
pmic_reg_write(REG_POWER_MISC, PWUP);
|
||||
pmic_reg_write(p, REG_POWER_MISC, PWUP);
|
||||
|
||||
/* Set core voltage to 1.1V */
|
||||
val = pmic_reg_read(REG_SW_0);
|
||||
pmic_reg_read(p, REG_SW_0, &val);
|
||||
val = (val & ~SWx_VOLT_MASK) | SWx_1_100V;
|
||||
pmic_reg_write(REG_SW_0, val);
|
||||
pmic_reg_write(p, REG_SW_0, val);
|
||||
|
||||
/* Setup VCC (SW2) to 1.25 */
|
||||
val = pmic_reg_read(REG_SW_1);
|
||||
pmic_reg_read(p, REG_SW_1, &val);
|
||||
val = (val & ~SWx_VOLT_MASK) | SWx_1_250V;
|
||||
pmic_reg_write(REG_SW_1, val);
|
||||
pmic_reg_write(p, REG_SW_1, val);
|
||||
|
||||
/* Setup 1V2_DIG1 (SW3) to 1.25 */
|
||||
val = pmic_reg_read(REG_SW_2);
|
||||
pmic_reg_read(p, REG_SW_2, &val);
|
||||
val = (val & ~SWx_VOLT_MASK) | SWx_1_250V;
|
||||
pmic_reg_write(REG_SW_2, val);
|
||||
pmic_reg_write(p, REG_SW_2, val);
|
||||
udelay(50);
|
||||
|
||||
/* Raise the core frequency to 800MHz */
|
||||
|
@ -240,46 +245,46 @@ static void power_init(void)
|
|||
|
||||
/* Set switchers in Auto in NORMAL mode & STANDBY mode */
|
||||
/* Setup the switcher mode for SW1 & SW2*/
|
||||
val = pmic_reg_read(REG_SW_4);
|
||||
pmic_reg_read(p, REG_SW_4, &val);
|
||||
val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) |
|
||||
(SWMODE_MASK << SWMODE2_SHIFT)));
|
||||
val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) |
|
||||
(SWMODE_AUTO_AUTO << SWMODE2_SHIFT);
|
||||
pmic_reg_write(REG_SW_4, val);
|
||||
pmic_reg_write(p, REG_SW_4, val);
|
||||
|
||||
/* Setup the switcher mode for SW3 & SW4 */
|
||||
val = pmic_reg_read(REG_SW_5);
|
||||
pmic_reg_read(p, REG_SW_5, &val);
|
||||
val = (val & ~((SWMODE_MASK << SWMODE3_SHIFT) |
|
||||
(SWMODE_MASK << SWMODE4_SHIFT)));
|
||||
val |= (SWMODE_AUTO_AUTO << SWMODE3_SHIFT) |
|
||||
(SWMODE_AUTO_AUTO << SWMODE4_SHIFT);
|
||||
pmic_reg_write(REG_SW_5, val);
|
||||
pmic_reg_write(p, REG_SW_5, val);
|
||||
|
||||
/* Set VDIG to 1.65V, VGEN3 to 1.8V, VCAM to 2.6V */
|
||||
val = pmic_reg_read(REG_SETTING_0);
|
||||
pmic_reg_read(p, REG_SETTING_0, &val);
|
||||
val &= ~(VCAM_MASK | VGEN3_MASK | VDIG_MASK);
|
||||
val |= VDIG_1_65 | VGEN3_1_8 | VCAM_2_6;
|
||||
pmic_reg_write(REG_SETTING_0, val);
|
||||
pmic_reg_write(p, REG_SETTING_0, val);
|
||||
|
||||
/* Set VVIDEO to 2.775V, VAUDIO to 3V, VSD to 3.15V */
|
||||
val = pmic_reg_read(REG_SETTING_1);
|
||||
pmic_reg_read(p, REG_SETTING_1, &val);
|
||||
val &= ~(VVIDEO_MASK | VSD_MASK | VAUDIO_MASK);
|
||||
val |= VSD_3_15 | VAUDIO_3_0 | VVIDEO_2_775;
|
||||
pmic_reg_write(REG_SETTING_1, val);
|
||||
pmic_reg_write(p, REG_SETTING_1, val);
|
||||
|
||||
/* Configure VGEN3 and VCAM regulators to use external PNP */
|
||||
val = VGEN3CONFIG | VCAMCONFIG;
|
||||
pmic_reg_write(REG_MODE_1, val);
|
||||
pmic_reg_write(p, REG_MODE_1, val);
|
||||
udelay(200);
|
||||
|
||||
/* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */
|
||||
val = VGEN3EN | VGEN3CONFIG | VCAMEN | VCAMCONFIG |
|
||||
VVIDEOEN | VAUDIOEN | VSDEN;
|
||||
pmic_reg_write(REG_MODE_1, val);
|
||||
pmic_reg_write(p, REG_MODE_1, val);
|
||||
|
||||
val = pmic_reg_read(REG_POWER_CTL2);
|
||||
pmic_reg_read(p, REG_POWER_CTL2, &val);
|
||||
val |= WDIRESET;
|
||||
pmic_reg_write(REG_POWER_CTL2, val);
|
||||
pmic_reg_write(p, REG_POWER_CTL2, val);
|
||||
|
||||
udelay(2500);
|
||||
}
|
||||
|
|
|
@ -25,6 +25,7 @@
|
|||
#include <asm/io.h>
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/imx-regs.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
|
@ -48,9 +49,16 @@ int board_early_init_f(void)
|
|||
* the only non-zero field "Wait State Control" is set to half the
|
||||
* default value.
|
||||
*/
|
||||
__REG(CSCR_U(0)) = 0x00000f00;
|
||||
__REG(CSCR_L(0)) = 0x10000D03;
|
||||
__REG(CSCR_A(0)) = 0x00720900;
|
||||
static const struct mxc_weimcs cs0 = {
|
||||
/* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
|
||||
CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 0, 15, 0, 0, 0),
|
||||
/* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
|
||||
CSCR_L(1, 0, 0, 0, 0, 1, 5, 0, 0, 0, 1, 1),
|
||||
/* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
|
||||
CSCR_A(0, 0, 7, 2, 0, 0, 2, 1, 0, 0, 0, 0, 0, 0)
|
||||
};
|
||||
|
||||
mxc_setup_weimcs(0, &cs0);
|
||||
|
||||
/* setup pins for UART1 */
|
||||
mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX);
|
||||
|
@ -104,7 +112,7 @@ int board_init(void)
|
|||
return 0;
|
||||
}
|
||||
|
||||
int checkboard (void)
|
||||
int checkboard(void)
|
||||
{
|
||||
printf("Board: MX31ADS\n");
|
||||
return 0;
|
||||
|
|
|
@ -28,6 +28,7 @@
|
|||
#include <netdev.h>
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/imx-regs.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <watchdog.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
@ -50,9 +51,16 @@ int dram_init(void)
|
|||
int board_early_init_f(void)
|
||||
{
|
||||
/* CS5: CPLD incl. network controller */
|
||||
__REG(CSCR_U(5)) = 0x0000d843;
|
||||
__REG(CSCR_L(5)) = 0x22252521;
|
||||
__REG(CSCR_A(5)) = 0x22220a00;
|
||||
static const struct mxc_weimcs cs5 = {
|
||||
/* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
|
||||
CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 24, 0, 4, 3),
|
||||
/* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
|
||||
CSCR_L(2, 2, 2, 5, 2, 0, 5, 2, 0, 0, 0, 1),
|
||||
/* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
|
||||
CSCR_A(2, 2, 2, 2, 0, 0, 2, 2, 0, 0, 0, 0, 0, 0)
|
||||
};
|
||||
|
||||
mxc_setup_weimcs(5, &cs5);
|
||||
|
||||
/* Setup UART1 and SPI2 pins */
|
||||
mx31_uart1_hw_init();
|
||||
|
|
|
@ -30,6 +30,7 @@
|
|||
#include <asm/arch/mx35_pins.h>
|
||||
#include <asm/arch/iomux.h>
|
||||
#include <i2c.h>
|
||||
#include <pmic.h>
|
||||
#include <fsl_pmic.h>
|
||||
#include <mc9sdz60.h>
|
||||
#include <mc13892.h>
|
||||
|
@ -202,9 +203,10 @@ int board_init(void)
|
|||
|
||||
static inline int pmic_detect(void)
|
||||
{
|
||||
int id;
|
||||
unsigned int id;
|
||||
struct pmic *p = get_pmic();
|
||||
|
||||
id = pmic_reg_read(REG_IDENTIFICATION);
|
||||
pmic_reg_read(p, REG_IDENTIFICATION, &id);
|
||||
|
||||
id = (id >> 6) & 0x7;
|
||||
if (id == 0x7)
|
||||
|
@ -225,15 +227,19 @@ int board_late_init(void)
|
|||
{
|
||||
u8 val;
|
||||
u32 pmic_val;
|
||||
struct pmic *p;
|
||||
|
||||
pmic_init();
|
||||
if (pmic_detect()) {
|
||||
p = get_pmic();
|
||||
mxc_request_iomux(MX35_PIN_WATCHDOG_RST, MUX_CONFIG_SION |
|
||||
MUX_CONFIG_ALT1);
|
||||
|
||||
pmic_val = pmic_reg_read(REG_SETTING_0);
|
||||
pmic_reg_write(REG_SETTING_0, pmic_val | VO_1_30V | VO_1_50V);
|
||||
pmic_val = pmic_reg_read(REG_MODE_0);
|
||||
pmic_reg_write(REG_MODE_0, pmic_val | VGEN3EN);
|
||||
pmic_reg_read(p, REG_SETTING_0, &pmic_val);
|
||||
pmic_reg_write(p, REG_SETTING_0,
|
||||
pmic_val | VO_1_30V | VO_1_50V);
|
||||
pmic_reg_read(p, REG_MODE_0, &pmic_val);
|
||||
pmic_reg_write(p, REG_MODE_0, pmic_val | VGEN3EN);
|
||||
|
||||
mxc_request_iomux(MX35_PIN_COMPARE, MUX_CONFIG_GPIO);
|
||||
mxc_iomux_set_input(MUX_IN_GPIO1_IN_5, INPUT_CTL_PATH0);
|
||||
|
|
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Add table
Reference in a new issue