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85xx: Added P1020 Processor Support.
P1020 is another member of QorIQ series of processors which falls in ULE category. It is an e500 based dual core SOC. Being a scaled down version of P2020 it has following differences: - 533MHz - 800MHz core frequency. - 256Kbyte L2 cache - Ethernet controllers with classification capabilities. Also the SOC is pin compatible with P2020 Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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4 changed files with 7 additions and 2 deletions
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@ -48,8 +48,9 @@ COBJS-$(CONFIG_MPC8544) += ddr-gen2.o
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# supports ddr1/2/3
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COBJS-$(CONFIG_MPC8572) += ddr-gen3.o
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COBJS-$(CONFIG_MPC8536) += ddr-gen3.o
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COBJS-$(CONFIG_P2020) += ddr-gen3.o
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COBJS-$(CONFIG_MPC8569) += ddr-gen3.o
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COBJS-$(CONFIG_P2020) += ddr-gen3.o
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COBJS-$(CONFIG_P1020) += ddr-gen3.o
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COBJS-$(CONFIG_MPC8536) += mpc8536_serdes.o
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COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o tlb.o \
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@ -66,6 +66,8 @@ struct cpu_type cpu_type_list [] = {
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CPU_TYPE_ENTRY(8572, 8572_E, 2),
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CPU_TYPE_ENTRY(P2020, P2020, 2),
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CPU_TYPE_ENTRY(P2020, P2020_E, 2),
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CPU_TYPE_ENTRY(P1020, P1020, 2),
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CPU_TYPE_ENTRY(P1020, P1020_E, 2),
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#elif defined(CONFIG_MPC86xx)
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CPU_TYPE_ENTRY(8610, 8610, 1),
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CPU_TYPE_ENTRY(8641, 8641, 2),
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@ -39,7 +39,7 @@ DECLARE_GLOBAL_DATA_PTR;
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defined(CONFIG_MPC8641) || defined(CONFIG_MPC8610)
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#define FSL_HW_NUM_LAWS 10
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#elif defined(CONFIG_MPC8536) || defined(CONFIG_MPC8572) || \
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defined(CONFIG_P2020)
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defined(CONFIG_P2020) || defined(CONFIG_P1020)
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#define FSL_HW_NUM_LAWS 12
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#else
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#error FSL_HW_NUM_LAWS not defined for this platform
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@ -1011,6 +1011,8 @@
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#define SVR_8572_E 0x80E800
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#define SVR_P2020 0x80E200
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#define SVR_P2020_E 0x80EA00
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#define SVR_P1020 0x80E400
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#define SVR_P1020_E 0x80EC00
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#define SVR_8610 0x80A000
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#define SVR_8641 0x809000
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