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x86: ivybridge: Drop unnecessary northbridge setup

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This is done by default with PCI auto-config. Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This commit is contained in:
Simon Glass 2016-01-17 16:11:33 -07:00 • committed by Bin Meng
parent 1a9dd221c6
commit 887cba8f38
1 changed files with 0 additions and 20 deletions
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20
arch/x86/cpu/ivybridge/pci.c
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@ -19,32 +19,12 @@
static int pci_ivybridge_probe(struct udevice *bus) static int pci_ivybridge_probe(struct udevice *bus)
{ {
struct pci_controller *hose = dev_get_uclass_priv(bus);
pci_dev_t dev;
u16 reg16;
if (!(gd->flags & GD_FLG_RELOC)) if (!(gd->flags & GD_FLG_RELOC))
return 0; return 0;
post_code(0x50); post_code(0x50);
bd82x6x_init_extra(); bd82x6x_init_extra();
post_code(0x51); post_code(0x51);
reg16 = 0xff;
dev = PCH_DEV;
reg16 = x86_pci_read_config16(dev, PCI_COMMAND);
reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
x86_pci_write_config16(dev, PCI_COMMAND, reg16);
/*
* Clear non-reserved bits in status register.
*/
pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
pci_write_bar32(hose, dev, 0, 0xf0000000);
post_code(0x52);
return 0; return 0;
} }