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https://github.com/Fishwaldo/u-boot.git
synced 2025-03-19 05:31:32 +00:00
Merge branch 'master' of git://git.denx.de/u-boot-spi
This commit is contained in:
commit
88c7da6275
5 changed files with 40 additions and 13 deletions
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@ -153,7 +153,7 @@ static int mxs_nand_init(void)
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nand_chip.numchips = 1;
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nand_chip.numchips = 1;
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/* identify flash device */
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/* identify flash device */
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puts("NAND : ");
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puts(": ");
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if (mxs_flash_ident(mtd)) {
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if (mxs_flash_ident(mtd)) {
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printf("Failed to identify\n");
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printf("Failed to identify\n");
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return -1;
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return -1;
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@ -30,6 +30,7 @@
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#include <linux/errno.h>
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#include <linux/errno.h>
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#include <wait_bit.h>
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#include <wait_bit.h>
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#include <spi.h>
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#include <spi.h>
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#include <bouncebuf.h>
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#include "cadence_qspi.h"
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#include "cadence_qspi.h"
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#define CQSPI_REG_POLL_US 1 /* 1us */
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#define CQSPI_REG_POLL_US 1 /* 1us */
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@ -633,6 +634,8 @@ int cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat,
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{
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{
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unsigned int remaining = n_rx;
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unsigned int remaining = n_rx;
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unsigned int bytes_to_read = 0;
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unsigned int bytes_to_read = 0;
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struct bounce_buffer bb;
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u8 *bb_rxbuf;
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int ret;
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int ret;
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writel(n_rx, plat->regbase + CQSPI_REG_INDIRECTRDBYTES);
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writel(n_rx, plat->regbase + CQSPI_REG_INDIRECTRDBYTES);
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@ -641,6 +644,11 @@ int cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat,
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writel(CQSPI_REG_INDIRECTRD_START,
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writel(CQSPI_REG_INDIRECTRD_START,
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plat->regbase + CQSPI_REG_INDIRECTRD);
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plat->regbase + CQSPI_REG_INDIRECTRD);
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ret = bounce_buffer_start(&bb, (void *)rxbuf, n_rx, GEN_BB_WRITE);
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if (ret)
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return ret;
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bb_rxbuf = bb.bounce_buffer;
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while (remaining > 0) {
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while (remaining > 0) {
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ret = cadence_qspi_wait_for_data(plat);
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ret = cadence_qspi_wait_for_data(plat);
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if (ret < 0) {
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if (ret < 0) {
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@ -654,12 +662,13 @@ int cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat,
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bytes_to_read *= CQSPI_FIFO_WIDTH;
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bytes_to_read *= CQSPI_FIFO_WIDTH;
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bytes_to_read = bytes_to_read > remaining ?
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bytes_to_read = bytes_to_read > remaining ?
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remaining : bytes_to_read;
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remaining : bytes_to_read;
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/* Handle non-4-byte aligned access to avoid data abort. */
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readsl(plat->ahbbase, bb_rxbuf, bytes_to_read >> 2);
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if (((uintptr_t)rxbuf % 4) || (bytes_to_read % 4))
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if (bytes_to_read % 4)
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readsb(plat->ahbbase, rxbuf, bytes_to_read);
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readsb(plat->ahbbase,
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else
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bb_rxbuf + rounddown(bytes_to_read, 4),
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readsl(plat->ahbbase, rxbuf, bytes_to_read >> 2);
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bytes_to_read % 4);
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rxbuf += bytes_to_read;
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bb_rxbuf += bytes_to_read;
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remaining -= bytes_to_read;
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remaining -= bytes_to_read;
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bytes_to_read = cadence_qspi_get_rd_sram_level(plat);
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bytes_to_read = cadence_qspi_get_rd_sram_level(plat);
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}
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}
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@ -676,6 +685,7 @@ int cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat,
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/* Clear indirect completion status */
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/* Clear indirect completion status */
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writel(CQSPI_REG_INDIRECTRD_DONE,
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writel(CQSPI_REG_INDIRECTRD_DONE,
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plat->regbase + CQSPI_REG_INDIRECTRD);
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plat->regbase + CQSPI_REG_INDIRECTRD);
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bounce_buffer_stop(&bb);
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return 0;
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return 0;
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@ -683,6 +693,7 @@ failrd:
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/* Cancel the indirect read */
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/* Cancel the indirect read */
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writel(CQSPI_REG_INDIRECTRD_CANCEL,
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writel(CQSPI_REG_INDIRECTRD_CANCEL,
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plat->regbase + CQSPI_REG_INDIRECTRD);
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plat->regbase + CQSPI_REG_INDIRECTRD);
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bounce_buffer_stop(&bb);
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return ret;
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return ret;
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}
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}
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@ -724,6 +735,17 @@ int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat,
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unsigned int remaining = n_tx;
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unsigned int remaining = n_tx;
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unsigned int write_bytes;
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unsigned int write_bytes;
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int ret;
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int ret;
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struct bounce_buffer bb;
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u8 *bb_txbuf;
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/*
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* Handle non-4-byte aligned accesses via bounce buffer to
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* avoid data abort.
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*/
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ret = bounce_buffer_start(&bb, (void *)txbuf, n_tx, GEN_BB_READ);
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if (ret)
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return ret;
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bb_txbuf = bb.bounce_buffer;
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/* Configure the indirect read transfer bytes */
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/* Configure the indirect read transfer bytes */
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writel(n_tx, plat->regbase + CQSPI_REG_INDIRECTWRBYTES);
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writel(n_tx, plat->regbase + CQSPI_REG_INDIRECTWRBYTES);
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@ -734,11 +756,11 @@ int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat,
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while (remaining > 0) {
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while (remaining > 0) {
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write_bytes = remaining > page_size ? page_size : remaining;
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write_bytes = remaining > page_size ? page_size : remaining;
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/* Handle non-4-byte aligned access to avoid data abort. */
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writesl(plat->ahbbase, bb_txbuf, write_bytes >> 2);
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if (((uintptr_t)txbuf % 4) || (write_bytes % 4))
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if (write_bytes % 4)
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writesb(plat->ahbbase, txbuf, write_bytes);
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writesb(plat->ahbbase,
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else
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bb_txbuf + rounddown(write_bytes, 4),
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writesl(plat->ahbbase, txbuf, write_bytes >> 2);
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write_bytes % 4);
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ret = wait_for_bit("QSPI", plat->regbase + CQSPI_REG_SDRAMLEVEL,
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ret = wait_for_bit("QSPI", plat->regbase + CQSPI_REG_SDRAMLEVEL,
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CQSPI_REG_SDRAMLEVEL_WR_MASK <<
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CQSPI_REG_SDRAMLEVEL_WR_MASK <<
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@ -748,7 +770,7 @@ int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat,
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goto failwr;
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goto failwr;
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}
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}
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txbuf += write_bytes;
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bb_txbuf += write_bytes;
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remaining -= write_bytes;
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remaining -= write_bytes;
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}
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}
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@ -759,6 +781,7 @@ int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat,
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printf("Indirect write completion error (%i)\n", ret);
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printf("Indirect write completion error (%i)\n", ret);
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goto failwr;
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goto failwr;
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}
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}
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bounce_buffer_stop(&bb);
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/* Clear indirect completion status */
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/* Clear indirect completion status */
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writel(CQSPI_REG_INDIRECTWR_DONE,
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writel(CQSPI_REG_INDIRECTWR_DONE,
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@ -769,6 +792,7 @@ failwr:
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/* Cancel the indirect write */
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/* Cancel the indirect write */
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writel(CQSPI_REG_INDIRECTWR_CANCEL,
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writel(CQSPI_REG_INDIRECTWR_CANCEL,
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plat->regbase + CQSPI_REG_INDIRECTWR);
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plat->regbase + CQSPI_REG_INDIRECTWR);
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bounce_buffer_stop(&bb);
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return ret;
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return ret;
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}
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}
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@ -77,6 +77,7 @@
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#define CONFIG_CADENCE_QSPI
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#define CONFIG_CADENCE_QSPI
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#define CONFIG_CQSPI_REF_CLK 384000000
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#define CONFIG_CQSPI_REF_CLK 384000000
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#define CONFIG_CQSPI_DECODER 0x0
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#define CONFIG_CQSPI_DECODER 0x0
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#define CONFIG_BOUNCE_BUFFER
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#endif
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#endif
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#endif /* __CONFIG_K2G_EVM_H */
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#endif /* __CONFIG_K2G_EVM_H */
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@ -207,6 +207,7 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
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#define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz()
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#define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz()
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#endif
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#endif
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#define CONFIG_CQSPI_DECODER 0
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#define CONFIG_CQSPI_DECODER 0
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#define CONFIG_BOUNCE_BUFFER
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/*
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/*
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* Designware SPI support
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* Designware SPI support
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@ -74,6 +74,7 @@
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#ifdef CONFIG_OF_CONTROL /* QSPI is controlled via DT */
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#ifdef CONFIG_OF_CONTROL /* QSPI is controlled via DT */
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#define CONFIG_CQSPI_DECODER 0
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#define CONFIG_CQSPI_DECODER 0
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#define CONFIG_CQSPI_REF_CLK ((30/4)/2)*1000*1000
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#define CONFIG_CQSPI_REF_CLK ((30/4)/2)*1000*1000
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#define CONFIG_BOUNCE_BUFFER
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#endif
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#endif
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