mirror of
https://github.com/Fishwaldo/u-boot.git
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UniPhier SoC updates for v2019.07
- Sync DT with Linux 5.1-rc4 - Enable CONFIG_SUPPORT_EMMC_RPMB for uniphier_v8_defconfig -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJctlk9AAoJED2LAQed4NsGsBoP/0wXmetq2UKCn+4qWy3+2ItR M8hspsdpIclFTcG7D8kxeCWgMv0SH6hFbRgEo8gfnHX/kWCXnklgVc7q2rEWIk53 0Dze8Zopr0YULhx8Esuq1viS/WVz1qPVK0cnqJc4QgBbXxLWxc9xC1WUV61G0ls2 3oHGLbEJTtTE2cbEIJaRIu1pfravN4RoJtsiO+Gum1LEtoyQ/h7g/5f/equwJ0q3 QwbvASuXOyoyhypcjA97PAQZru54e8cqFd1VwRJNJMryjkOOk7Tq+z77WwtFiv7G heDy0P0b/ykxoasUMwPOOkC7/uVjeh6lsoOqiJejQan7bcYEWPsWRPflZeFVFTIS ptfir+LCNaBdUddVP7IcNaRRrho11zyvhOcHLb+df7dI7UNytux9YA0CIOlgFNmZ /lIxKlCfXKEft20XHTxIfSoPPrlmmKzk1zyvv8+rZLsMW0yBIQkLUoXKcZL+dmSG 3U8DrCNZlc4xHVEh69dntqHZ2+5TtpKV3KEBnEOHAwlqSdP6K0sU0no1hZ4H0gkU xylEihbMxwGljIAQt3VBiGb+UDlvZKvADyZDKnRt1OSO65Z3z1Vt2W4ziSrcWCTC bloy6jiOxaRkbXeEQSmjKfmOr3DpagyUuESjTKLFhYeFLl9dqMURh4C0FtP3M50d R6ivoyBE6BLnK8gOz9JL =YEOC -----END PGP SIGNATURE----- Merge tag 'uniphier-v2019.07' of git://git.denx.de/u-boot-uniphier UniPhier SoC updates for v2019.07 - Sync DT with Linux 5.1-rc4 - Enable CONFIG_SUPPORT_EMMC_RPMB for uniphier_v8_defconfig
This commit is contained in:
commit
88d5ab3d67
9 changed files with 161 additions and 19 deletions
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@ -33,7 +33,7 @@
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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compatible = "arm,cortex-a53";
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reg = <0 0x000>;
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clocks = <&sys_clk 33>;
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enable-method = "psci";
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@ -42,7 +42,7 @@
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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compatible = "arm,cortex-a53";
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reg = <0 0x001>;
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clocks = <&sys_clk 33>;
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enable-method = "psci";
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@ -43,7 +43,7 @@
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a72", "arm,armv8";
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compatible = "arm,cortex-a72";
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reg = <0 0x000>;
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clocks = <&sys_clk 32>;
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enable-method = "psci";
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@ -53,7 +53,7 @@
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a72", "arm,armv8";
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compatible = "arm,cortex-a72";
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reg = <0 0x001>;
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clocks = <&sys_clk 32>;
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enable-method = "psci";
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@ -63,7 +63,7 @@
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cpu2: cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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compatible = "arm,cortex-a53";
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reg = <0 0x100>;
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clocks = <&sys_clk 33>;
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enable-method = "psci";
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@ -73,7 +73,7 @@
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cpu3: cpu@101 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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compatible = "arm,cortex-a53";
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reg = <0 0x101>;
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clocks = <&sys_clk 33>;
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enable-method = "psci";
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@ -206,13 +206,10 @@
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cooling-maps {
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map0 {
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trip = <&cpu_alert>;
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cooling-device = <&cpu0
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THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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};
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map1 {
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trip = <&cpu_alert>;
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cooling-device = <&cpu2
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THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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};
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};
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};
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@ -891,6 +888,53 @@
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};
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};
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pcie: pcie@66000000 {
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compatible = "socionext,uniphier-pcie", "snps,dw-pcie";
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status = "disabled";
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reg-names = "dbi", "link", "config";
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reg = <0x66000000 0x1000>, <0x66010000 0x10000>,
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<0x2fff0000 0x10000>;
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#address-cells = <3>;
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#size-cells = <2>;
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clocks = <&sys_clk 24>;
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resets = <&sys_rst 24>;
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num-lanes = <1>;
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num-viewport = <1>;
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bus-range = <0x0 0xff>;
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device_type = "pci";
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ranges =
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/* downstream I/O */
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<0x81000000 0 0x00000000 0x2ffe0000 0 0x00010000>,
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/* non-prefetchable memory */
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<0x82000000 0 0x20000000 0x20000000 0 0x0ffe0000>;
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#interrupt-cells = <1>;
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interrupt-names = "dma", "msi";
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interrupts = <0 224 4>, <0 225 4>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie_intc 0>, /* INTA */
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<0 0 0 2 &pcie_intc 1>, /* INTB */
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<0 0 0 3 &pcie_intc 2>, /* INTC */
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<0 0 0 4 &pcie_intc 3>; /* INTD */
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phy-names = "pcie-phy";
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phys = <&pcie_phy>;
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pcie_intc: legacy-interrupt-controller {
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupt-parent = <&gic>;
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interrupts = <0 226 4>;
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};
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};
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pcie_phy: phy@66038000 {
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compatible = "socionext,uniphier-ld20-pcie-phy";
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reg = <0x66038000 0x4000>;
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#phy-cells = <0>;
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clocks = <&sys_clk 24>;
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resets = <&sys_rst 24>;
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socionext,syscon = <&soc_glue>;
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};
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nand: nand@68000000 {
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compatible = "socionext,uniphier-denali-nand-v5b";
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status = "disabled";
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@ -235,6 +235,16 @@
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};
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};
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dmac: dma-controller@5a000000 {
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compatible = "socionext,uniphier-mio-dmac";
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reg = <0x5a000000 0x1000>;
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interrupts = <0 68 4>, <0 68 4>, <0 69 4>, <0 70 4>,
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<0 71 4>, <0 72 4>, <0 73 4>;
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clocks = <&mio_clk 7>;
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resets = <&mio_rst 7>;
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#dma-cells = <1>;
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};
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sd: sdhc@5a400000 {
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compatible = "socionext,uniphier-sd-v2.91";
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status = "disabled";
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@ -246,6 +256,8 @@
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clocks = <&mio_clk 0>;
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reset-names = "host", "bridge";
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resets = <&mio_rst 0>, <&mio_rst 3>;
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dma-names = "rx-tx";
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dmas = <&dmac 4>;
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bus-width = <4>;
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cap-sd-highspeed;
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sd-uhs-sdr12;
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@ -263,6 +275,8 @@
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clocks = <&mio_clk 1>;
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reset-names = "host", "bridge", "hw";
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resets = <&mio_rst 1>, <&mio_rst 4>, <&mio_rst 6>;
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dma-names = "rx-tx";
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dmas = <&dmac 6>;
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bus-width = <8>;
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cap-mmc-highspeed;
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cap-mmc-hw-reset;
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@ -269,6 +269,16 @@
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};
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};
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dmac: dma-controller@5a000000 {
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compatible = "socionext,uniphier-mio-dmac";
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reg = <0x5a000000 0x1000>;
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interrupts = <0 68 4>, <0 68 4>, <0 69 4>, <0 70 4>,
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<0 71 4>, <0 72 4>, <0 73 4>, <0 74 4>;
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clocks = <&mio_clk 7>;
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resets = <&mio_rst 7>;
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#dma-cells = <1>;
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};
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sd: sdhc@5a400000 {
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compatible = "socionext,uniphier-sd-v2.91";
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status = "disabled";
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@ -280,6 +290,8 @@
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clocks = <&mio_clk 0>;
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reset-names = "host", "bridge";
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resets = <&mio_rst 0>, <&mio_rst 3>;
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dma-names = "rx-tx";
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dmas = <&dmac 4>;
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bus-width = <4>;
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cap-sd-highspeed;
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sd-uhs-sdr12;
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@ -297,6 +309,8 @@
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clocks = <&mio_clk 1>;
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reset-names = "host", "bridge", "hw";
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resets = <&mio_rst 1>, <&mio_rst 4>, <&mio_rst 6>;
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dma-names = "rx-tx";
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dmas = <&dmac 5>;
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bus-width = <8>;
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cap-mmc-highspeed;
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cap-mmc-hw-reset;
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@ -313,6 +327,8 @@
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clocks = <&mio_clk 2>;
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reset-names = "host", "bridge";
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resets = <&mio_rst 2>, <&mio_rst 5>;
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dma-names = "rx-tx";
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dmas = <&dmac 6>;
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bus-width = <4>;
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cap-sd-highspeed;
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};
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@ -141,8 +141,10 @@
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cooling-maps {
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map {
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trip = <&cpu_alert>;
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cooling-device = <&cpu0
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THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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};
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};
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};
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@ -109,6 +109,10 @@
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status = "okay";
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};
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&pcie {
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status = "okay";
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};
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&nand {
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status = "okay";
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};
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@ -39,7 +39,7 @@
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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compatible = "arm,cortex-a53";
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reg = <0 0x000>;
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clocks = <&sys_clk 33>;
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enable-method = "psci";
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@ -48,7 +48,7 @@
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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compatible = "arm,cortex-a53";
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reg = <0 0x001>;
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clocks = <&sys_clk 33>;
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enable-method = "psci";
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@ -57,7 +57,7 @@
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cpu2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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compatible = "arm,cortex-a53";
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reg = <0 0x002>;
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clocks = <&sys_clk 33>;
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enable-method = "psci";
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@ -66,7 +66,7 @@
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cpu3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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compatible = "arm,cortex-a53";
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reg = <0 0x003>;
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clocks = <&sys_clk 33>;
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enable-method = "psci";
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@ -765,6 +765,53 @@
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};
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};
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pcie: pcie@66000000 {
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compatible = "socionext,uniphier-pcie", "snps,dw-pcie";
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status = "disabled";
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reg-names = "dbi", "link", "config";
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reg = <0x66000000 0x1000>, <0x66010000 0x10000>,
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<0x2fff0000 0x10000>;
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#address-cells = <3>;
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#size-cells = <2>;
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clocks = <&sys_clk 24>;
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resets = <&sys_rst 24>;
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num-lanes = <1>;
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num-viewport = <1>;
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bus-range = <0x0 0xff>;
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device_type = "pci";
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ranges =
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/* downstream I/O */
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<0x81000000 0 0x00000000 0x2ffe0000 0 0x00010000>,
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/* non-prefetchable memory */
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<0x82000000 0 0x20000000 0x20000000 0 0x0ffe0000>;
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#interrupt-cells = <1>;
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interrupt-names = "dma", "msi";
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interrupts = <0 224 4>, <0 225 4>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie_intc 0>, /* INTA */
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<0 0 0 2 &pcie_intc 1>, /* INTB */
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<0 0 0 3 &pcie_intc 2>, /* INTC */
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<0 0 0 4 &pcie_intc 3>; /* INTD */
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phy-names = "pcie-phy";
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phys = <&pcie_phy>;
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pcie_intc: legacy-interrupt-controller {
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupt-parent = <&gic>;
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interrupts = <0 226 4>;
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};
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};
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pcie_phy: phy@66038000 {
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compatible = "socionext,uniphier-pxs3-pcie-phy";
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reg = <0x66038000 0x4000>;
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#phy-cells = <0>;
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clocks = <&sys_clk 24>;
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resets = <&sys_rst 24>;
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socionext,syscon = <&soc_glue>;
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};
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nand: nand@68000000 {
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compatible = "socionext,uniphier-denali-nand-v5b";
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status = "disabled";
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@ -239,6 +239,16 @@
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};
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};
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dmac: dma-controller@5a000000 {
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compatible = "socionext,uniphier-mio-dmac";
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reg = <0x5a000000 0x1000>;
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interrupts = <0 68 4>, <0 68 4>, <0 69 4>, <0 70 4>,
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<0 71 4>, <0 72 4>, <0 73 4>;
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clocks = <&mio_clk 7>;
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resets = <&mio_rst 7>;
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#dma-cells = <1>;
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};
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sd: sdhc@5a400000 {
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compatible = "socionext,uniphier-sd-v2.91";
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status = "disabled";
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@ -250,6 +260,8 @@
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clocks = <&mio_clk 0>;
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reset-names = "host", "bridge";
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resets = <&mio_rst 0>, <&mio_rst 3>;
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dma-names = "rx-tx";
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dmas = <&dmac 4>;
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bus-width = <4>;
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cap-sd-highspeed;
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sd-uhs-sdr12;
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@ -267,6 +279,8 @@
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clocks = <&mio_clk 1>;
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reset-names = "host", "bridge", "hw";
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resets = <&mio_rst 1>, <&mio_rst 4>, <&mio_rst 6>;
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dma-names = "rx-tx";
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dmas = <&dmac 6>;
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bus-width = <8>;
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cap-mmc-highspeed;
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cap-mmc-hw-reset;
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@ -33,6 +33,7 @@ CONFIG_GPIO_UNIPHIER=y
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CONFIG_MISC=y
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CONFIG_I2C_EEPROM=y
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CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10
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CONFIG_SUPPORT_EMMC_RPMB=y
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CONFIG_MMC_HS200_SUPPORT=y
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CONFIG_MMC_UNIPHIER=y
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CONFIG_MMC_SDHCI=y
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