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arm/davinci: fix DDR2/mDDR memory controller initialization for Omap L138

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follow section 15.2.13.1 (Initializing Following Device Power Up or Reset) of
OMAP-L138 DSP+ARM Processor Technical Reference Manual

Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@gmail.com>
Acked-by: Christian Riesch <christian.riesch@omicron.at>
Tested-by: Christian Riesch <christian.riesch@omicron.at>
This commit is contained in:
Mikhail Kshevetskiy 2012-07-09 08:52:41 +00:00 • committed by Albert ARIBAUD
parent c50afc1dab
commit 89473d233f
2 changed files with 20 additions and 7 deletions
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26
arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c
View file

@ -190,13 +190,21 @@ int da850_ddr_setup(void)
setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_LOCK); setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_LOCK);
setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_POWERDWN); setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_POWERDWN);
setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_IOPWRDWN);
} }
setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_IOPWRDWN);
writel(CONFIG_SYS_DA850_DDR2_DDRPHYCR, &dv_ddr2_regs_ctrl->ddrphycr); writel(CONFIG_SYS_DA850_DDR2_DDRPHYCR, &dv_ddr2_regs_ctrl->ddrphycr);
clrbits_le32(&davinci_syscfg1_regs->ddr_slew,
(1 << DDR_SLEW_CMOSEN_BIT)); if (CONFIG_SYS_DA850_DDR2_SDBCR & (1 << DV_DDR_SDCR_DDR2EN_SHIFT)) {
/* DDR2 */
clrbits_le32(&davinci_syscfg1_regs->ddr_slew,
(1 << DDR_SLEW_DDR_PDENA_BIT) |
(1 << DDR_SLEW_CMOSEN_BIT));
} else {
/* MOBILE DDR */
setbits_le32(&davinci_syscfg1_regs->ddr_slew,
(1 << DDR_SLEW_DDR_PDENA_BIT) |
(1 << DDR_SLEW_CMOSEN_BIT));
}
/* /*
* SDRAM Configuration Register (SDCR): * SDRAM Configuration Register (SDCR):
@ -216,7 +224,11 @@ int da850_ddr_setup(void)
writel(tmp, &dv_ddr2_regs_ctrl->sdbcr); writel(tmp, &dv_ddr2_regs_ctrl->sdbcr);
/* write memory configuration and timing */ /* write memory configuration and timing */
writel(CONFIG_SYS_DA850_DDR2_SDBCR2, &dv_ddr2_regs_ctrl->sdbcr2); if (!(CONFIG_SYS_DA850_DDR2_SDBCR & (1 << DV_DDR_SDCR_DDR2EN_SHIFT))) {
/* MOBILE DDR only*/
writel(CONFIG_SYS_DA850_DDR2_SDBCR2,
&dv_ddr2_regs_ctrl->sdbcr2);
}
writel(CONFIG_SYS_DA850_DDR2_SDTIMR, &dv_ddr2_regs_ctrl->sdtimr); writel(CONFIG_SYS_DA850_DDR2_SDTIMR, &dv_ddr2_regs_ctrl->sdtimr);
writel(CONFIG_SYS_DA850_DDR2_SDTIMR2, &dv_ddr2_regs_ctrl->sdtimr2); writel(CONFIG_SYS_DA850_DDR2_SDTIMR2, &dv_ddr2_regs_ctrl->sdtimr2);
@ -240,7 +252,7 @@ int da850_ddr_setup(void)
/* disable self refresh */ /* disable self refresh */
clrbits_le32(&dv_ddr2_regs_ctrl->sdrcr, clrbits_le32(&dv_ddr2_regs_ctrl->sdrcr,
DV_DDR_SDRCR_LPMODEN | DV_DDR_SDRCR_LPMODEN); DV_DDR_SDRCR_LPMODEN | DV_DDR_SDRCR_MCLKSTOPEN);
writel(CONFIG_SYS_DA850_DDR2_PBBPR, &dv_ddr2_regs_ctrl->pbbpr); writel(CONFIG_SYS_DA850_DDR2_PBBPR, &dv_ddr2_regs_ctrl->pbbpr);
return 0; return 0;

1
arch/arm/include/asm/arch-davinci/hardware.h
View file

@ -506,6 +506,7 @@ struct davinci_syscfg1_regs {
((struct davinci_syscfg1_regs *)DAVINCI_SYSCFG1_BASE) ((struct davinci_syscfg1_regs *)DAVINCI_SYSCFG1_BASE)
#define DDR_SLEW_CMOSEN_BIT 4 #define DDR_SLEW_CMOSEN_BIT 4
#define DDR_SLEW_DDR_PDENA_BIT 5
#define VTP_POWERDWN (1 << 6) #define VTP_POWERDWN (1 << 6)
#define VTP_LOCK (1 << 7) #define VTP_LOCK (1 << 7)