Xilinx changes for v2018.05

- Fix mkimage recognition
 - Update all my fragments
 
 ZynqMP:
 - Use clk driver
 - Support loading elfs in el1
 - Various DTS and defconfig changes
 - Enable newer pmufw versions
 - Support more clocks
 - Remove ep108
 - Secure image support
 - Fix memtest setup
 
 Zynq:
 - Enabling watchdog driver
 - Support more clocks
 - defconfig changes
 
 fpga:
 - Simplify error path
 
 net:
 - GMII case update
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 =7++x
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Merge tag 'xilinx-for-v2018.05' of git://git.denx.de/u-boot-microblaze

Xilinx changes for v2018.05

- Fix mkimage recognition
- Update all my fragments

ZynqMP:
- Use clk driver
- Support loading elfs in el1
- Various DTS and defconfig changes
- Enable newer pmufw versions
- Support more clocks
- Remove ep108
- Secure image support
- Fix memtest setup

Zynq:
- Enabling watchdog driver
- Support more clocks
- defconfig changes

fpga:
- Simplify error path

net:
- GMII case update

MAINTAINERS

@@ -245,14 +245,50 @@ N:	uniphier
 ARM ZYNQ
 M:	Michal Simek <monstr@monstr.eu>
 S:	Maintained
-F:	arch/arm/cpu/armv7/zynq/
+T:	git git://git.denx.de/u-boot-microblaze.git
-F:	arch/arm/include/asm/arch-zynq/
+F:	arch/arm/mach-zynq/
+F:	drivers/clk/clk_zynq.c
+F:	drivers/fpga/zynqpl.c
+F:	drivers/gpio/zynq_gpio.c
+F:	drivers/i2c/i2c-cdns.c
+F:	drivers/i2c/muxes/pca954x.c
+F:	drivers/i2c/zynq_i2c.c
+F:	drivers/mmc/zynq_sdhci.c
+F:	drivers/mtd/nand/zynq_nand.c
+F:	drivers/net/phy/xilinx_phy.c
+F:	drivers/net/zynq_gem.c
+F:	drivers/serial/serial_zynq.c
+F:	drivers/spi/zynq_qspi.c
+F:	drivers/spi/zynq_spi.c
+F:	drivers/usb/host/ehci-zynq.c
+F:	drivers/watchdog/cdns_wdt.c
+F:	include/zynqmp.h
+F:	tools/zynqimage.c
+N:	zynq
 
 ARM ZYNQMP
 M:	Michal Simek <michal.simek@xilinx.com>
 S:	Maintained
-F:	arch/arm/cpu/armv8/zynqmp/
+T:	git git://git.denx.de/u-boot-microblaze.git
-F:	arch/arm/include/asm/arch-zynqmp/
+F:	arch/arm/mach-zynq/
+F:	drivers/clk/clk_zynq.c
+F:	drivers/fpga/zynqpl.c
+F:	drivers/gpio/zynq_gpio.c
+F:	drivers/i2c/i2c-cdns.c
+F:	drivers/i2c/muxes/pca954x.c
+F:	drivers/i2c/zynq_i2c.c
+F:	drivers/mmc/zynq_sdhci.c
+F:	drivers/mtd/nand/zynq_nand.c
+F:	drivers/net/phy/xilinx_phy.c
+F:	drivers/net/zynq_gem.c
+F:	drivers/serial/serial_zynq.c
+F:	drivers/spi/zynq_qspi.c
+F:	drivers/spi/zynq_spi.c
+F:	drivers/usb/host/ehci-zynq.c
+F:	drivers/watchdog/cdns_wdt.c
+F:	include/zynqmp.h
+F:	tools/zynqimage.c
+N:	zynqmp
 
 BUILDMAN
 M:	Simon Glass <sjg@chromium.org>
@@ -343,6 +379,14 @@ M:	Michal Simek <monstr@monstr.eu>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-microblaze.git
 F:	arch/microblaze/
+F:	cmd/mfsl.c
+F:	drivers/gpio/xilinx_gpio.c
+F:	drivers/net/xilinx_axi_emac.c
+F:	drivers/net/xilinx_emaclite.c
+F:	drivers/serial/serial_xuartlite.c
+F:	drivers/spi/xilinx_spi.c
+F:	drivers/watchdog/xilinx_tb_wdt.c
+N:	xilinx
 
 MIPS
 M:	Daniel Schwierzeck <daniel.schwierzeck@gmail.com>

arch/arm/Kconfig

@@ -762,6 +762,7 @@ config ARCH_ZYNQ
 	select SUPPORT_SPL
 	select OF_CONTROL
 	select SPL_BOARD_INIT if SPL
+	select BOARD_EARLY_INIT_F if WDT
 	select SPL_OF_CONTROL if SPL
 	select DM
 	select DM_ETH if NET
@@ -1359,6 +1360,7 @@ source "board/toradex/colibri_pxa270/Kconfig"
 source "board/vscom/baltos/Kconfig"
 source "board/woodburn/Kconfig"
 source "board/work-microwave/work_92105/Kconfig"
+source "board/xilinx/zynqmp/Kconfig"
 source "board/zipitz2/Kconfig"
 
 source "arch/arm/Kconfig.debug"

arch/arm/cpu/armv8/zynqmp/cpu.c

@@ -185,7 +185,7 @@ void zynqmp_pmufw_version(void)
 	       pm_api_version >> ZYNQMP_PM_VERSION_MAJOR_SHIFT,
 	       pm_api_version & ZYNQMP_PM_VERSION_MINOR_MASK);
 
-	if (pm_api_version != ZYNQMP_PM_VERSION)
+	if (pm_api_version < ZYNQMP_PM_VERSION)
 		panic("PMUFW version error. Expected: v%d.%d\n",
 		      ZYNQMP_PM_VERSION_MAJOR, ZYNQMP_PM_VERSION_MINOR);
 }

arch/arm/dts/Makefile

@@ -146,7 +146,6 @@ dtb-$(CONFIG_ARCH_ZYNQ) += \
 	zynq-zturn-myir.dtb \
 	zynq-zybo.dtb
 dtb-$(CONFIG_ARCH_ZYNQMP) += \
-	zynqmp-ep108.dtb			\
 	zynqmp-mini-emmc.dtb			\
 	zynqmp-mini-nand.dtb			\
 	zynqmp-zcu102-revA.dtb			\

arch/arm/dts/zynq-zc706.dts

@@ -333,3 +333,7 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_usb0_default>;
 };
+
+&watchdog0 {
+	reset-on-timeout;
+};

arch/arm/dts/zynqmp-clk-ccf.dtsi

@@ -0,0 +1,290 @@
+/*
+ * Clock specification for Xilinx ZynqMP
+ *
+ * (C) Copyright 2017, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+/ {
+	fclk0: fclk0 {
+		status = "disabled";
+		compatible = "xlnx,fclk";
+		clocks = <&clkc 71>;
+	};
+
+	fclk1: fclk1 {
+		status = "disabled";
+		compatible = "xlnx,fclk";
+		clocks = <&clkc 72>;
+	};
+
+	fclk2: fclk2 {
+		status = "disabled";
+		compatible = "xlnx,fclk";
+		clocks = <&clkc 73>;
+	};
+
+	fclk3: fclk3 {
+		status = "disabled";
+		compatible = "xlnx,fclk";
+		clocks = <&clkc 74>;
+	};
+
+	pss_ref_clk: pss_ref_clk {
+		u-boot,dm-pre-reloc;
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <33333333>;
+	};
+
+	video_clk: video_clk {
+		u-boot,dm-pre-reloc;
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <27000000>;
+	};
+
+	pss_alt_ref_clk: pss_alt_ref_clk {
+		u-boot,dm-pre-reloc;
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <0>;
+	};
+
+	gt_crx_ref_clk: gt_crx_ref_clk {
+		u-boot,dm-pre-reloc;
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <108000000>;
+	};
+
+	aux_ref_clk: aux_ref_clk {
+		u-boot,dm-pre-reloc;
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <27000000>;
+	};
+
+	clkc: clkc {
+		u-boot,dm-pre-reloc;
+		#clock-cells = <1>;
+		compatible = "xlnx,zynqmp-clkc";
+		clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>, <&aux_ref_clk>, <&gt_crx_ref_clk>;
+		clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk", "aux_ref_clk", "gt_crx_ref_clk";
+		clock-output-names = "iopll", "rpll", "apll", "dpll",
+				"vpll", "iopll_to_fpd", "rpll_to_fpd",
+				"apll_to_lpd", "dpll_to_lpd", "vpll_to_lpd",
+				"acpu", "acpu_half", "dbf_fpd", "dbf_lpd",
+				"dbg_trace", "dbg_tstmp", "dp_video_ref",
+				"dp_audio_ref", "dp_stc_ref", "gdma_ref",
+				"dpdma_ref", "ddr_ref", "sata_ref", "pcie_ref",
+				"gpu_ref", "gpu_pp0_ref", "gpu_pp1_ref",
+				"topsw_main", "topsw_lsbus", "gtgref0_ref",
+				"lpd_switch", "lpd_lsbus", "usb0_bus_ref",
+				"usb1_bus_ref", "usb3_dual_ref", "usb0",
+				"usb1", "cpu_r5", "cpu_r5_core", "csu_spb",
+				"csu_pll", "pcap", "iou_switch", "gem_tsu_ref",
+				"gem_tsu", "gem0_ref", "gem1_ref", "gem2_ref",
+				"gem3_ref", "gem0_tx", "gem1_tx", "gem2_tx",
+				"gem3_tx", "qspi_ref", "sdio0_ref", "sdio1_ref",
+				"uart0_ref", "uart1_ref", "spi0_ref",
+				"spi1_ref", "nand_ref", "i2c0_ref", "i2c1_ref",
+				"can0_ref", "can1_ref", "can0", "can1",
+				"dll_ref", "adma_ref", "timestamp_ref",
+				"ams_ref", "pl0", "pl1", "pl2", "pl3", "wdt";
+	};
+
+	dp_aclk: dp_aclk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <100000000>;
+		clock-accuracy = <100>;
+	};
+};
+
+&can0 {
+	clocks = <&clkc 63>, <&clkc 31>;
+};
+
+&can1 {
+	clocks = <&clkc 64>, <&clkc 31>;
+};
+
+&cpu0 {
+	clocks = <&clkc 10>;
+};
+
+&fpd_dma_chan1 {
+	clocks = <&clkc 19>, <&clkc 31>;
+};
+
+&fpd_dma_chan2 {
+	clocks = <&clkc 19>, <&clkc 31>;
+};
+
+&fpd_dma_chan3 {
+	clocks = <&clkc 19>, <&clkc 31>;
+};
+
+&fpd_dma_chan4 {
+	clocks = <&clkc 19>, <&clkc 31>;
+};
+
+&fpd_dma_chan5 {
+	clocks = <&clkc 19>, <&clkc 31>;
+};
+
+&fpd_dma_chan6 {
+	clocks = <&clkc 19>, <&clkc 31>;
+};
+
+&fpd_dma_chan7 {
+	clocks = <&clkc 19>, <&clkc 31>;
+};
+
+&fpd_dma_chan8 {
+	clocks = <&clkc 19>, <&clkc 31>;
+};
+
+&gpu {
+	clocks = <&clkc 24>, <&clkc 25>, <&clkc 26>;
+};
+
+&lpd_dma_chan1 {
+	clocks = <&clkc 68>, <&clkc 31>;
+};
+
+&lpd_dma_chan2 {
+	clocks = <&clkc 68>, <&clkc 31>;
+};
+
+&lpd_dma_chan3 {
+	clocks = <&clkc 68>, <&clkc 31>;
+};
+
+&lpd_dma_chan4 {
+	clocks = <&clkc 68>, <&clkc 31>;
+};
+
+&lpd_dma_chan5 {
+	clocks = <&clkc 68>, <&clkc 31>;
+};
+
+&lpd_dma_chan6 {
+	clocks = <&clkc 68>, <&clkc 31>;
+};
+
+&lpd_dma_chan7 {
+	clocks = <&clkc 68>, <&clkc 31>;
+};
+
+&lpd_dma_chan8 {
+	clocks = <&clkc 68>, <&clkc 31>;
+};
+
+&nand0 {
+	clocks = <&clkc 60>, <&clkc 31>;
+};
+
+&gem0 {
+	clocks = <&clkc 31>, <&clkc 49>, <&clkc 45>, <&clkc 49>, <&clkc 44>;
+	clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
+};
+
+&gem1 {
+	clocks = <&clkc 31>, <&clkc 50>, <&clkc 46>, <&clkc 50>, <&clkc 44>;
+	clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
+};
+
+&gem2 {
+	clocks = <&clkc 31>, <&clkc 51>, <&clkc 47>, <&clkc 51>, <&clkc 44>;
+	clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
+};
+
+&gem3 {
+	clocks = <&clkc 31>, <&clkc 52>, <&clkc 48>, <&clkc 52>, <&clkc 44>;
+	clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
+};
+
+&gpio {
+	clocks = <&clkc 31>;
+};
+
+&i2c0 {
+	clocks = <&clkc 61>;
+};
+
+&i2c1 {
+	clocks = <&clkc 62>;
+};
+
+&pcie {
+	clocks = <&clkc 23>;
+};
+
+&qspi {
+	clocks = <&clkc 53>, <&clkc 31>;
+};
+
+&sata {
+	clocks = <&clkc 22>;
+};
+
+&sdhci0 {
+	clocks = <&clkc 54>, <&clkc 31>;
+};
+
+&sdhci1 {
+	clocks = <&clkc 55>, <&clkc 31>;
+};
+
+&spi0 {
+	clocks = <&clkc 58>, <&clkc 31>;
+};
+
+&spi1 {
+	clocks = <&clkc 59>, <&clkc 31>;
+};
+
+&uart0 {
+	clocks = <&clkc 56>,  <&clkc 31>;
+};
+
+&uart1 {
+	clocks = <&clkc 57>,  <&clkc 31>;
+};
+
+&usb0 {
+	clocks = <&clkc 32>,  <&clkc 34>;
+};
+
+&usb1 {
+	clocks = <&clkc 33>,  <&clkc 34>;
+};
+
+&watchdog0 {
+	clocks = <&clkc 75>;
+};
+
+&xilinx_ams {
+	clocks = <&clkc 70>;
+};
+
+&xilinx_drm {
+	clocks = <&clkc 16>;
+};
+
+&xlnx_dp {
+	clocks = <&dp_aclk>, <&clkc 17>;
+};
+
+&xlnx_dpdma {
+	clocks = <&clkc 20>;
+};
+
+&xlnx_dp_snd_codec0 {
+	clocks = <&clkc 17>;
+};

arch/arm/dts/zynqmp-ep108-clk.dtsi

@@ -1,172 +0,0 @@
-/*
- * clock specification for Xilinx ZynqMP ep108 development board
- *
- * (C) Copyright 2015, Xilinx, Inc.
- *
- * Michal Simek <michal.simek@xilinx.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/ {
-	misc_clk: misc_clk {
-		compatible = "fixed-clock";
-		#clock-cells = <0>;
-		clock-frequency = <25000000>;
-		u-boot,dm-pre-reloc;
-	};
-
-	i2c_clk: i2c_clk {
-		compatible = "fixed-clock";
-		#clock-cells = <0x0>;
-		clock-frequency = <111111111>;
-	};
-
-	sata_clk: sata_clk {
-		compatible = "fixed-clock";
-		#clock-cells = <0>;
-		clock-frequency = <75000000>;
-	};
-
-	dp_aclk: clock0 {
-		compatible = "fixed-clock";
-		#clock-cells = <0>;
-		clock-frequency = <50000000>;
-		clock-accuracy = <100>;
-	};
-
-	clk100: clk100 {
-		compatible = "fixed-clock";
-		#clock-cells = <0>;
-		clock-frequency = <100000000>;
-	};
-
-	clk600: clk600 {
-		compatible = "fixed-clock";
-		#clock-cells = <0>;
-		clock-frequency = <600000000>;
-	};
-
-	dp_aud_clk: clock1 {
-		compatible = "fixed-clock";
-		#clock-cells = <0>;
-		clock-frequency = <22579200>;
-		clock-accuracy = <100>;
-	};
-};
-
-&can0 {
-	clocks = <&misc_clk &misc_clk>;
-};
-
-&can1 {
-	clocks = <&misc_clk &misc_clk>;
-};
-
-&fpd_dma_chan1 {
-	clocks = <&clk600>, <&clk100>;
-};
-
-&fpd_dma_chan2 {
-	clocks = <&clk600>, <&clk100>;
-};
-
-&fpd_dma_chan3 {
-	clocks = <&clk600>, <&clk100>;
-};
-
-&fpd_dma_chan4 {
-	clocks = <&clk600>, <&clk100>;
-};
-
-&fpd_dma_chan5 {
-	clocks = <&clk600>, <&clk100>;
-};
-
-&fpd_dma_chan6 {
-	clocks = <&clk600>, <&clk100>;
-};
-
-&fpd_dma_chan7 {
-	clocks = <&clk600>, <&clk100>;
-};
-
-&fpd_dma_chan8 {
-	clocks = <&clk600>, <&clk100>;
-};
-
-&gem0 {
-	clocks = <&misc_clk>, <&misc_clk>, <&misc_clk>;
-};
-
-&gpio {
-	clocks = <&misc_clk>;
-};
-
-&i2c0 {
-	clocks = <&i2c_clk>;
-};
-
-&i2c1 {
-	clocks = <&i2c_clk>;
-};
-
-&nand0 {
-	clocks = <&misc_clk &misc_clk>;
-};
-
-&qspi {
-	clocks = <&misc_clk &misc_clk>;
-};
-
-&sata {
-	clocks = <&sata_clk>;
-};
-
-&sdhci0 {
-	clocks = <&misc_clk>, <&misc_clk>;
-};
-
-&sdhci1 {
-	clocks = <&misc_clk>, <&misc_clk>;
-};
-
-&spi0 {
-	clocks = <&misc_clk &misc_clk>;
-};
-
-&spi1 {
-	clocks = <&misc_clk &misc_clk>;
-};
-
-&uart0 {
-	clocks = <&misc_clk &misc_clk>;
-};
-
-&usb0 {
-	clocks = <&misc_clk>, <&misc_clk>;
-};
-
-&usb1 {
-	clocks = <&misc_clk>, <&misc_clk>;
-};
-
-&watchdog0 {
-	clocks= <&misc_clk>;
-};
-
-&xilinx_drm {
-	clocks = <&misc_clk>;
-};
-
-&xlnx_dp {
-	clocks = <&dp_aclk>, <&dp_aud_clk>;
-};
-
-&xlnx_dp_snd_codec0 {
-	clocks = <&dp_aud_clk>;
-};
-
-&xlnx_dpdma {
-	clocks = <&misc_clk>;
-};

arch/arm/dts/zynqmp-ep108.dts

@@ -1,235 +0,0 @@
-/*
- * dts file for Xilinx ZynqMP ep108 development board
- *
- * (C) Copyright 2014 - 2015, Xilinx, Inc.
- *
- * Michal Simek <michal.simek@xilinx.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/dts-v1/;
-
-#include "zynqmp.dtsi"
-#include "zynqmp-ep108-clk.dtsi"
-
-/ {
-	model = "ZynqMP EP108";
-
-	aliases {
-		ethernet0 = &gem0;
-		mmc0 = &sdhci0;
-		mmc1 = &sdhci1;
-		serial0 = &uart0;
-		spi0 = &qspi;
-		spi1 = &spi0;
-		spi2 = &spi1;
-		usb0 = &usb0;
-		usb1 = &usb1;
-	};
-
-	chosen {
-		bootargs = "earlycon";
-		stdout-path = "serial0:115200n8";
-	};
-
-	memory@0 {
-		device_type = "memory";
-		reg = <0x0 0x0 0x0 0x40000000>;
-	};
-};
-
-&can0 {
-	status = "okay";
-};
-
-&can1 {
-	status = "okay";
-};
-
-&gem0 {
-	status = "okay";
-	phy-handle = <&phy0>;
-	phy-mode = "rgmii-id";
-	phy0: phy@0 {
-		reg = <0>;
-		max-speed = <100>;
-	};
-};
-
-&gpio {
-	status = "okay";
-};
-
-&i2c0 {
-	status = "okay";
-	clock-frequency = <400000>;
-	eeprom@54 {
-		compatible = "atmel,24c64";
-		reg = <0x54>;
-	};
-};
-
-&i2c1 {
-	status = "okay";
-	clock-frequency = <400000>;
-	eeprom@55 {
-		compatible = "atmel,24c64";
-		reg = <0x55>;
-	};
-};
-
-&nand0 {
-	status = "okay";
-	arasan,has-mdma;
-	num-cs = <1>;
-
-	partition@0 {	/* for testing purpose */
-		label = "nand-fsbl-uboot";
-		reg = <0x0 0x0 0x400000>;
-	};
-	partition@1 {	/* for testing purpose */
-		label = "nand-linux";
-		reg = <0x0 0x400000 0x1400000>;
-	};
-	partition@2 {	/* for testing purpose */
-		label = "nand-device-tree";
-		reg = <0x0 0x1800000 0x400000>;
-	};
-	partition@3 {	/* for testing purpose */
-		label = "nand-rootfs";
-		reg = <0x0 0x1C00000 0x1400000>;
-	};
-	partition@4 {	/* for testing purpose */
-		label = "nand-bitstream";
-		reg = <0x0 0x3000000 0x400000>;
-	};
-	partition@5 {	/* for testing purpose */
-		label = "nand-misc";
-		reg = <0x0 0x3400000 0xFCC00000>;
-	};
-};
-
-&qspi {
-	status = "okay";
-	flash@0 {
-		compatible = "m25p80";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		reg = <0x0>;
-		spi-tx-bus-width = <1>;
-		spi-rx-bus-width = <4>;
-		spi-max-frequency = <10000000>;
-		partition@qspi-fsbl-uboot { /* for testing purpose */
-			label = "qspi-fsbl-uboot";
-			reg = <0x0 0x100000>;
-		};
-		partition@qspi-linux { /* for testing purpose */
-			label = "qspi-linux";
-			reg = <0x100000 0x500000>;
-		};
-		partition@qspi-device-tree { /* for testing purpose */
-			label = "qspi-device-tree";
-			reg = <0x600000 0x20000>;
-		};
-		partition@qspi-rootfs { /* for testing purpose */
-			label = "qspi-rootfs";
-			reg = <0x620000 0x5E0000>;
-		};
-	};
-};
-
-&sata {
-	status = "okay";
-	ceva,broken-gen2;
-	/* SATA Phy OOB timing settings */
-	ceva,p0-cominit-params = /bits/ 8 <0x0F 0x25 0x18 0x29>;
-	ceva,p0-comwake-params = /bits/ 8 <0x04 0x0B 0x08 0x0F>;
-	ceva,p0-burst-params = /bits/ 8 <0x0A 0x08 0x4A 0x06>;
-	ceva,p0-retry-params = /bits/ 16 <0x0216 0x7F06>;
-	ceva,p1-cominit-params = /bits/ 8 <0x0F 0x25 0x18 0x29>;
-	ceva,p1-comwake-params = /bits/ 8 <0x04 0x0B 0x08 0x0F>;
-	ceva,p1-burst-params = /bits/ 8 <0x0A 0x08 0x4A 0x06>;
-	ceva,p1-retry-params = /bits/ 16 <0x0216 0x7F06>;
-};
-
-&sdhci0 {
-	status = "okay";
-	bus-width = <8>;
-	xlnx,mio_bank = <2>;
-};
-
-&sdhci1 {
-	status = "okay";
-	xlnx,mio_bank = <1>;
-};
-
-&spi0 {
-	status = "okay";
-	num-cs = <1>;
-	spi0_flash0: spi0_flash0@0 {
-		compatible = "m25p80";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		spi-max-frequency = <50000000>;
-		reg = <0>;
-
-		spi0_flash0@0 {
-			label = "spi0_flash0";
-			reg = <0x0 0x100000>;
-		};
-	};
-};
-
-&spi1 {
-	status = "okay";
-	num-cs = <1>;
-	spi1_flash0: spi1_flash0@0 {
-		compatible = "m25p80";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		spi-max-frequency = <50000000>;
-		reg = <0>;
-
-		spi1_flash0@0 {
-			label = "spi1_flash0";
-			reg = <0x0 0x100000>;
-		};
-	};
-};
-
-&uart0 {
-	status = "okay";
-};
-
-&usb0 {
-	status = "okay";
-};
-
-&dwc3_0 {
-	status = "okay";
-	dr_mode = "peripheral";
-	maximum-speed = "high-speed";
-};
-
-&usb1 {
-	status = "okay";
-};
-
-&dwc3_1 {
-	status = "okay";
-	dr_mode = "host";
-	maximum-speed = "high-speed";
-};
-
-&watchdog0 {
-	status = "okay";
-};
-
-&xlnx_dp {
-	xlnx,max-pclock-frequency = <200000>;
-};
-
-&xlnx_dpdma {
-	xlnx,axi-clock-freq = <200000000>;
-};

arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts

@@ -11,7 +11,7 @@
 /dts-v1/;
 
 #include "zynqmp.dtsi"
-#include "zynqmp-clk.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
 
 / {
 	model = "ZynqMP zc1751-xm015-dc1 RevA";

arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts

@@ -11,7 +11,7 @@
 /dts-v1/;
 
 #include "zynqmp.dtsi"
-#include "zynqmp-clk.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
 
 / {
 	model = "ZynqMP zc1751-xm016-dc2 RevA";

arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts

@@ -11,7 +11,7 @@
 /dts-v1/;
 
 #include "zynqmp.dtsi"
-#include "zynqmp-clk.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
 
 / {
 	model = "ZynqMP zc1751-xm018-dc4";

arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts

@@ -12,7 +12,7 @@
 /dts-v1/;
 
 #include "zynqmp.dtsi"
-#include "zynqmp-clk.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
 / {
 	model = "ZynqMP zc1751-xm019-dc5 RevA";
 	compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";

arch/arm/dts/zynqmp-zcu102-revA.dts

@@ -11,7 +11,7 @@
 /dts-v1/;
 
 #include "zynqmp.dtsi"
-#include "zynqmp-clk.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
 #include <dt-bindings/phy/phy.h>

arch/arm/include/asm/arch-zynqmp/sys_proto.h

@@ -11,6 +11,8 @@
 #define PAYLOAD_ARG_CNT		5
 
 #define ZYNQMP_CSU_SILICON_VER_MASK	0xF
+#define ZYNQMP_SIP_SVC_PM_SECURE_IMG_LOAD	0xC200002D
+#define KEY_PTR_LEN	32
 
 enum {
 	IDCODE,

board/xilinx/zynq/MAINTAINERS

@@ -1,6 +1,7 @@
 ZYNQ BOARD
 M:	Michal Simek <monstr@monstr.eu>
 S:	Maintained
+F:	arch/arm/dts/zynq-*
 F:	board/xilinx/zynq/
 F:	include/configs/zynq*.h
 F:	configs/zynq_*_defconfig

board/xilinx/zynq/board.c

@@ -6,9 +6,11 @@
  */
 
 #include <common.h>
+#include <dm/uclass.h>
 #include <fdtdec.h>
 #include <fpga.h>
 #include <mmc.h>
+#include <wdt.h>
 #include <zynqpl.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/sys_proto.h>
@@ -33,6 +35,22 @@ static xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45);
 static xilinx_desc fpga100 = XILINX_XC7Z100_DESC(0x100);
 #endif
 
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT)
+static struct udevice *watchdog_dev;
+#endif
+
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_BOARD_EARLY_INIT_F)
+int board_early_init_f(void)
+{
+# if defined(CONFIG_WDT)
+	/* bss is not cleared at time when watchdog_reset() is called */
+	watchdog_dev = NULL;
+# endif
+
+	return 0;
+}
+#endif
+
 int board_init(void)
 {
 #if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
@@ -75,6 +93,15 @@ int board_init(void)
 	}
 #endif
 
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT)
+	if (uclass_get_device(UCLASS_WDT, 0, &watchdog_dev)) {
+		puts("Watchdog: Not found!\n");
+	} else {
+		wdt_start(watchdog_dev, 0, 0);
+		puts("Watchdog: Started\n");
+	}
+# endif
+
 #if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
     (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
 	fpga_init();
@@ -164,3 +191,25 @@ int dram_init(void)
 	return 0;
 }
 #endif
+
+#if defined(CONFIG_WATCHDOG)
+/* Called by macro WATCHDOG_RESET */
+void watchdog_reset(void)
+{
+# if !defined(CONFIG_SPL_BUILD)
+	static ulong next_reset;
+	ulong now;
+
+	if (!watchdog_dev)
+		return;
+
+	now = timer_get_us();
+
+	/* Do not reset the watchdog too often */
+	if (now > next_reset) {
+		wdt_reset(watchdog_dev);
+		next_reset = now + 1000;
+	}
+# endif
+}
+#endif

board/xilinx/zynqmp/Kconfig

@@ -0,0 +1,18 @@
+# Copyright (c) 2018, Xilinx, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0
+
+if ARCH_ZYNQMP
+
+config CMD_ZYNQMP
+	bool "Enable ZynqMP specific commands"
+	default y
+	help
+	  Enable ZynqMP specific commands like "zynqmp secure"
+	  which is used for zynqmp secure image verification.
+	  The secure image is a xilinx specific BOOT.BIN with
+	  either authentication or encryption or both encryption
+	  and authentication feature enabled while generating
+	  BOOT.BIN using Xilinx bootgen tool.
+
+endif

board/xilinx/zynqmp/MAINTAINERS

@@ -1,6 +1,7 @@
 XILINX_ZYNQMP BOARDS
 M:	Michal Simek <michal.simek@xilinx.com>
 S:	Maintained
+F:	arch/arm/dts/zynqmp-*
 F:	board/xilinx/zynqmp/
 F:	include/configs/xilinx_zynqmp*
 F:	configs/xilinx_zynqmp*

board/xilinx/zynqmp/Makefile

@@ -26,6 +26,10 @@ ifneq ($(call ifdef_any_of, CONFIG_ZYNQMP_PSU_INIT_ENABLED CONFIG_SPL_BUILD),)
 obj-y += $(init-objs)
 endif
 
+ifndef CONFIG_SPL_BUILD
+obj-$(CONFIG_CMD_ZYNQMP) += cmds.o
+endif
+
 # Suppress "warning: function declaration isn't a prototype"
 CFLAGS_REMOVE_psu_init_gpl.o := -Wstrict-prototypes
 

board/xilinx/zynqmp/cmds.c

@@ -0,0 +1,105 @@
+/*
+ * (C) Copyright 2018 Xilinx, Inc.
+ * Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/io.h>
+
+static int zynqmp_verify_secure(u8 *key_ptr, u8 *src_ptr, u32 len)
+{
+	int ret;
+	u32 src_lo, src_hi;
+	u32 key_lo = 0;
+	u32 key_hi = 0;
+	u32 ret_payload[PAYLOAD_ARG_CNT];
+	u64 addr;
+
+	if ((ulong)src_ptr != ALIGN((ulong)src_ptr,
+				    CONFIG_SYS_CACHELINE_SIZE)) {
+		printf("Failed: source address not aligned:%p\n", src_ptr);
+		return -EINVAL;
+	}
+
+	src_lo = lower_32_bits((ulong)src_ptr);
+	src_hi = upper_32_bits((ulong)src_ptr);
+	flush_dcache_range((ulong)src_ptr, (ulong)(src_ptr + len));
+
+	if (key_ptr) {
+		key_lo = lower_32_bits((ulong)key_ptr);
+		key_hi = upper_32_bits((ulong)key_ptr);
+		flush_dcache_range((ulong)key_ptr,
+				   (ulong)(key_ptr + KEY_PTR_LEN));
+	}
+
+	ret = invoke_smc(ZYNQMP_SIP_SVC_PM_SECURE_IMG_LOAD, src_lo, src_hi,
+			 key_lo, key_hi, ret_payload);
+	if (ret) {
+		printf("Failed: secure op status:0x%x\n", ret);
+	} else {
+		addr = (u64)ret_payload[1] << 32 | ret_payload[2];
+		printf("Verified image at 0x%llx\n", addr);
+		env_set_hex("zynqmp_verified_img_addr", addr);
+	}
+
+	return ret;
+}
+
+/**
+ * do_zynqmp - Handle the "zynqmp" command-line command
+ * @cmdtp:	Command data struct pointer
+ * @flag:	Command flag
+ * @argc:	Command-line argument count
+ * @argv:	Array of command-line arguments
+ *
+ * Processes the zynqmp specific commands
+ *
+ * Return: return 0 on success and CMD_RET_USAGE incase of misuse and error
+ */
+static int do_zynqmp(cmd_tbl_t *cmdtp, int flag, int argc,
+		     char *const argv[])
+{
+	u64 src_addr;
+	u32 len;
+	u8 *key_ptr = NULL;
+	u8 *src_ptr;
+	int ret;
+
+	if (argc > 5 || argc < 4 || strncmp(argv[1], "secure", 6))
+		return CMD_RET_USAGE;
+
+	src_addr = simple_strtoull(argv[2], NULL, 16);
+
+	len = simple_strtoul(argv[3], NULL, 16);
+
+	if (argc > 4)
+		key_ptr = (uint8_t *)(uintptr_t)simple_strtoull(argv[4],
+								NULL, 16);
+
+	src_ptr = (uint8_t *)(uintptr_t)src_addr;
+
+	ret = zynqmp_verify_secure(key_ptr, src_ptr, len);
+	if (ret)
+		return CMD_RET_FAILURE;
+
+	return CMD_RET_SUCCESS;
+}
+
+/***************************************************/
+#ifdef CONFIG_SYS_LONGHELP
+static char zynqmp_help_text[] =
+	"secure src len [key_addr] - verifies secure images of $len bytes\n"
+	"                            long at address $src. Optional key_addr\n"
+	"                            can be specified if user key needs to\n"
+	"                            be used for decryption\n";
+#endif
+
+U_BOOT_CMD(
+	zynqmp, 5, 1, do_zynqmp,
+	"Verify and load secure images",
+	zynqmp_help_text
+)

board/xilinx/zynqmp/zynqmp.c

@@ -31,6 +31,7 @@ static const struct {
 	u32 id;
 	u32 ver;
 	char *name;
+	bool evexists;
 } zynqmp_devices[] = {
 	{
 		.id = 0x10,
@@ -53,11 +54,13 @@ static const struct {
 	{
 		.id = 0x20,
 		.name = "5ev",
+		.evexists = 1,
 	},
 	{
 		.id = 0x20,
 		.ver = 0x100,
 		.name = "5eg",
+		.evexists = 1,
 	},
 	{
 		.id = 0x20,
@@ -67,11 +70,13 @@ static const struct {
 	{
 		.id = 0x21,
 		.name = "4ev",
+		.evexists = 1,
 	},
 	{
 		.id = 0x21,
 		.ver = 0x100,
 		.name = "4eg",
+		.evexists = 1,
 	},
 	{
 		.id = 0x21,
@@ -81,11 +86,13 @@ static const struct {
 	{
 		.id = 0x30,
 		.name = "7ev",
+		.evexists = 1,
 	},
 	{
 		.id = 0x30,
 		.ver = 0x100,
 		.name = "7eg",
+		.evexists = 1,
 	},
 	{
 		.id = 0x30,
@@ -219,20 +226,48 @@ int chip_id(unsigned char id)
 	return val;
 }
 
+#define ZYNQMP_VERSION_SIZE		9
+#define ZYNQMP_PL_STATUS_BIT		9
+#define ZYNQMP_PL_STATUS_MASK		BIT(ZYNQMP_PL_STATUS_BIT)
+#define ZYNQMP_CSU_VERSION_MASK		~(ZYNQMP_PL_STATUS_MASK)
+
 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
 	!defined(CONFIG_SPL_BUILD)
 static char *zynqmp_get_silicon_idcode_name(void)
 {
 	u32 i, id, ver;
+	char *buf;
+	static char name[ZYNQMP_VERSION_SIZE];
 
 	id = chip_id(IDCODE);
 	ver = chip_id(IDCODE2);
 
 	for (i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) {
-		if (zynqmp_devices[i].id == id && zynqmp_devices[i].ver == ver)
+		if ((zynqmp_devices[i].id == id) &&
-			return zynqmp_devices[i].name;
+		    (zynqmp_devices[i].ver == (ver &
+		    ZYNQMP_CSU_VERSION_MASK))) {
+			strncat(name, "zu", 2);
+			strncat(name, zynqmp_devices[i].name,
+				ZYNQMP_VERSION_SIZE - 3);
+			break;
 		}
+	}
+
+	if (i >= ARRAY_SIZE(zynqmp_devices))
 		return "unknown";
+
+	if (!zynqmp_devices[i].evexists)
+		return name;
+
+	if (ver & ZYNQMP_PL_STATUS_MASK)
+		return name;
+
+	if (strstr(name, "eg") || strstr(name, "ev")) {
+		buf = strstr(name, "e");
+		*buf = '\0';
+	}
+
+	return name;
 }
 #endif
 
@@ -250,8 +285,6 @@ int board_early_init_f(void)
 	return ret;
 }
 
-#define ZYNQMP_VERSION_SIZE	9
-
 int board_init(void)
 {
 	printf("EL Level:\tEL%d\n", current_el());
@@ -260,12 +293,7 @@ int board_init(void)
     !defined(CONFIG_SPL_BUILD) || (defined(CONFIG_SPL_FPGA_SUPPORT) && \
     defined(CONFIG_SPL_BUILD))
 	if (current_el() != 3) {
-		static char version[ZYNQMP_VERSION_SIZE];
+		zynqmppl.name = zynqmp_get_silicon_idcode_name();
-
-		strncat(version, "zu", 2);
-		zynqmppl.name = strncat(version,
-					zynqmp_get_silicon_idcode_name(),
-					ZYNQMP_VERSION_SIZE - 3);
 		printf("Chip ID:\t%s\n", zynqmppl.name);
 		fpga_init();
 		fpga_add(fpga_xilinx, &zynqmppl);
@@ -316,6 +344,23 @@ int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
 	return 0;
 }
 
+unsigned long do_go_exec(ulong (*entry)(int, char * const []), int argc,
+			 char * const argv[])
+{
+	int ret = 0;
+
+	if (current_el() > 1) {
+		smp_kick_all_cpus();
+		dcache_disable();
+		armv8_switch_to_el1(0x0, 0, 0, 0, (unsigned long)entry,
+				    ES_TO_AARCH64);
+	} else {
+		printf("FAIL: current EL is not above EL1\n");
+		ret = EINVAL;
+	}
+	return ret;
+}
+
 #if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
 int dram_init_banksize(void)
 {

configs/microblaze-generic_defconfig

@@ -3,6 +3,7 @@ CONFIG_SYS_TEXT_BASE=0x29000000
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL=y
 CONFIG_TARGET_MICROBLAZE_GENERIC=y
 CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR=1
 CONFIG_XILINX_MICROBLAZE0_USE_BARREL=1
@@ -15,7 +16,6 @@ CONFIG_BOOTDELAY=-1
 CONFIG_USE_BOOTARGS=y
 CONFIG_BOOTARGS="root=romfs"
 CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_SPL=y
 CONFIG_SPL_BOARD_INIT=y
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 CONFIG_SPL_NOR_SUPPORT=y

configs/syzygy_hub_defconfig

@@ -3,6 +3,7 @@ CONFIG_SYS_VENDOR="opalkelly"
 CONFIG_SYS_CONFIG_NAME="syzygy_hub"
 CONFIG_ARCH_ZYNQ=y
 CONFIG_SYS_TEXT_BASE=0x4000000
+CONFIG_SPL=y
 CONFIG_SPL_STACK_R_ADDR=0x200000
 CONFIG_DEFAULT_DEVICE_TREE="zynq-syzygy-hub"
 CONFIG_DEBUG_UART=y
@@ -12,7 +13,6 @@ CONFIG_FIT_SIGNATURE=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd"
 # CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_OS_BOOT=y
 CONFIG_SYS_PROMPT="Zynq> "

configs/topic_miami_defconfig

@@ -3,6 +3,7 @@ CONFIG_SYS_VENDOR="topic"
 CONFIG_SYS_CONFIG_NAME="topic_miami"
 CONFIG_ARCH_ZYNQ=y
 CONFIG_SYS_TEXT_BASE=0x4000000
+CONFIG_SPL=y
 CONFIG_SPL_STACK_R_ADDR=0x200000
 CONFIG_BOOT_INIT_FILE="board/topic/zynq/zynq-topic-miami/ps7_regs.txt"
 CONFIG_DEFAULT_DEVICE_TREE="zynq-topic-miami"
@@ -11,7 +12,6 @@ CONFIG_DISTRO_DEFAULTS=y
 CONFIG_BOOTDELAY=0
 CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd"
 # CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
 CONFIG_SYS_PROMPT="zynq-uboot> "
 CONFIG_CMD_THOR_DOWNLOAD=y

configs/topic_miamilite_defconfig

@@ -3,6 +3,7 @@ CONFIG_SYS_VENDOR="topic"
 CONFIG_SYS_CONFIG_NAME="topic_miami"
 CONFIG_ARCH_ZYNQ=y
 CONFIG_SYS_TEXT_BASE=0x4000000
+CONFIG_SPL=y
 CONFIG_SPL_STACK_R_ADDR=0x200000
 CONFIG_BOOT_INIT_FILE="board/topic/zynq/zynq-topic-miamilite/ps7_regs.txt"
 CONFIG_DEFAULT_DEVICE_TREE="zynq-topic-miamilite"
@@ -11,7 +12,6 @@ CONFIG_DISTRO_DEFAULTS=y
 CONFIG_BOOTDELAY=0
 CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd"
 # CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
 CONFIG_SYS_PROMPT="zynq-uboot> "
 CONFIG_CMD_THOR_DOWNLOAD=y

configs/topic_miamiplus_defconfig

@@ -3,6 +3,7 @@ CONFIG_SYS_VENDOR="topic"
 CONFIG_SYS_CONFIG_NAME="topic_miami"
 CONFIG_ARCH_ZYNQ=y
 CONFIG_SYS_TEXT_BASE=0x4000000
+CONFIG_SPL=y
 CONFIG_SPL_STACK_R_ADDR=0x200000
 CONFIG_BOOT_INIT_FILE="board/topic/zynq/zynq-topic-miamiplus/ps7_regs.txt"
 CONFIG_DEFAULT_DEVICE_TREE="zynq-topic-miamiplus"
@@ -11,7 +12,6 @@ CONFIG_DISTRO_DEFAULTS=y
 CONFIG_BOOTDELAY=0
 CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd"
 # CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
 CONFIG_SYS_PROMPT="zynq-uboot> "
 CONFIG_CMD_THOR_DOWNLOAD=y

configs/xilinx_zynqmp_ep_defconfig

@@ -1,102 +0,0 @@
-CONFIG_ARM=y
-CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_ep"
-CONFIG_ARCH_ZYNQMP=y
-CONFIG_SYS_TEXT_BASE=0x8000000
-CONFIG_SYS_MALLOC_F_LEN=0x8000
-CONFIG_ZYNQ_SDHCI_MAX_FREQ=52000000
-CONFIG_ZYNQMP_USB=y
-CONFIG_DEFAULT_DEVICE_TREE="zynqmp-ep108"
-CONFIG_DEBUG_UART=y
-CONFIG_AHCI=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_SPL_LOAD_FIT=y
-# CONFIG_DISPLAY_CPUINFO is not set
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL=y
-CONFIG_SPL_OS_BOOT=y
-CONFIG_SYS_PROMPT="ZynqMP> "
-CONFIG_FASTBOOT=y
-CONFIG_FASTBOOT_FLASH=y
-CONFIG_FASTBOOT_FLASH_MMC_DEV=0
-# CONFIG_CMD_CONSOLE is not set
-# CONFIG_CMD_XIMG is not set
-CONFIG_CMD_THOR_DOWNLOAD=y
-# CONFIG_CMD_EDITENV is not set
-# CONFIG_CMD_ENV_EXISTS is not set
-CONFIG_CMD_CLK=y
-CONFIG_CMD_DFU=y
-# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-# CONFIG_CMD_LOADB is not set
-# CONFIG_CMD_LOADS is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND_LOCK_UNLOCK=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_ITEST is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_TFTPPUT=y
-# CONFIG_CMD_NFS is not set
-CONFIG_CMD_TIME=y
-CONFIG_CMD_TIMER=y
-CONFIG_CMD_EXT4_WRITE=y
-# CONFIG_SPL_ISO_PARTITION is not set
-CONFIG_SPL_OF_CONTROL=y
-CONFIG_OF_EMBED=y
-CONFIG_ENV_IS_IN_FAT=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_SPL_DM=y
-CONFIG_SPL_DM_SEQ_ALIAS=y
-CONFIG_SCSI_AHCI=y
-CONFIG_SATA_CEVA=y
-CONFIG_DFU_RAM=y
-CONFIG_FPGA_XILINX=y
-CONFIG_FPGA_ZYNQMPPL=y
-CONFIG_DM_GPIO=y
-CONFIG_DM_I2C=y
-CONFIG_SYS_I2C_CADENCE=y
-CONFIG_MISC=y
-CONFIG_DM_MMC=y
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_ZYNQ=y
-CONFIG_ZYNQ_SDHCI_MIN_FREQ=100000
-CONFIG_NAND=y
-CONFIG_NAND_ARASAN=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_BAR=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_WINBOND=y
-# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_TI=y
-CONFIG_PHY_VITESSE=y
-CONFIG_DM_ETH=y
-CONFIG_PHY_GIGE=y
-CONFIG_ZYNQ_GEM=y
-CONFIG_SCSI=y
-CONFIG_DM_SCSI=y
-CONFIG_DEBUG_UART_ZYNQ=y
-CONFIG_DEBUG_UART_BASE=0xff000000
-CONFIG_DEBUG_UART_CLOCK=25000000
-CONFIG_DEBUG_UART_ANNOUNCE=y
-CONFIG_ZYNQ_SERIAL=y
-CONFIG_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_USB_XHCI_ZYNQMP=y
-CONFIG_USB_DWC3=y
-CONFIG_USB_DWC3_GADGET=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="Xilinx"
-CONFIG_USB_GADGET_VENDOR_NUM=0x03fd
-CONFIG_USB_GADGET_PRODUCT_NUM=0x0300
-CONFIG_USB_FUNCTION_THOR=y
-# CONFIG_REGEX is not set
-CONFIG_EFI_LOADER_BOUNCE_BUFFER=y

configs/xilinx_zynqmp_mini_emmc_defconfig

@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_mini_emmc"
 CONFIG_ARCH_ZYNQMP=y
 CONFIG_SYS_TEXT_BASE=0x10000
+# CONFIG_CMD_ZYNQMP is not set
 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-mini-emmc"
 CONFIG_ENV_VARS_UBOOT_CONFIG=y
 CONFIG_FIT=y

configs/xilinx_zynqmp_mini_nand_defconfig

@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_mini_nand"
 CONFIG_ARCH_ZYNQMP=y
 CONFIG_SYS_TEXT_BASE=0x10000
+# CONFIG_CMD_ZYNQMP is not set
 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-mini-nand"
 CONFIG_ENV_VARS_UBOOT_CONFIG=y
 CONFIG_FIT=y

configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig

@@ -3,6 +3,7 @@ CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zc1751_xm015_dc1"
 CONFIG_ARCH_ZYNQMP=y
 CONFIG_SYS_TEXT_BASE=0x8000000
 CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SPL=y
 CONFIG_IDENT_STRING=" Xilinx ZynqMP ZC1751 xm015 dc1"
 CONFIG_ZYNQMP_USB=y
 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm015-dc1"
@@ -14,7 +15,6 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_SPL_LOAD_FIT=y
 # CONFIG_DISPLAY_CPUINFO is not set
 # CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL=y
 CONFIG_SPL_OS_BOOT=y
 CONFIG_SPL_RAM_SUPPORT=y
 CONFIG_SPL_RAM_DEVICE=y
@@ -45,6 +45,7 @@ CONFIG_ENV_IS_IN_FAT=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_CLK_ZYNQMP=y
 CONFIG_DFU_RAM=y
 CONFIG_FPGA_XILINX=y
 CONFIG_FPGA_ZYNQMPPL=y

configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig

@@ -4,6 +4,7 @@ CONFIG_ARCH_ZYNQMP=y
 CONFIG_SYS_TEXT_BASE=0x8000000
 CONFIG_SYS_MALLOC_F_LEN=0x8000
 # CONFIG_SPL_LIBDISK_SUPPORT is not set
+CONFIG_SPL=y
 CONFIG_IDENT_STRING=" Xilinx ZynqMP ZC1751 xm016 dc2"
 # CONFIG_SPL_FAT_SUPPORT is not set
 CONFIG_ZYNQMP_USB=y
@@ -15,7 +16,6 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_SPL_LOAD_FIT=y
 # CONFIG_DISPLAY_CPUINFO is not set
 # CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL=y
 CONFIG_SPL_OS_BOOT=y
 CONFIG_SPL_RAM_SUPPORT=y
 CONFIG_SPL_RAM_DEVICE=y
@@ -44,6 +44,7 @@ CONFIG_OF_EMBED=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_CLK_ZYNQMP=y
 CONFIG_DFU_RAM=y
 CONFIG_FPGA_XILINX=y
 CONFIG_FPGA_ZYNQMPPL=y

configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig

@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_ZYNQMP=y
 CONFIG_SYS_TEXT_BASE=0x8000000
 CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SPL=y
 CONFIG_IDENT_STRING=" Xilinx ZynqMP ZC1751 xm018 dc4"
 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm018-dc4"
 CONFIG_DEBUG_UART=y
@@ -11,7 +12,6 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_SPL_LOAD_FIT=y
 # CONFIG_DISPLAY_CPUINFO is not set
 # CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL=y
 CONFIG_SPL_OS_BOOT=y
 CONFIG_SPL_RAM_SUPPORT=y
 CONFIG_SPL_RAM_DEVICE=y
@@ -34,6 +34,7 @@ CONFIG_ENV_IS_IN_FAT=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_CLK_ZYNQMP=y
 CONFIG_FPGA_XILINX=y
 CONFIG_FPGA_ZYNQMPPL=y
 CONFIG_DM_GPIO=y

configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig

@@ -3,6 +3,7 @@ CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zc1751_xm019_dc5"
 CONFIG_ARCH_ZYNQMP=y
 CONFIG_SYS_TEXT_BASE=0x8000000
 CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SPL=y
 CONFIG_IDENT_STRING=" Xilinx ZynqMP ZC1751 xm019 dc5"
 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm019-dc5"
 CONFIG_DEBUG_UART=y
@@ -12,7 +13,6 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_SPL_LOAD_FIT=y
 # CONFIG_DISPLAY_CPUINFO is not set
 # CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL=y
 CONFIG_SPL_OS_BOOT=y
 CONFIG_SPL_RAM_SUPPORT=y
 CONFIG_SPL_RAM_DEVICE=y
@@ -34,6 +34,7 @@ CONFIG_OF_EMBED=y
 CONFIG_ENV_IS_IN_FAT=y
 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_CLK_ZYNQMP=y
 CONFIG_FPGA_XILINX=y
 CONFIG_FPGA_ZYNQMPPL=y
 CONFIG_DM_GPIO=y
@@ -44,6 +45,8 @@ CONFIG_DM_MMC=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ZYNQ=y
 CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_ZYNQ_GEM=y
 CONFIG_DEBUG_UART_ZYNQ=y
 CONFIG_DEBUG_UART_BASE=0xff000000
 CONFIG_DEBUG_UART_CLOCK=100000000

configs/xilinx_zynqmp_zcu102_rev1_0_defconfig

@@ -3,6 +3,7 @@ CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zcu102"
 CONFIG_ARCH_ZYNQMP=y
 CONFIG_SYS_TEXT_BASE=0x8000000
 CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SPL=y
 CONFIG_IDENT_STRING=" Xilinx ZynqMP ZCU102 rev1.0"
 CONFIG_ZYNQMP_USB=y
 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu102-rev1.0"
@@ -14,7 +15,6 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_SPL_LOAD_FIT=y
 # CONFIG_DISPLAY_CPUINFO is not set
 # CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL=y
 CONFIG_SPL_OS_BOOT=y
 CONFIG_SPL_RAM_SUPPORT=y
 CONFIG_SPL_RAM_DEVICE=y
@@ -48,6 +48,7 @@ CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_SCSI_AHCI=y
 CONFIG_SATA_CEVA=y
+CONFIG_CLK_ZYNQMP=y
 CONFIG_DFU_RAM=y
 CONFIG_FPGA_XILINX=y
 CONFIG_FPGA_ZYNQMPPL=y

configs/xilinx_zynqmp_zcu102_revA_defconfig

@@ -3,6 +3,7 @@ CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zcu102"
 CONFIG_ARCH_ZYNQMP=y
 CONFIG_SYS_TEXT_BASE=0x8000000
 CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SPL=y
 CONFIG_IDENT_STRING=" Xilinx ZynqMP ZCU102 revA"
 CONFIG_ZYNQMP_USB=y
 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu102-revA"
@@ -14,7 +15,6 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_SPL_LOAD_FIT=y
 # CONFIG_DISPLAY_CPUINFO is not set
 # CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL=y
 CONFIG_SPL_OS_BOOT=y
 CONFIG_SPL_RAM_SUPPORT=y
 CONFIG_SPL_RAM_DEVICE=y
@@ -48,6 +48,7 @@ CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_SCSI_AHCI=y
 CONFIG_SATA_CEVA=y
+CONFIG_CLK_ZYNQMP=y
 CONFIG_DFU_RAM=y
 CONFIG_FPGA_XILINX=y
 CONFIG_FPGA_ZYNQMPPL=y

configs/xilinx_zynqmp_zcu102_revB_defconfig

@@ -3,6 +3,7 @@ CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zcu102"
 CONFIG_ARCH_ZYNQMP=y
 CONFIG_SYS_TEXT_BASE=0x8000000
 CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SPL=y
 CONFIG_IDENT_STRING=" Xilinx ZynqMP ZCU102 revB"
 CONFIG_ZYNQMP_USB=y
 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu102-revB"
@@ -14,7 +15,6 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_SPL_LOAD_FIT=y
 # CONFIG_DISPLAY_CPUINFO is not set
 # CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL=y
 CONFIG_SPL_OS_BOOT=y
 CONFIG_SPL_RAM_SUPPORT=y
 CONFIG_SPL_RAM_DEVICE=y
@@ -48,6 +48,7 @@ CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_SCSI_AHCI=y
 CONFIG_SATA_CEVA=y
+CONFIG_CLK_ZYNQMP=y
 CONFIG_DFU_RAM=y
 CONFIG_FPGA_XILINX=y
 CONFIG_FPGA_ZYNQMPPL=y

configs/zynq_cc108_defconfig

@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_ARCH_ZYNQ=y
 CONFIG_SYS_TEXT_BASE=0x4000000
+CONFIG_SPL=y
 CONFIG_SPL_STACK_R_ADDR=0x200000
 CONFIG_DEFAULT_DEVICE_TREE="zynq-cc108"
 CONFIG_DEBUG_UART=y
@@ -10,7 +11,6 @@ CONFIG_FIT_SIGNATURE=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd"
 # CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
 CONFIG_SYS_PROMPT="Zynq> "
 CONFIG_CMD_DFU=y

configs/zynq_cse_qspi_defconfig

@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_SYS_CONFIG_NAME="zynq_cse"
 CONFIG_ARCH_ZYNQ=y
 CONFIG_SYS_TEXT_BASE=0xFFFC0000
+CONFIG_SPL=y
 CONFIG_SPL_STACK_R_ADDR=0x200000
 # CONFIG_ZYNQ_DDRC_INIT is not set
 CONFIG_DEFAULT_DEVICE_TREE="zynq-cse-qspi-single"
@@ -11,7 +12,6 @@ CONFIG_DISTRO_DEFAULTS=y
 CONFIG_BOOTDELAY=-1
 # CONFIG_USE_BOOTCOMMAND is not set
 # CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
 CONFIG_SYS_PROMPT="Zynq> "
 # CONFIG_CMD_BDI is not set

configs/zynq_microzed_defconfig

@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_ARCH_ZYNQ=y
 CONFIG_SYS_TEXT_BASE=0x4000000
+CONFIG_SPL=y
 CONFIG_SPL_STACK_R_ADDR=0x200000
 CONFIG_DEFAULT_DEVICE_TREE="zynq-microzed"
 CONFIG_DISTRO_DEFAULTS=y
@@ -9,7 +10,6 @@ CONFIG_FIT_SIGNATURE=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd"
 # CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_OS_BOOT=y
 CONFIG_SYS_PROMPT="Zynq> "

configs/zynq_picozed_defconfig

@@ -1,12 +1,12 @@
 CONFIG_ARM=y
 CONFIG_ARCH_ZYNQ=y
 CONFIG_SYS_TEXT_BASE=0x4000000
+CONFIG_SPL=y
 CONFIG_SPL_STACK_R_ADDR=0x200000
 CONFIG_DEFAULT_DEVICE_TREE="zynq-picozed"
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd"
 # CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_OS_BOOT=y
 CONFIG_SYS_PROMPT="Zynq> "

configs/zynq_z_turn_defconfig

@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_ARCH_ZYNQ=y
 CONFIG_SYS_TEXT_BASE=0x4000000
+CONFIG_SPL=y
 CONFIG_SPL_STACK_R_ADDR=0x200000
 CONFIG_DEFAULT_DEVICE_TREE="zynq-zturn-myir"
 CONFIG_DEBUG_UART=y
@@ -10,7 +11,6 @@ CONFIG_FIT_SIGNATURE=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd"
 # CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_OS_BOOT=y
 CONFIG_SYS_PROMPT="Zynq> "

configs/zynq_zc702_defconfig

@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_SYS_CONFIG_NAME="zynq_zc70x"
 CONFIG_ARCH_ZYNQ=y
 CONFIG_SYS_TEXT_BASE=0x4000000
+CONFIG_SPL=y
 CONFIG_IDENT_STRING=" Xilinx Zynq ZC702"
 CONFIG_SPL_STACK_R_ADDR=0x200000
 CONFIG_DEFAULT_DEVICE_TREE="zynq-zc702"
@@ -12,7 +13,6 @@ CONFIG_FIT_SIGNATURE=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd"
 # CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_OS_BOOT=y
 CONFIG_SYS_PROMPT="Zynq> "

configs/zynq_zc706_defconfig

@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_SYS_CONFIG_NAME="zynq_zc70x"
 CONFIG_ARCH_ZYNQ=y
 CONFIG_SYS_TEXT_BASE=0x4000000
+CONFIG_SPL=y
 CONFIG_IDENT_STRING=" Xilinx Zynq ZC706"
 CONFIG_SPL_STACK_R_ADDR=0x200000
 CONFIG_DEFAULT_DEVICE_TREE="zynq-zc706"
@@ -12,7 +13,6 @@ CONFIG_FIT_SIGNATURE=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd"
 # CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_OS_BOOT=y
 CONFIG_SYS_PROMPT="Zynq> "
@@ -73,3 +73,5 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0x0300
 CONFIG_CI_UDC=y
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_USB_FUNCTION_THOR=y
+CONFIG_WDT=y
+CONFIG_WDT_CDNS=y

configs/zynq_zc770_xm010_defconfig

@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_ARCH_ZYNQ=y
 CONFIG_SYS_TEXT_BASE=0x4000000
+CONFIG_SPL=y
 CONFIG_IDENT_STRING=" Xilinx Zynq ZC770 XM010"
 CONFIG_SPL_STACK_R_ADDR=0x200000
 CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm010"
@@ -11,7 +12,6 @@ CONFIG_FIT_SIGNATURE=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd"
 # CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_OS_BOOT=y
 CONFIG_SYS_PROMPT="Zynq> "

configs/zynq_zc770_xm011_defconfig

@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_ARCH_ZYNQ=y
 CONFIG_SYS_TEXT_BASE=0x4000000
+CONFIG_SPL=y
 CONFIG_IDENT_STRING=" Xilinx Zynq ZC770 XM011"
 CONFIG_SPL_STACK_R_ADDR=0x200000
 # CONFIG_SPL_FAT_SUPPORT is not set
@@ -12,7 +13,6 @@ CONFIG_FIT_SIGNATURE=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd"
 # CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_OS_BOOT=y
 CONFIG_SYS_PROMPT="Zynq> "

configs/zynq_zc770_xm011_x16_defconfig

@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_ARCH_ZYNQ=y
 CONFIG_SYS_TEXT_BASE=0x4000000
+CONFIG_SPL=y
 CONFIG_IDENT_STRING=" Xilinx Zynq ZC770 XM011 x16"
 CONFIG_SPL_STACK_R_ADDR=0x200000
 # CONFIG_SPL_FAT_SUPPORT is not set
@@ -10,9 +11,8 @@ CONFIG_DISTRO_DEFAULTS=y
 CONFIG_FIT=y
 CONFIG_FIT_SIGNATURE=y
 CONFIG_FIT_VERBOSE=y
-# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd"
 # CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_OS_BOOT=y
 CONFIG_SYS_PROMPT="Zynq> "
@@ -29,7 +29,6 @@ CONFIG_CMD_CACHE=y
 # CONFIG_SPL_DOS_PARTITION is not set
 # CONFIG_SPL_ISO_PARTITION is not set
 # CONFIG_SPL_EFI_PARTITION is not set
-CONFIG_OF_EMBED=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_FPGA_XILINX=y
 CONFIG_FPGA_ZYNQPL=y

configs/zynq_zc770_xm012_defconfig

@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_ARCH_ZYNQ=y
 CONFIG_SYS_TEXT_BASE=0x4000000
+CONFIG_SPL=y
 CONFIG_IDENT_STRING=" Xilinx Zynq ZC770 XM012"
 CONFIG_SPL_STACK_R_ADDR=0x200000
 # CONFIG_SPL_FAT_SUPPORT is not set
@@ -11,7 +12,6 @@ CONFIG_FIT_SIGNATURE=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd"
 # CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_OS_BOOT=y
 CONFIG_SYS_PROMPT="Zynq> "

configs/zynq_zc770_xm013_defconfig

@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_ARCH_ZYNQ=y
 CONFIG_SYS_TEXT_BASE=0x4000000
+CONFIG_SPL=y
 CONFIG_IDENT_STRING=" Xilinx Zynq ZC770 XM013"
 CONFIG_SPL_STACK_R_ADDR=0x200000
 # CONFIG_SPL_FAT_SUPPORT is not set
@@ -11,7 +12,6 @@ CONFIG_FIT_SIGNATURE=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd"
 # CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_OS_BOOT=y
 CONFIG_SYS_PROMPT="Zynq> "

configs/zynq_zed_defconfig

@@ -1,15 +1,16 @@
 CONFIG_ARM=y
 CONFIG_ARCH_ZYNQ=y
 CONFIG_SYS_TEXT_BASE=0x4000000
+CONFIG_SPL=y
 CONFIG_SPL_STACK_R_ADDR=0x200000
 CONFIG_DEFAULT_DEVICE_TREE="zynq-zed"
+CONFIG_DEBUG_UART=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_FIT=y
 CONFIG_FIT_SIGNATURE=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd"
 # CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_OS_BOOT=y
 CONFIG_SYS_PROMPT="Zynq> "
@@ -47,6 +48,9 @@ CONFIG_PHY_MARVELL=y
 CONFIG_PHY_REALTEK=y
 CONFIG_PHY_XILINX=y
 CONFIG_ZYNQ_GEM=y
+CONFIG_DEBUG_UART_ZYNQ=y
+CONFIG_DEBUG_UART_BASE=0xe0001000
+CONFIG_DEBUG_UART_CLOCK=50000000
 CONFIG_ZYNQ_SERIAL=y
 CONFIG_ZYNQ_QSPI=y
 CONFIG_USB=y

configs/zynq_zybo_defconfig

@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_SYS_CONFIG_NAME="zynq_zybo"
 CONFIG_ARCH_ZYNQ=y
 CONFIG_SYS_TEXT_BASE=0x4000000
+CONFIG_SPL=y
 CONFIG_SPL_STACK_R_ADDR=0x200000
 CONFIG_DEFAULT_DEVICE_TREE="zynq-zybo"
 CONFIG_DEBUG_UART=y
@@ -11,7 +12,6 @@ CONFIG_FIT_SIGNATURE=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd"
 # CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_OS_BOOT=y
 CONFIG_SYS_PROMPT="Zynq> "

drivers/clk/clk_zynq.c

@@ -394,7 +394,7 @@ static ulong zynq_clk_get_rate(struct clk *clk)
 		return zynq_clk_get_peripheral_rate(priv, id, two_divs);
 	case dma_clk:
 		return zynq_clk_get_cpu_rate(priv, cpu_2x_clk);
-	case usb0_aper_clk ... smc_aper_clk:
+	case usb0_aper_clk ... swdt_clk:
 		return zynq_clk_get_cpu_rate(priv, cpu_1x_clk);
 	default:
 		return -ENXIO;

drivers/clk/clk_zynqmp.c

@@ -226,6 +226,18 @@ static u32 zynqmp_clk_get_register(enum zynqmp_clk id)
 		return CRL_APB_CAN0_REF_CTRL;
 	case can1_ref:
 		return CRL_APB_CAN1_REF_CTRL;
+	case pl0:
+		return CRL_APB_PL0_REF_CTRL;
+	case pl1:
+		return CRL_APB_PL1_REF_CTRL;
+	case pl2:
+		return CRL_APB_PL2_REF_CTRL;
+	case pl3:
+		return CRL_APB_PL3_REF_CTRL;
+	case wdt:
+		return CRF_APB_TOPSW_LSBUS_CTRL;
+	case iopll_to_fpd:
+		return CRL_APB_IOPLL_TO_FPD_CTRL;
 	default:
 		debug("Invalid clk id%d\n", id);
 	}
@@ -278,6 +290,22 @@ static enum zynqmp_clk zynqmp_clk_get_peripheral_pll(u32 clk_ctrl)
 	}
 }
 
+static enum zynqmp_clk zynqmp_clk_get_wdt_pll(u32 clk_ctrl)
+{
+	u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >>
+		      CLK_CTRL_SRCSEL_SHIFT;
+
+	switch (srcsel) {
+	case 2:
+		return iopll_to_fpd;
+	case 3:
+		return dpll;
+	case 0 ... 1:
+	default:
+		return apll;
+	}
+}
+
 static ulong zynqmp_clk_get_pll_src(ulong clk_ctrl,
 				    struct zynqmp_clk_priv *priv,
 				    bool is_pre_src)
@@ -420,6 +448,49 @@ static ulong zynqmp_clk_get_peripheral_rate(struct zynqmp_clk_priv *priv,
 			DIV_ROUND_CLOSEST(pllrate, div0), div1);
 }
 
+static ulong zynqmp_clk_get_wdt_rate(struct zynqmp_clk_priv *priv,
+				     enum zynqmp_clk id, bool two_divs)
+{
+	enum zynqmp_clk pll;
+	u32 clk_ctrl, div0;
+	u32 div1 = 1;
+	int ret;
+	ulong pllrate;
+
+	ret = zynqmp_mmio_read(zynqmp_clk_get_register(id), &clk_ctrl);
+	if (ret) {
+		printf("%d %s mio read fail\n", __LINE__, __func__);
+		return -EIO;
+	}
+
+	div0 = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
+	if (!div0)
+		div0 = 1;
+
+	pll = zynqmp_clk_get_wdt_pll(clk_ctrl);
+	if (two_divs) {
+		ret = zynqmp_mmio_read(zynqmp_clk_get_register(pll), &clk_ctrl);
+		if (ret) {
+			printf("%d %s mio read fail\n", __LINE__, __func__);
+			return -EIO;
+		}
+		div1 = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
+		if (!div1)
+			div1 = 1;
+	}
+
+	if (pll == iopll_to_fpd)
+		pll = iopll;
+
+	pllrate = zynqmp_clk_get_pll_rate(priv, pll);
+	if (IS_ERR_VALUE(pllrate))
+		return pllrate;
+
+	return
+		DIV_ROUND_CLOSEST(
+			DIV_ROUND_CLOSEST(pllrate, div0), div1);
+}
+
 static unsigned long zynqmp_clk_calc_peripheral_two_divs(ulong rate,
 						       ulong pll_rate,
 						       u32 *div0, u32 *div1)
@@ -510,8 +581,12 @@ static ulong zynqmp_clk_get_rate(struct clk *clk)
 		return zynqmp_clk_get_ddr_rate(priv);
 	case gem0_ref ... gem3_ref:
 	case qspi_ref ... can1_ref:
+	case pl0 ... pl3:
 		two_divs = true;
 		return zynqmp_clk_get_peripheral_rate(priv, id, two_divs);
+	case wdt:
+		two_divs = true;
+		return zynqmp_clk_get_wdt_rate(priv, id, two_divs);
 	default:
 		return -ENXIO;
 	}

drivers/fpga/fpga.c

@@ -148,10 +148,14 @@ int fpga_add(fpga_type devtype, void *desc)
 {
 	int devnum = FPGA_INVALID_DEVICE;
 
+	if (!desc) {
+		printf("%s: NULL device descriptor\n", __func__);
+		return devnum;
+	}
+
 	if (next_desc < 0) {
 		printf("%s: FPGA support not initialized!\n", __func__);
 	} else if ((devtype > fpga_min_type) && (devtype < fpga_undefined)) {
-		if (desc) {
 		if (next_desc < CONFIG_MAX_FPGA_DEVICES) {
 			devnum = next_desc;
 			desc_table[next_desc].devtype = devtype;
@@ -160,9 +164,6 @@ int fpga_add(fpga_type devtype, void *desc)
 			printf("%s: Exceeded Max FPGA device count\n",
 			       __func__);
 		}
-		} else {
-			printf("%s: NULL device descriptor\n", __func__);
-		}
 	} else {
 		printf("%s: Unsupported FPGA type %d\n", __func__, devtype);
 	}

drivers/mtd/nand/arasan_nfc.c

@@ -86,7 +86,7 @@ struct arasan_nand_command_format {
 #define ARASAN_NAND_CMD_ADDR_CYCL_MASK		0x70000000
 #define ARASAN_NAND_CMD_ADDR_CYCL_SHIFT		28
 
-#define ARASAN_NAND_MEM_ADDR1_PAGE_MASK		0xFFFF0000
+#define ARASAN_NAND_MEM_ADDR1_PAGE_MASK		0xFFFF
 #define ARASAN_NAND_MEM_ADDR1_COL_MASK		0xFFFF
 #define ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT	16
 #define ARASAN_NAND_MEM_ADDR2_PAGE_MASK		0xFF
@@ -795,10 +795,11 @@ static int arasan_nand_erase(struct arasan_nand_command_format *curr_cmd,
 
 	writel(reg_val, &arasan_nand_base->cmd_reg);
 
-	page = (page_addr << ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT) &
+	page = (page_addr >> ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT) &
 		ARASAN_NAND_MEM_ADDR1_PAGE_MASK;
 	column = page_addr & ARASAN_NAND_MEM_ADDR1_COL_MASK;
-	writel(page | column, &arasan_nand_base->memadr_reg1);
+	writel(column | (page << ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT),
+	       &arasan_nand_base->memadr_reg1);
 
 	reg_val = readl(&arasan_nand_base->memadr_reg2);
 	reg_val &= ~ARASAN_NAND_MEM_ADDR2_PAGE_MASK;

drivers/net/zynq_gem.c

@@ -325,7 +325,8 @@ static int zynq_phy_init(struct udevice *dev)
 	/* Enable only MDIO bus */
 	writel(ZYNQ_GEM_NWCTRL_MDEN_MASK, &regs->nwctrl);
 
-	if (priv->interface != PHY_INTERFACE_MODE_SGMII) {
+	if ((priv->interface != PHY_INTERFACE_MODE_SGMII) &&
+	    (priv->interface != PHY_INTERFACE_MODE_GMII)) {
 		ret = phy_detection(dev);
 		if (ret) {
 			printf("GEM PHY init failed\n");

drivers/watchdog/Kconfig

@@ -1,5 +1,13 @@
 menu "Watchdog Timer Support"
 
+config WATCHDOG
+	bool "Enable U-Boot watchdog reset"
+	help
+	  This option enables U-Boot watchdog support where U-Boot is using
+	  watchdog_reset function to service watchdog device in U-Boot. Enable
+	  this option if you want to service enabled watchdog by U-Boot. Disable
+	  this option if you want U-Boot to start watchdog but never service it.
+
 config HW_WATCHDOG
 	bool
 
@@ -78,4 +86,12 @@ config WDT_ORION
 	   Select this to enable Orion watchdog timer, which can be found on some
 	   Marvell Armada chips.
 
+config WDT_CDNS
+	bool "Cadence watchdog timer support"
+	depends on WDT
+	imply WATCHDOG
+	help
+	   Select this to enable Cadence watchdog timer, which can be found on some
+	   Xilinx Microzed Platform.
+
 endmenu

drivers/watchdog/Makefile

@@ -22,3 +22,4 @@ obj-$(CONFIG_WDT_ASPEED) += ast_wdt.o
 obj-$(CONFIG_WDT_BCM6345) += bcm6345_wdt.o
 obj-$(CONFIG_BCM2835_WDT)       += bcm2835_wdt.o
 obj-$(CONFIG_WDT_ORION) += orion_wdt.o
+obj-$(CONFIG_WDT_CDNS) += cdns_wdt.o

drivers/watchdog/cdns_wdt.c

@@ -0,0 +1,276 @@
+/*
+ * Cadence WDT driver - Used by Xilinx Zynq
+ * Reference: Linux kernel Cadence watchdog driver.
+ *
+ * Author(s):	Shreenidhi Shedi <yesshedi@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <wdt.h>
+#include <clk.h>
+#include <linux/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct cdns_regs {
+	u32 zmr;	/* WD Zero mode register, offset - 0x0 */
+	u32 ccr;	/* Counter Control Register offset - 0x4 */
+	u32 restart;	/* Restart key register, offset - 0x8 */
+	u32 status;	/* Status Register, offset - 0xC */
+};
+
+struct cdns_wdt_priv {
+	bool rst;
+	u32 timeout;
+	void __iomem *reg;
+	struct cdns_regs *regs;
+};
+
+#define CDNS_WDT_DEFAULT_TIMEOUT	10
+
+/* Supports 1 - 516 sec */
+#define CDNS_WDT_MIN_TIMEOUT		1
+#define CDNS_WDT_MAX_TIMEOUT		516
+
+/* Restart key */
+#define CDNS_WDT_RESTART_KEY		0x00001999
+
+/* Counter register access key */
+#define CDNS_WDT_REGISTER_ACCESS_KEY	0x00920000
+
+/* Counter value divisor */
+#define CDNS_WDT_COUNTER_VALUE_DIVISOR	0x1000
+
+/* Clock prescaler value and selection */
+#define CDNS_WDT_PRESCALE_64		64
+#define CDNS_WDT_PRESCALE_512		512
+#define CDNS_WDT_PRESCALE_4096		4096
+#define CDNS_WDT_PRESCALE_SELECT_64	1
+#define CDNS_WDT_PRESCALE_SELECT_512	2
+#define CDNS_WDT_PRESCALE_SELECT_4096	3
+
+/* Input clock frequency */
+#define CDNS_WDT_CLK_75MHZ	75000000
+
+/* Counter maximum value */
+#define CDNS_WDT_COUNTER_MAX	0xFFF
+
+/*********************    Register Map    **********************************/
+
+/*
+ * Zero Mode Register - This register controls how the time out is indicated
+ * and also contains the access code to allow writes to the register (0xABC).
+ */
+#define CDNS_WDT_ZMR_WDEN_MASK	0x00000001 /* Enable the WDT */
+#define CDNS_WDT_ZMR_RSTEN_MASK	0x00000002 /* Enable the reset output */
+#define CDNS_WDT_ZMR_IRQEN_MASK	0x00000004 /* Enable IRQ output */
+#define CDNS_WDT_ZMR_RSTLEN_16	0x00000030 /* Reset pulse of 16 pclk cycles */
+#define CDNS_WDT_ZMR_ZKEY_VAL	0x00ABC000 /* Access key, 0xABC << 12 */
+
+/*
+ * Counter Control register - This register controls how fast the timer runs
+ * and the reset value and also contains the access code to allow writes to
+ * the register.
+ */
+#define CDNS_WDT_CCR_CRV_MASK	0x00003FFC /* Counter reset value */
+
+/* Write access to Registers */
+static inline void cdns_wdt_writereg(u32 *addr, u32 val)
+{
+	writel(val, addr);
+}
+
+/**
+ * cdns_wdt_reset - Reload the watchdog timer (i.e. pat the watchdog).
+ *
+ * @dev: Watchdog device
+ *
+ * Write the restart key value (0x00001999) to the restart register.
+ *
+ * Return: Always 0
+ */
+static int cdns_wdt_reset(struct udevice *dev)
+{
+	struct cdns_wdt_priv *priv = dev_get_priv(dev);
+
+	debug("%s\n", __func__);
+
+	cdns_wdt_writereg(&priv->regs->restart, CDNS_WDT_RESTART_KEY);
+
+	return 0;
+}
+
+/**
+ * cdns_wdt_start - Enable and start the watchdog.
+ *
+ * @dev: Watchdog device
+ * @timeout: Timeout value
+ * @flags: Driver flags
+ *
+ * The counter value is calculated according to the formula:
+ *		count = (timeout * clock) / prescaler + 1.
+ *
+ * The calculated count is divided by 0x1000 to obtain the field value
+ * to write to counter control register.
+ *
+ * Clears the contents of prescaler and counter reset value. Sets the
+ * prescaler to 4096 and the calculated count and access key
+ * to write to CCR Register.
+ *
+ * Sets the WDT (WDEN bit) and either the Reset signal(RSTEN bit)
+ * or Interrupt signal(IRQEN) with a specified cycles and the access
+ * key to write to ZMR Register.
+ *
+ * Return: Upon success 0, failure -1.
+ */
+static int cdns_wdt_start(struct udevice *dev, u64 timeout, ulong flags)
+{
+	ulong clk_f;
+	u32 count, prescaler, ctrl_clksel, data = 0;
+	struct clk clock;
+	struct cdns_wdt_priv *priv = dev_get_priv(dev);
+
+	if (clk_get_by_index(dev, 0, &clock) < 0) {
+		dev_err(dev, "failed to get clock\n");
+		return -1;
+	}
+
+	clk_f = clk_get_rate(&clock);
+	if (IS_ERR_VALUE(clk_f)) {
+		dev_err(dev, "failed to get rate\n");
+		return -1;
+	}
+
+	debug("%s: CLK_FREQ %ld, timeout %lld\n", __func__, clk_f, timeout);
+
+	if ((timeout < CDNS_WDT_MIN_TIMEOUT) ||
+	    (timeout > CDNS_WDT_MAX_TIMEOUT)) {
+		timeout = priv->timeout;
+	}
+
+	if (clk_f <= CDNS_WDT_CLK_75MHZ) {
+		prescaler = CDNS_WDT_PRESCALE_512;
+		ctrl_clksel = CDNS_WDT_PRESCALE_SELECT_512;
+	} else {
+		prescaler = CDNS_WDT_PRESCALE_4096;
+		ctrl_clksel = CDNS_WDT_PRESCALE_SELECT_4096;
+	}
+
+	/*
+	 * Counter value divisor to obtain the value of
+	 * counter reset to be written to control register.
+	 */
+	count = (timeout * (clk_f / prescaler)) /
+		CDNS_WDT_COUNTER_VALUE_DIVISOR + 1;
+
+	if (count > CDNS_WDT_COUNTER_MAX)
+		count = CDNS_WDT_COUNTER_MAX;
+
+	cdns_wdt_writereg(&priv->regs->zmr, CDNS_WDT_ZMR_ZKEY_VAL);
+
+	count = (count << 2) & CDNS_WDT_CCR_CRV_MASK;
+
+	/* Write counter access key first to be able write to register */
+	data = count | CDNS_WDT_REGISTER_ACCESS_KEY | ctrl_clksel;
+	cdns_wdt_writereg(&priv->regs->ccr, data);
+
+	data = CDNS_WDT_ZMR_WDEN_MASK | CDNS_WDT_ZMR_RSTLEN_16 |
+		CDNS_WDT_ZMR_ZKEY_VAL;
+
+	/* Reset on timeout if specified in device tree. */
+	if (priv->rst) {
+		data |= CDNS_WDT_ZMR_RSTEN_MASK;
+		data &= ~CDNS_WDT_ZMR_IRQEN_MASK;
+	} else {
+		data &= ~CDNS_WDT_ZMR_RSTEN_MASK;
+		data |= CDNS_WDT_ZMR_IRQEN_MASK;
+	}
+
+	cdns_wdt_writereg(&priv->regs->zmr, data);
+	cdns_wdt_writereg(&priv->regs->restart, CDNS_WDT_RESTART_KEY);
+
+	return 0;
+}
+
+/**
+ * cdns_wdt_stop - Stop the watchdog.
+ *
+ * @dev: Watchdog device
+ *
+ * Read the contents of the ZMR register, clear the WDEN bit in the register
+ * and set the access key for successful write.
+ *
+ * Return: Always 0
+ */
+static int cdns_wdt_stop(struct udevice *dev)
+{
+	struct cdns_wdt_priv *priv = dev_get_priv(dev);
+
+	cdns_wdt_writereg(&priv->regs->zmr,
+			  CDNS_WDT_ZMR_ZKEY_VAL & (~CDNS_WDT_ZMR_WDEN_MASK));
+
+	return 0;
+}
+
+/**
+ * cdns_wdt_probe - Probe call for the device.
+ *
+ * @dev: Handle to the udevice structure.
+ *
+ * Return: Always 0.
+ */
+static int cdns_wdt_probe(struct udevice *dev)
+{
+	struct cdns_wdt_priv *priv = dev_get_priv(dev);
+
+	debug("%s: Probing wdt%u\n", __func__, dev->seq);
+
+	priv->reg = ioremap((u32)priv->regs, sizeof(struct cdns_regs));
+
+	cdns_wdt_stop(dev);
+
+	return 0;
+}
+
+static int cdns_wdt_ofdata_to_platdata(struct udevice *dev)
+{
+	int node = dev_of_offset(dev);
+	struct cdns_wdt_priv *priv = dev_get_priv(dev);
+
+	priv->regs = devfdt_get_addr_ptr(dev);
+	if (IS_ERR(priv->regs))
+		return PTR_ERR(priv->regs);
+
+	priv->timeout = fdtdec_get_int(gd->fdt_blob, node, "timeout-sec",
+				       CDNS_WDT_DEFAULT_TIMEOUT);
+
+	priv->rst = fdtdec_get_bool(gd->fdt_blob, node, "reset-on-timeout");
+
+	debug("%s: timeout %d, reset %d\n", __func__, priv->timeout, priv->rst);
+
+	return 0;
+}
+
+static const struct wdt_ops cdns_wdt_ops = {
+	.start = cdns_wdt_start,
+	.reset = cdns_wdt_reset,
+	.stop = cdns_wdt_stop,
+};
+
+static const struct udevice_id cdns_wdt_ids[] = {
+	{ .compatible = "cdns,wdt-r1p2" },
+	{}
+};
+
+U_BOOT_DRIVER(cdns_wdt) = {
+	.name = "cdns_wdt",
+	.id = UCLASS_WDT,
+	.of_match = cdns_wdt_ids,
+	.probe = cdns_wdt_probe,
+	.priv_auto_alloc_size = sizeof(struct cdns_wdt_priv),
+	.ofdata_to_platdata = cdns_wdt_ofdata_to_platdata,
+	.ops = &cdns_wdt_ops,
+};

include/command.h

@@ -111,6 +111,8 @@ extern int common_diskboot(cmd_tbl_t *cmdtp, const char *intf, int argc,
 extern int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
 extern int do_poweroff(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
 
+extern unsigned long do_go_exec(ulong (*entry)(int, char * const []), int argc,
+				char * const argv[]);
 /*
  * Error codes that commands return to cmd_process(). We use the standard 0
  * and 1 for success and failure, but add one more case - failure with a

include/configs/xilinx_zynqmp.h

@@ -21,7 +21,9 @@
 #define GICC_BASE	0xF9020000
 
 #define CONFIG_SYS_ALT_MEMTEST
-#define CONFIG_SYS_MEMTEST_SCRATCH	0xfffc0000
+#ifndef CONFIG_SYS_MEMTEST_SCRATCH
+# define CONFIG_SYS_MEMTEST_SCRATCH	0x10800000
+#endif
 
 #ifndef CONFIG_NR_DRAM_BANKS
 # define CONFIG_NR_DRAM_BANKS		2

include/configs/xilinx_zynqmp_ep.h

@@ -1,24 +0,0 @@
-/*
- * Configuration for Xilinx ZynqMP emulation platforms
- *
- * (C) Copyright 2014 - 2015 Xilinx, Inc.
- * Michal Simek <michal.simek@xilinx.com>
- * Siva Durga Prasad Paladugu <sivadur@xilinx.com>
- *
- * Based on Configuration for Versatile Express
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __CONFIG_ZYNQMP_EP_H
-#define __CONFIG_ZYNQMP_EP_H
-
-#define CONFIG_ZYNQ_EEPROM
-#define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR, \
-				 ZYNQMP_USB1_XHCI_BASEADDR}
-
-#define COUNTER_FREQUENCY	4000000
-
-#include <configs/xilinx_zynqmp.h>
-
-#endif /* __CONFIG_ZYNQMP_EP_H */

include/configs/xilinx_zynqmp_mini.h

@@ -11,6 +11,8 @@
 #ifndef __CONFIG_ZYNQMP_MINI_H
 #define __CONFIG_ZYNQMP_MINI_H
 
+#define CONFIG_SYS_MEMTEST_SCRATCH     0xfffc0000
+
 #include <configs/xilinx_zynqmp.h>
 
 /* Undef unneeded configs */

tools/zynqimage.c

@@ -147,6 +147,12 @@ static int zynqimage_verify_header(unsigned char *ptr, int image_size,
 	if (image_size < sizeof(struct zynq_header))
 		return -1;
 
+	if (zynqhdr->__reserved1 != 0)
+		return -1;
+
+	if (zynqhdr->__reserved2 != 0)
+		return -1;
+
 	if (zynqhdr->width_detection != HEADER_WIDTHDETECTION)
 		return -1;
 	if (zynqhdr->image_identifier != HEADER_IMAGEIDENTIFIER)

tools/zynqmpimage.c

@@ -178,7 +178,7 @@ static void zynqmpimage_print_header(const void *ptr)
 	struct zynqmp_header *zynqhdr = (struct zynqmp_header *)ptr;
 	int i;
 
-	printf("Image Type   : Xilinx Zynq Boot Image support\n");
+	printf("Image Type   : Xilinx ZynqMP Boot Image support\n");
 	printf("Image Offset : 0x%08x\n", le32_to_cpu(zynqhdr->image_offset));
 	printf("Image Size   : %lu bytes (%lu bytes packed)\n",
 	       (unsigned long)le32_to_cpu(zynqhdr->image_size),