mirror of
https://github.com/Fishwaldo/u-boot.git
synced 2025-03-18 13:11:31 +00:00
PCI: layerscape: Fix assigning wrong address to LS2088A pcie cfg1 space
This bug is brought by the commit 3d8553f0a3
(pci: layerscape: add
LS2088A series SoC pcie support), which only updated cfg_res.start
and did not update the .end field. This causes fdt_resource_size()
getting wrong value when calculate the cfg1 space address.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
[YS: Revise subject and commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
This commit is contained in:
parent
563ac65a1a
commit
89d8e1313f
1 changed files with 3 additions and 0 deletions
|
@ -478,6 +478,7 @@ static int ls_pcie_probe(struct udevice *dev)
|
|||
bool ep_mode;
|
||||
uint svr;
|
||||
int ret;
|
||||
fdt_size_t cfg_size;
|
||||
|
||||
pcie->bus = dev;
|
||||
|
||||
|
@ -539,8 +540,10 @@ static int ls_pcie_probe(struct udevice *dev)
|
|||
if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
|
||||
svr == SVR_LS2048A || svr == SVR_LS2044A ||
|
||||
svr == SVR_LS2081A || svr == SVR_LS2041A) {
|
||||
cfg_size = fdt_resource_size(&pcie->cfg_res);
|
||||
pcie->cfg_res.start = LS2088A_PCIE1_PHYS_ADDR +
|
||||
LS2088A_PCIE_PHYS_SIZE * pcie->idx;
|
||||
pcie->cfg_res.end = pcie->cfg_res.start + cfg_size;
|
||||
pcie->ctrl = pcie->lut + 0x40000;
|
||||
}
|
||||
|
||||
|
|
Loading…
Add table
Reference in a new issue