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ARM: keystone2: PLL: Enable glitch free initialization sequence
Update the PLL initialization sequence to avoid glitches while programming. User guide for the same is available at[1]. [1] http://www.ti.com/lit/ug/sprugv2h/sprugv2h.pdf Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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1 changed files with 8 additions and 8 deletions
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@ -163,15 +163,15 @@ void configure_secondary_pll(const struct pll_init_data *data)
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{
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int pllod = data->pll_od - 1;
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/* Enable Glitch free bypass for ARM PLL */
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if (cpu_is_k2hk() && data->pll == TETRIS_PLL)
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clrbits_le32(KS2_MISC_CTRL, MISC_CTL1_ARM_PLL_EN);
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/* Enable Bypass mode */
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setbits_le32(keystone_pll_regs[data->pll].reg1, CFG_PLLCTL1_ENSAT_MASK);
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setbits_le32(keystone_pll_regs[data->pll].reg0,
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CFG_PLLCTL0_BYPASS_MASK);
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/* Enable Glitch free bypass for ARM PLL */
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if (cpu_is_k2hk() && data->pll == TETRIS_PLL)
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clrbits_le32(KS2_MISC_CTRL, MISC_CTL1_ARM_PLL_EN);
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configure_mult_div(data);
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/* Program Output Divider */
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@ -189,10 +189,6 @@ void configure_secondary_pll(const struct pll_init_data *data)
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if (data->pll == PASS_PLL && cpu_is_k2hk())
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pll_pa_clk_sel();
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/* Select the Output of ARM PLL as input to ARM */
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if (data->pll == TETRIS_PLL)
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setbits_le32(KS2_MISC_CTRL, MISC_CTL1_ARM_PLL_EN);
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clrbits_le32(keystone_pll_regs[data->pll].reg1, CFG_PLLCTL1_RST_MASK);
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/* Wait for 500 * REFCLK cucles * (PLLD + 1) */
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sdelay(105000);
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@ -200,6 +196,10 @@ void configure_secondary_pll(const struct pll_init_data *data)
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/* Switch to PLL mode */
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clrbits_le32(keystone_pll_regs[data->pll].reg0,
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CFG_PLLCTL0_BYPASS_MASK);
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/* Select the Output of ARM PLL as input to ARM */
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if (cpu_is_k2hk() && data->pll == TETRIS_PLL)
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setbits_le32(KS2_MISC_CTRL, MISC_CTL1_ARM_PLL_EN);
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}
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void init_pll(const struct pll_init_data *data)
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