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ARM: keystone2: PLL: Enable glitch free initialization sequence

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Update the PLL initialization sequence to avoid glitches while
programming. User guide for the same is available at[1].

[1] http://www.ti.com/lit/ug/sprugv2h/sprugv2h.pdf

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Lokesh Vutla 2016-11-03 15:32:51 +05:30 • committed by Tom Rini
parent 06d43c808d
commit 8b01ebd812
1 changed files with 8 additions and 8 deletions
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16
arch/arm/mach-keystone/clock.c
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@ -163,15 +163,15 @@ void configure_secondary_pll(const struct pll_init_data *data)
{ {
int pllod = data->pll_od - 1; int pllod = data->pll_od - 1;
/* Enable Glitch free bypass for ARM PLL */
if (cpu_is_k2hk() && data->pll == TETRIS_PLL)
clrbits_le32(KS2_MISC_CTRL, MISC_CTL1_ARM_PLL_EN);
/* Enable Bypass mode */ /* Enable Bypass mode */
setbits_le32(keystone_pll_regs[data->pll].reg1, CFG_PLLCTL1_ENSAT_MASK); setbits_le32(keystone_pll_regs[data->pll].reg1, CFG_PLLCTL1_ENSAT_MASK);
setbits_le32(keystone_pll_regs[data->pll].reg0, setbits_le32(keystone_pll_regs[data->pll].reg0,
CFG_PLLCTL0_BYPASS_MASK); CFG_PLLCTL0_BYPASS_MASK);
/* Enable Glitch free bypass for ARM PLL */
if (cpu_is_k2hk() && data->pll == TETRIS_PLL)
clrbits_le32(KS2_MISC_CTRL, MISC_CTL1_ARM_PLL_EN);
configure_mult_div(data); configure_mult_div(data);
/* Program Output Divider */ /* Program Output Divider */
@ -189,10 +189,6 @@ void configure_secondary_pll(const struct pll_init_data *data)
if (data->pll == PASS_PLL && cpu_is_k2hk()) if (data->pll == PASS_PLL && cpu_is_k2hk())
pll_pa_clk_sel(); pll_pa_clk_sel();
/* Select the Output of ARM PLL as input to ARM */
if (data->pll == TETRIS_PLL)
setbits_le32(KS2_MISC_CTRL, MISC_CTL1_ARM_PLL_EN);
clrbits_le32(keystone_pll_regs[data->pll].reg1, CFG_PLLCTL1_RST_MASK); clrbits_le32(keystone_pll_regs[data->pll].reg1, CFG_PLLCTL1_RST_MASK);
/* Wait for 500 * REFCLK cucles * (PLLD + 1) */ /* Wait for 500 * REFCLK cucles * (PLLD + 1) */
sdelay(105000); sdelay(105000);
@ -200,6 +196,10 @@ void configure_secondary_pll(const struct pll_init_data *data)
/* Switch to PLL mode */ /* Switch to PLL mode */
clrbits_le32(keystone_pll_regs[data->pll].reg0, clrbits_le32(keystone_pll_regs[data->pll].reg0,
CFG_PLLCTL0_BYPASS_MASK); CFG_PLLCTL0_BYPASS_MASK);
/* Select the Output of ARM PLL as input to ARM */
if (cpu_is_k2hk() && data->pll == TETRIS_PLL)
setbits_le32(KS2_MISC_CTRL, MISC_CTL1_ARM_PLL_EN);
} }
void init_pll(const struct pll_init_data *data) void init_pll(const struct pll_init_data *data)