mirror of
https://github.com/Fishwaldo/u-boot.git
synced 2025-03-21 14:41:31 +00:00
ddr: altera: Clean up rw_mgr_*_vfifo() part 2
Pluck out all this VFIFO value counting, which turns out to be completely unused. Thus, remove it to simplify the code. Signed-off-by: Marek Vasut <marex@denx.de>
This commit is contained in:
Marek Vasut
parent
60bb8a8a7e
commit
8c887b6ec3
1 changed files with 41 additions and 51 deletions
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@ -1289,38 +1289,35 @@ static uint32_t rw_mgr_mem_calibrate_read_test_all_ranks(uint32_t group,
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/**
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* rw_mgr_incr_vfifo() - Increase VFIFO value
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* @grp: Read/Write group
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* @v: VFIFO value
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*
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* Increase VFIFO value.
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*/
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static void rw_mgr_incr_vfifo(const u32 grp, u32 *v)
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static void rw_mgr_incr_vfifo(const u32 grp)
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{
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writel(grp, &phy_mgr_cmd->inc_vfifo_hard_phy);
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(*v)++;
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}
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/**
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* rw_mgr_decr_vfifo() - Decrease VFIFO value
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* @grp: Read/Write group
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* @v: VFIFO value
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*
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* Decrease VFIFO value.
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*/
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static void rw_mgr_decr_vfifo(const u32 grp, u32 *v)
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static void rw_mgr_decr_vfifo(const u32 grp)
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{
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u32 i;
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for (i = 0; i < VFIFO_SIZE - 1; i++)
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rw_mgr_incr_vfifo(grp, v);
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rw_mgr_incr_vfifo(grp);
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}
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static int find_vfifo_read(uint32_t grp, uint32_t *bit_chk)
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{
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uint32_t v;
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uint32_t v;
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uint32_t fail_cnt = 0;
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uint32_t test_status;
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for (v = 0; v < VFIFO_SIZE; ) {
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for (v = 0; v < VFIFO_SIZE; v++) {
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debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: vfifo %u\n",
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__func__, __LINE__, v);
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test_status = rw_mgr_mem_calibrate_read_test_all_ranks
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@ -1333,7 +1330,7 @@ static int find_vfifo_read(uint32_t grp, uint32_t *bit_chk)
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}
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/* fiddle with FIFO */
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rw_mgr_incr_vfifo(grp, &v);
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rw_mgr_incr_vfifo(grp);
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}
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if (v >= VFIFO_SIZE) {
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@ -1350,14 +1347,13 @@ static int find_vfifo_read(uint32_t grp, uint32_t *bit_chk)
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* sdr_find_phase() - Find DQS enable phase
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* @working: If 1, look for working phase, if 0, look for non-working phase
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* @grp: Read/Write group
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* @v: VFIFO value
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* @work: Working window position
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* @i: Iterator
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* @p: DQS Phase Iterator
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*
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* Find working or non-working DQS enable phase setting.
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*/
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static int sdr_find_phase(int working, const u32 grp, u32 *v, u32 *work,
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static int sdr_find_phase(int working, const u32 grp, u32 *work,
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u32 *i, u32 *p)
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{
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u32 ret, bit_chk;
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@ -1383,7 +1379,7 @@ static int sdr_find_phase(int working, const u32 grp, u32 *v, u32 *work,
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if (*p > IO_DQS_EN_PHASE_MAX) {
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/* Fiddle with FIFO. */
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rw_mgr_incr_vfifo(grp, v);
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rw_mgr_incr_vfifo(grp);
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if (!working)
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*p = 0;
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}
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@ -1396,14 +1392,13 @@ static int sdr_find_phase(int working, const u32 grp, u32 *v, u32 *work,
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* sdr_working_phase() - Find working DQS enable phase
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* @grp: Read/Write group
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* @work_bgn: Working window start position
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* @v: VFIFO value
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* @d: dtaps output value
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* @p: DQS Phase Iterator
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* @i: Iterator
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*
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* Find working DQS enable phase setting.
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*/
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static int sdr_working_phase(const u32 grp, u32 *work_bgn, u32 *v, u32 *d,
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static int sdr_working_phase(const u32 grp, u32 *work_bgn, u32 *d,
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u32 *p, u32 *i)
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{
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const u32 dtaps_per_ptap = IO_DELAY_PER_OPA_TAP /
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@ -1415,7 +1410,7 @@ static int sdr_working_phase(const u32 grp, u32 *work_bgn, u32 *v, u32 *d,
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for (*d = 0; *d <= dtaps_per_ptap; (*d)++) {
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*i = 0;
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scc_mgr_set_dqs_en_delay_all_ranks(grp, *d);
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ret = sdr_find_phase(1, grp, v, work_bgn, i, p);
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ret = sdr_find_phase(1, grp, work_bgn, i, p);
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if (!ret)
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return 0;
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*work_bgn += IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
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@ -1431,12 +1426,11 @@ static int sdr_working_phase(const u32 grp, u32 *work_bgn, u32 *v, u32 *d,
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* sdr_backup_phase() - Find DQS enable backup phase
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* @grp: Read/Write group
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* @work_bgn: Working window start position
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* @v: VFIFO value
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* @p: DQS Phase Iterator
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*
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* Find DQS enable backup phase setting.
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*/
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static void sdr_backup_phase(const u32 grp, u32 *work_bgn, u32 *v, u32 *p)
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static void sdr_backup_phase(const u32 grp, u32 *work_bgn, u32 *p)
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{
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u32 tmp_delay, bit_chk, d;
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int ret;
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@ -1444,7 +1438,7 @@ static void sdr_backup_phase(const u32 grp, u32 *work_bgn, u32 *v, u32 *p)
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/* Special case code for backing up a phase */
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if (*p == 0) {
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*p = IO_DQS_EN_PHASE_MAX;
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rw_mgr_decr_vfifo(grp, v);
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rw_mgr_decr_vfifo(grp);
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} else {
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(*p)--;
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}
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@ -1468,7 +1462,7 @@ static void sdr_backup_phase(const u32 grp, u32 *work_bgn, u32 *v, u32 *p)
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(*p)++;
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if (*p > IO_DQS_EN_PHASE_MAX) {
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*p = 0;
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rw_mgr_incr_vfifo(grp, v);
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rw_mgr_incr_vfifo(grp);
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}
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scc_mgr_set_dqs_en_delay_all_ranks(grp, 0);
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@ -1478,14 +1472,12 @@ static void sdr_backup_phase(const u32 grp, u32 *work_bgn, u32 *v, u32 *p)
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* sdr_nonworking_phase() - Find non-working DQS enable phase
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* @grp: Read/Write group
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* @work_end: Working window end position
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* @v: VFIFO value
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* @p: DQS Phase Iterator
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* @i: Iterator
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*
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* Find non-working DQS enable phase setting.
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*/
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static int sdr_nonworking_phase(const u32 grp, u32 *work_end, u32 *v,
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u32 *p, u32 *i)
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static int sdr_nonworking_phase(const u32 grp, u32 *work_end, u32 *p, u32 *i)
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{
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int ret;
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@ -1494,10 +1486,10 @@ static int sdr_nonworking_phase(const u32 grp, u32 *work_end, u32 *v,
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if (*p > IO_DQS_EN_PHASE_MAX) {
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/* Fiddle with FIFO. */
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*p = 0;
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rw_mgr_incr_vfifo(grp, v);
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rw_mgr_incr_vfifo(grp);
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}
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ret = sdr_find_phase(0, grp, v, work_end, i, p);
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ret = sdr_find_phase(0, grp, work_end, i, p);
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if (ret) {
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/* Cannot see edge of failing read. */
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debug_cond(DLEVEL == 2, "%s:%d: end: failed\n",
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@ -1512,14 +1504,13 @@ static int sdr_nonworking_phase(const u32 grp, u32 *work_end, u32 *v,
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* @grp: Read/Write group
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* @work_bgn: First working settings
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* @work_end: Last working settings
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* @val: VFIFO value
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*
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* Find center of the working DQS enable window.
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*/
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static int sdr_find_window_center(const u32 grp, const u32 work_bgn,
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const u32 work_end, const u32 val)
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const u32 work_end)
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{
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u32 bit_chk, work_mid, v = val;
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u32 bit_chk, work_mid;
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int tmp_delay = 0;
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int i, p, d;
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@ -1556,19 +1547,18 @@ static int sdr_find_window_center(const u32 grp, const u32 work_bgn,
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* because the largest possible margin in 1 VFIFO cycle.
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*/
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for (i = 0; i < VFIFO_SIZE; i++) {
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debug_cond(DLEVEL == 2, "find_dqs_en_phase: center: vfifo=%u\n",
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v);
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debug_cond(DLEVEL == 2, "find_dqs_en_phase: center\n");
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if (rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
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PASS_ONE_BIT,
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&bit_chk, 0)) {
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debug_cond(DLEVEL == 2,
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"%s:%d center: found: vfifo=%u ptap=%u dtap=%u\n",
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__func__, __LINE__, v, p, d);
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"%s:%d center: found: ptap=%u dtap=%u\n",
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__func__, __LINE__, p, d);
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return 0;
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}
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/* Fiddle with FIFO. */
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rw_mgr_incr_vfifo(grp, &v);
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rw_mgr_incr_vfifo(grp);
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}
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debug_cond(DLEVEL == 2, "%s:%d center: failed.\n",
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@ -1579,7 +1569,7 @@ static int sdr_find_window_center(const u32 grp, const u32 work_bgn,
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/* find a good dqs enable to use */
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static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp)
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{
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uint32_t v, d, p, i;
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uint32_t d, p, i;
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uint32_t bit_chk;
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uint32_t dtaps_per_ptap;
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uint32_t work_bgn, work_end;
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@ -1598,12 +1588,12 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp)
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/* ********************************************************* */
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/* * Step 1 : First push vfifo until we get a failing read * */
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v = find_vfifo_read(grp, &bit_chk);
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find_vfifo_read(grp, &bit_chk);
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/* ******************************************************** */
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/* * step 2: find first working phase, increment in ptaps * */
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work_bgn = 0;
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if (sdr_working_phase(grp, &work_bgn, &v, &d, &p, &i))
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if (sdr_working_phase(grp, &work_bgn, &d, &p, &i))
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return 0;
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work_end = work_bgn;
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@ -1618,12 +1608,12 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp)
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/* * step 3a: if we have room, back off by one and
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increment in dtaps * */
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sdr_backup_phase(grp, &work_bgn, &v, &p);
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sdr_backup_phase(grp, &work_bgn, &p);
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/* ********************************************************* */
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/* * step 4a: go forward from working phase to non working
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phase, increment in ptaps * */
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if (sdr_nonworking_phase(grp, &work_end, &v, &p, &i))
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if (sdr_nonworking_phase(grp, &work_end, &p, &i))
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return 0;
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/* ********************************************************* */
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@ -1632,7 +1622,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp)
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/* Special case code for backing up a phase */
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if (p == 0) {
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p = IO_DQS_EN_PHASE_MAX;
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rw_mgr_decr_vfifo(grp, &v);
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rw_mgr_decr_vfifo(grp);
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} else {
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p = p - 1;
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}
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@ -1644,16 +1634,16 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp)
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the if/else loop to share code */
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d = 0;
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debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: v/p: \
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vfifo=%u ptap=%u\n", __func__, __LINE__,
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v, p);
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debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: p: \
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ptap=%u\n", __func__, __LINE__,
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p);
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} else {
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/* ******************************************************* */
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/* * step 3-5b: Find the right edge of the window using
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delay taps * */
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debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase:vfifo=%u \
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debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: \
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ptap=%u dtap=%u bgn=%u\n", __func__, __LINE__,
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v, p, d, work_bgn);
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p, d, work_bgn);
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work_end = work_bgn;
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}
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@ -1676,9 +1666,9 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp)
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if (d != 0)
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work_end -= IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
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debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: v/p/d: vfifo=%u \
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debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: p/d: \
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ptap=%u dtap=%u end=%u\n", __func__, __LINE__,
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v, p, d-1, work_end);
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p, d-1, work_end);
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if (work_end < work_bgn) {
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/* nil range */
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@ -1703,15 +1693,15 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp)
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/* Special case code for backing up a phase */
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if (p == 0) {
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p = IO_DQS_EN_PHASE_MAX;
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rw_mgr_decr_vfifo(grp, &v);
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rw_mgr_decr_vfifo(grp);
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debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: backedup \
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cycle/phase: v=%u p=%u\n", __func__, __LINE__,
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v, p);
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cycle/phase: p=%u\n", __func__, __LINE__,
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p);
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} else {
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p = p - 1;
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debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: backedup \
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phase only: v=%u p=%u", __func__, __LINE__,
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v, p);
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phase only: p=%u", __func__, __LINE__,
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p);
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}
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scc_mgr_set_dqs_en_phase_all_ranks(grp, p);
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@ -1778,7 +1768,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp)
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/* ******************************************** */
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/* * step 6: Find the centre of the window * */
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if (sdr_find_window_centre(grp, work_bgn, work_end, v))
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if (sdr_find_window_centre(grp, work_bgn, work_end))
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return 0; /* FIXME: Old code, return 0 means failure :-( */
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return 1;
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