mirror of
https://github.com/Fishwaldo/u-boot.git
synced 2025-03-18 13:11:31 +00:00
fsl: Clean up printing of PCI boot info
Previously boards used a variety of indentations, newline styles, and colon styles for the PCI information that is printed on bootup. This patch unifies the style to look like: ... NAND: 1024 MiB PCIE1: connected as Root Complex Scanning PCI bus 01 04 01 8086 1010 0200 00 04 01 8086 1010 0200 00 03 00 10b5 8112 0604 00 02 01 10b5 8518 0604 00 02 02 10b5 8518 0604 00 08 00 1957 0040 0b20 00 07 00 10b5 8518 0604 00 09 00 10b5 8112 0604 00 07 01 10b5 8518 0604 00 07 02 10b5 8518 0604 00 06 00 10b5 8518 0604 00 02 03 10b5 8518 0604 00 01 00 10b5 8518 0604 00 PCIE1: Bus 00 - 0b PCIE2: connected as Root Complex Scanning PCI bus 0d 0d 00 1957 0040 0b20 00 PCIE2: Bus 0c - 0d In: serial ... Signed-off-by: Peter Tyser <ptyser@xes-inc.com> CC: wd@denx.de CC: sr@denx.de CC: galak@kernel.crashing.org
This commit is contained in:
parent
a72dbae2cc
commit
8ca78f2c89
24 changed files with 147 additions and 147 deletions
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@ -218,14 +218,14 @@ void pci_init_board(void)
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pcie1_hose.region_count = 1;
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#endif
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printf (" PCIE1 connected to Slot as %s (base addr %lx)\n",
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printf ("PCIE1: connected to Slot as %s (base addr %lx)\n",
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pcie_ep ? "Endpoint" : "Root Complex",
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pci_info[num].regs);
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first_free_busno = fsl_pci_init_port(&pci_info[num++],
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&pcie1_hose, first_free_busno);
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} else {
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printf (" PCIE1: disabled\n");
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printf("PCIE1: disabled\n");
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}
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puts("\n");
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@ -242,7 +242,7 @@ void pci_init_board(void)
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if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
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SET_STD_PCI_INFO(pci_info[num], 1);
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pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs);
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printf ("\n PCI1: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
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printf("PCI1: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
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(pci_32) ? 32 : 64,
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(pci_speed == 33333000) ? "33" :
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(pci_speed == 66666000) ? "66" : "unknown",
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@ -254,7 +254,7 @@ void pci_init_board(void)
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first_free_busno = fsl_pci_init_port(&pci_info[num++],
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&pci1_hose, first_free_busno);
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} else {
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printf (" PCI: disabled\n");
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printf("PCI1: disabled\n");
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}
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puts("\n");
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@ -267,11 +267,11 @@ void pci_init_board(void)
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SET_STD_PCI_INFO(pci_info[num], 2);
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pci_agent = fsl_setup_hose(&pci2_hose, pci_info[num].regs);
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puts (" PCI2\n");
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puts("PCI2\n");
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first_free_busno = fsl_pci_init_port(&pci_info[num++],
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&pci1_hose, first_free_busno);
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} else {
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printf (" PCI2: disabled\n");
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printf("PCI2: disabled\n");
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}
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puts("\n");
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#else
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@ -68,13 +68,13 @@ void pci_init_board(void)
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LAW_TRGT_IF_PCIE_1);
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SET_STD_PCIE_INFO(pci_info[num], 1);
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pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
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printf(" PCIE1 connected to Slot 1 as %s (base addr %lx)\n",
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printf("PCIE1: connected to Slot 1 as %s (base addr %lx)\n",
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pcie_ep ? "End Point" : "Root Complex",
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pci_info[num].regs);
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first_free_busno = fsl_pci_init_port(&pci_info[num++],
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&pcie1_hose, first_free_busno);
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} else {
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printf (" PCIE1: disabled\n");
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printf("PCIE1: disabled\n");
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}
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#else
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setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_PCIE1); /* disable */
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@ -90,13 +90,13 @@ void pci_init_board(void)
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LAW_TRGT_IF_PCIE_2);
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SET_STD_PCIE_INFO(pci_info[num], 2);
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pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
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printf(" PCIE2 connected to Slot 3 as %s (base addr %lx)\n",
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printf("PCIE2: connected to Slot 3 as %s (base addr %lx)\n",
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pcie_ep ? "End Point" : "Root Complex",
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pci_info[num].regs);
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first_free_busno = fsl_pci_init_port(&pci_info[num++],
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&pcie2_hose, first_free_busno);
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} else {
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printf (" PCIE2: disabled\n");
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printf("PCIE2: disabled\n");
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}
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#else
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setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_PCIE2); /* disable */
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@ -112,13 +112,13 @@ void pci_init_board(void)
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LAW_TRGT_IF_PCIE_3);
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SET_STD_PCIE_INFO(pci_info[num], 3);
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pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs);
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printf(" PCIE3 connected to Slot 2 as %s (base addr %lx)\n",
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printf("PCIE3: connected to Slot 2 as %s (base addr %lx)\n",
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pcie_ep ? "End Point" : "Root Complex",
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pci_info[num].regs);
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first_free_busno = fsl_pci_init_port(&pci_info[num++],
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&pcie3_hose, first_free_busno);
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} else {
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printf (" PCIE3: disabled\n");
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printf("PCIE3: disabled\n");
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}
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#else
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setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_PCIE3); /* disable */
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@ -134,13 +134,13 @@ void pci_init_board(void)
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LAW_TRGT_IF_PCIE_4);
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SET_STD_PCIE_INFO(pci_info[num], 4);
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pcie_ep = fsl_setup_hose(&pcie4_hose, pci_info[num].regs);
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printf(" PCIE4 connected to as %s (base addr %lx)\n",
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printf("PCIE4: connected to as %s (base addr %lx)\n",
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pcie_ep ? "End Point" : "Root Complex",
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pci_info[num].regs);
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first_free_busno = fsl_pci_init_port(&pci_info[num++],
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&pcie4_hose, first_free_busno);
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} else {
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printf (" PCIE4: disabled\n");
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printf("PCIE4: disabled\n");
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}
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#else
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setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_PCIE4); /* disable */
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@ -229,13 +229,13 @@ void pci_init_board(void)
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LAW_TRGT_IF_PCIE_3);
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SET_STD_PCIE_INFO(pci_info[num], 3);
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pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs);
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printf (" PCIE3 connected to Slot3 as %s (base address %lx)\n",
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printf("PCIE3: connected to Slot3 as %s (base address %lx)\n",
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pcie_ep ? "Endpoint" : "Root Complex",
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pci_info[num].regs);
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first_free_busno = fsl_pci_init_port(&pci_info[num++],
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&pcie3_hose, first_free_busno);
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} else {
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printf (" PCIE3: disabled\n");
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printf("PCIE3: disabled\n");
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}
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puts("\n");
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@ -253,13 +253,13 @@ void pci_init_board(void)
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LAW_TRGT_IF_PCIE_1);
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SET_STD_PCIE_INFO(pci_info[num], 1);
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pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
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printf (" PCIE1 connected to Slot1 as %s (base address %lx)\n",
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printf("PCIE1: connected to Slot1 as %s (base address %lx)\n",
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pcie_ep ? "Endpoint" : "Root Complex",
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pci_info[num].regs);
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first_free_busno = fsl_pci_init_port(&pci_info[num++],
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&pcie1_hose, first_free_busno);
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} else {
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printf (" PCIE1: disabled\n");
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printf("PCIE1: disabled\n");
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}
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puts("\n");
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@ -277,13 +277,13 @@ void pci_init_board(void)
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LAW_TRGT_IF_PCIE_2);
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SET_STD_PCIE_INFO(pci_info[num], 2);
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pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
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printf (" PCIE2 connected to Slot 2 as %s (base address %lx)\n",
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printf("PCIE2: connected to Slot 2 as %s (base address %lx)\n",
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pcie_ep ? "Endpoint" : "Root Complex",
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pci_info[num].regs);
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first_free_busno = fsl_pci_init_port(&pci_info[num++],
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&pcie2_hose, first_free_busno);
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} else {
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printf (" PCIE2: disabled\n");
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printf("PCIE2: disabled\n");
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}
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puts("\n");
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@ -304,7 +304,7 @@ void pci_init_board(void)
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LAW_TRGT_IF_PCI);
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SET_STD_PCI_INFO(pci_info[num], 1);
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pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs);
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printf ("\n PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
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printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
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(pci_32) ? 32 : 64,
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(pci_speed == 33333000) ? "33" :
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(pci_speed == 66666000) ? "66" : "unknown",
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@ -316,7 +316,7 @@ void pci_init_board(void)
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first_free_busno = fsl_pci_init_port(&pci_info[num++],
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&pci1_hose, first_free_busno);
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} else {
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printf (" PCI: disabled\n");
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printf("PCI: disabled\n");
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}
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puts("\n");
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@ -47,10 +47,10 @@ int checkboard (void)
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puts("Board: ADS\n");
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#ifdef CONFIG_PCI
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printf(" PCI1: 32 bit, %d MHz (compiled)\n",
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printf("PCI1: 32 bit, %d MHz (compiled)\n",
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CONFIG_SYS_CLK_FREQ / 1000000);
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#else
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printf(" PCI1: disabled\n");
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printf("PCI1: disabled\n");
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#endif
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/*
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@ -221,17 +221,17 @@ int checkboard (void)
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MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
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MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
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printf (" PCI1: %d bit, %s MHz, %s\n",
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printf("PCI1: %d bit, %s MHz, %s\n",
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(pci1_32) ? 32 : 64,
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(pci1_speed == 33000000) ? "33" :
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(pci1_speed == 66000000) ? "66" : "unknown",
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pci1_clk_sel ? "sync" : "async");
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if (pci_dual) {
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printf (" PCI2: 32 bit, 66 MHz, %s\n",
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printf("PCI2: 32 bit, 66 MHz, %s\n",
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pci2_clk_sel ? "sync" : "async");
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} else {
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printf (" PCI2: disabled\n");
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printf("PCI2: disabled\n");
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}
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/*
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@ -142,9 +142,9 @@ void pci_init_board(void)
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pcie3_hose.region_count = 1;
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#endif
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printf (" PCIE3 connected to ULI as %s (base addr %lx)\n",
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pcie_ep ? "Endpoint" : "Root Complex",
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pci_info[num].regs);
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printf("PCIE3: connected to ULI as %s (base addr %lx)\n",
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pcie_ep ? "Endpoint" : "Root Complex",
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pci_info[num].regs);
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first_free_busno = fsl_pci_init_port(&pci_info[num++],
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&pcie3_hose, first_free_busno);
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@ -154,7 +154,7 @@ void pci_init_board(void)
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*/
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in_be32((u32 *)CONFIG_SYS_PCIE3_MEM_BUS);
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} else {
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printf (" PCIE3: disabled\n");
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printf("PCIE3: disabled\n");
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}
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puts("\n");
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#else
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@ -177,14 +177,14 @@ void pci_init_board(void)
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pcie1_hose.region_count = 1;
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#endif
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printf (" PCIE1 connected to Slot 2 as %s (base addr %lx)\n",
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printf("PCIE1: connected to Slot 2 as %s (base addr %lx)\n",
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pcie_ep ? "Endpoint" : "Root Complex",
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pci_info[num].regs);
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first_free_busno = fsl_pci_init_port(&pci_info[num++],
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&pcie1_hose, first_free_busno);
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} else {
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printf (" PCIE1: disabled\n");
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printf("PCIE1: disabled\n");
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}
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puts("\n");
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@ -208,13 +208,13 @@ void pci_init_board(void)
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pcie2_hose.region_count = 1;
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#endif
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printf (" PCIE2 connected to Slot 1 as %s (base addr %lx)\n",
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pcie_ep ? "Endpoint" : "Root Complex",
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pci_info[num].regs);
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printf("PCIE2: connected to Slot 1 as %s (base addr %lx)\n",
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pcie_ep ? "Endpoint" : "Root Complex",
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pci_info[num].regs);
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first_free_busno = fsl_pci_init_port(&pci_info[num++],
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&pcie2_hose, first_free_busno);
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} else {
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printf (" PCIE2: disabled\n");
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printf("PCIE2: disabled\n");
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}
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puts("\n");
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@ -231,7 +231,7 @@ void pci_init_board(void)
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if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
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SET_STD_PCI_INFO(pci_info[num], 1);
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pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs);
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printf ("\n PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
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printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
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(pci_32) ? 32 : 64,
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(pci_speed == 33333000) ? "33" :
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(pci_speed == 66666000) ? "66" : "unknown",
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@ -243,7 +243,7 @@ void pci_init_board(void)
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first_free_busno = fsl_pci_init_port(&pci_info[num++],
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&pci1_hose, first_free_busno);
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} else {
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printf (" PCI: disabled\n");
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printf("PCI: disabled\n");
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}
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puts("\n");
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@ -284,7 +284,7 @@ void pci_init_board(void)
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if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
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SET_STD_PCI_INFO(pci_info[num], 1);
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pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs);
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printf ("\n PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
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printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
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(pci_32) ? 32 : 64,
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(pci_speed == 33333000) ? "33" :
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(pci_speed == 66666000) ? "66" : "unknown",
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@ -308,7 +308,7 @@ void pci_init_board(void)
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}
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#endif
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} else {
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printf (" PCI: disabled\n");
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printf("PCI: disabled\n");
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}
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puts("\n");
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@ -321,10 +321,10 @@ void pci_init_board(void)
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uint pci2_clk_sel = porpllsr & 0x4000; /* PORPLLSR[17] */
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uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */
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if (pci_dual) {
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printf (" PCI2: 32 bit, 66 MHz, %s\n",
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printf("PCI2: 32 bit, 66 MHz, %s\n",
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pci2_clk_sel ? "sync" : "async");
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} else {
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printf (" PCI2: disabled\n");
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printf("PCI2: disabled\n");
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}
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}
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#else
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@ -337,14 +337,14 @@ void pci_init_board(void)
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if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
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SET_STD_PCIE_INFO(pci_info[num], 1);
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pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
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printf (" PCIE1 connected to Slot as %s (base addr %lx)\n",
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pcie_ep ? "Endpoint" : "Root Complex",
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pci_info[num].regs);
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printf("PCIE1: connected to Slot as %s (base addr %lx)\n",
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pcie_ep ? "Endpoint" : "Root Complex",
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pci_info[num].regs);
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first_free_busno = fsl_pci_init_port(&pci_info[num++],
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&pcie1_hose, first_free_busno);
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} else {
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printf (" PCIE1: disabled\n");
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printf("PCIE1: disabled\n");
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}
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puts("\n");
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@ -219,17 +219,17 @@ int checkboard (void)
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MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
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MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
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printf (" PCI1: %d bit, %s MHz, %s\n",
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printf("PCI1: %d bit, %s MHz, %s\n",
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(pci1_32) ? 32 : 64,
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(pci1_speed == 33000000) ? "33" :
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(pci1_speed == 66000000) ? "66" : "unknown",
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pci1_clk_sel ? "sync" : "async");
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if (pci_dual) {
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printf (" PCI2: 32 bit, 66 MHz, %s\n",
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printf("PCI2: 32 bit, 66 MHz, %s\n",
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pci2_clk_sel ? "sync" : "async");
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} else {
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printf (" PCI2: disabled\n");
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printf("PCI2: disabled\n");
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}
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/*
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@ -252,10 +252,10 @@ int checkboard (void)
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puts("Board: ADS\n");
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#ifdef CONFIG_PCI
|
||||
printf(" PCI1: 32 bit, %d MHz (compiled)\n",
|
||||
printf("PCI1: 32 bit, %d MHz (compiled)\n",
|
||||
CONFIG_SYS_CLK_FREQ / 1000000);
|
||||
#else
|
||||
printf(" PCI1: disabled\n");
|
||||
printf("PCI1: disabled\n");
|
||||
#endif
|
||||
|
||||
/*
|
||||
|
|
|
@ -378,7 +378,7 @@ void pci_init_board(void)
|
|||
if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
|
||||
SET_STD_PCI_INFO(pci_info[num], 1);
|
||||
pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs);
|
||||
printf ("\n PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
|
||||
printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
|
||||
(pci_32) ? 32 : 64,
|
||||
(pci_speed == 33333000) ? "33" :
|
||||
(pci_speed == 66666000) ? "66" : "unknown",
|
||||
|
@ -390,7 +390,7 @@ void pci_init_board(void)
|
|||
first_free_busno = fsl_pci_init_port(&pci_info[num++],
|
||||
&pci1_hose, first_free_busno);
|
||||
} else {
|
||||
printf (" PCI: disabled\n");
|
||||
printf("PCI: disabled\n");
|
||||
}
|
||||
|
||||
puts("\n");
|
||||
|
@ -404,14 +404,14 @@ void pci_init_board(void)
|
|||
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
|
||||
SET_STD_PCIE_INFO(pci_info[num], 1);
|
||||
pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
|
||||
printf (" PCIE1 connected to Slot as %s (base addr %lx)\n",
|
||||
printf("PCIE1: connected to Slot as %s (base addr %lx)\n",
|
||||
pcie_ep ? "Endpoint" : "Root Complex",
|
||||
pci_info[num].regs);
|
||||
|
||||
first_free_busno = fsl_pci_init_port(&pci_info[num++],
|
||||
&pcie1_hose, first_free_busno);
|
||||
} else {
|
||||
printf (" PCIE1: disabled\n");
|
||||
printf("PCIE1: disabled\n");
|
||||
}
|
||||
|
||||
puts("\n");
|
||||
|
|
|
@ -584,13 +584,13 @@ void pci_init_board(void)
|
|||
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
|
||||
SET_STD_PCIE_INFO(pci_info[num], 1);
|
||||
pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
|
||||
printf (" PCIE1 connected to Slot as %s (base addr %lx)\n",
|
||||
pcie_ep ? "Endpoint" : "Root Complex",
|
||||
pci_info[num].regs);
|
||||
printf("PCIE1: connected to Slot as %s (base addr %lx)\n",
|
||||
pcie_ep ? "Endpoint" : "Root Complex",
|
||||
pci_info[num].regs);
|
||||
first_free_busno = fsl_pci_init_port(&pci_info[num++],
|
||||
&pcie1_hose, first_free_busno);
|
||||
} else {
|
||||
printf (" PCIE1: disabled\n");
|
||||
printf("PCIE1: disabled\n");
|
||||
}
|
||||
|
||||
puts("\n");
|
||||
|
|
|
@ -192,9 +192,9 @@ void pci_init_board(void)
|
|||
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){
|
||||
SET_STD_PCIE_INFO(pci_info[num], 3);
|
||||
pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs);
|
||||
printf (" PCIE3 connected to ULI as %s (base addr %lx)\n",
|
||||
pcie_ep ? "Endpoint" : "Root Complex",
|
||||
pci_info[num].regs);
|
||||
printf("PCIE3: connected to ULI as %s (base addr %lx)\n",
|
||||
pcie_ep ? "Endpoint" : "Root Complex",
|
||||
pci_info[num].regs);
|
||||
first_free_busno = fsl_pci_init_port(&pci_info[num++],
|
||||
&pcie3_hose, first_free_busno);
|
||||
/*
|
||||
|
@ -211,7 +211,7 @@ void pci_init_board(void)
|
|||
in_be32(p);
|
||||
}
|
||||
} else {
|
||||
printf (" PCIE3: disabled\n");
|
||||
printf("PCIE3: disabled\n");
|
||||
}
|
||||
puts("\n");
|
||||
#else
|
||||
|
@ -224,13 +224,13 @@ void pci_init_board(void)
|
|||
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)){
|
||||
SET_STD_PCIE_INFO(pci_info[num], 2);
|
||||
pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
|
||||
printf (" PCIE2 connected to Slot 1 as %s (base addr %lx)\n",
|
||||
pcie_ep ? "Endpoint" : "Root Complex",
|
||||
pci_info[num].regs);
|
||||
printf("PCIE2: connected to Slot 1 as %s (base addr %lx)\n",
|
||||
pcie_ep ? "Endpoint" : "Root Complex",
|
||||
pci_info[num].regs);
|
||||
first_free_busno = fsl_pci_init_port(&pci_info[num++],
|
||||
&pcie2_hose, first_free_busno);
|
||||
} else {
|
||||
printf (" PCIE2: disabled\n");
|
||||
printf("PCIE2: disabled\n");
|
||||
}
|
||||
|
||||
puts("\n");
|
||||
|
@ -244,13 +244,13 @@ void pci_init_board(void)
|
|||
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
|
||||
SET_STD_PCIE_INFO(pci_info[num], 1);
|
||||
pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
|
||||
printf (" PCIE1 connected to Slot 2 as %s (base addr %lx)\n",
|
||||
printf("PCIE1: connected to Slot 2 as %s (base addr %lx)\n",
|
||||
pcie_ep ? "Endpoint" : "Root Complex",
|
||||
pci_info[num].regs);
|
||||
first_free_busno = fsl_pci_init_port(&pci_info[num++],
|
||||
&pcie1_hose, first_free_busno);
|
||||
} else {
|
||||
printf (" PCIE1: disabled\n");
|
||||
printf("PCIE1: disabled\n");
|
||||
}
|
||||
|
||||
puts("\n");
|
||||
|
|
|
@ -244,14 +244,14 @@ void pci_init_board(void)
|
|||
if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE1)){
|
||||
SET_STD_PCIE_INFO(pci_info[num], 1);
|
||||
pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
|
||||
printf (" PCIE1 connected to ULI as %s (base addr %lx)\n",
|
||||
pcie_ep ? "Endpoint" : "Root Complex",
|
||||
pci_info[num].regs);
|
||||
printf("PCIE1: connected to ULI as %s (base addr %lx)\n",
|
||||
pcie_ep ? "Endpoint" : "Root Complex",
|
||||
pci_info[num].regs);
|
||||
|
||||
first_free_busno = fsl_pci_init_port(&pci_info[num++],
|
||||
&pcie1_hose, first_free_busno);
|
||||
} else {
|
||||
printf (" PCIE1: disabled\n");
|
||||
printf("PCIE1: disabled\n");
|
||||
}
|
||||
|
||||
puts("\n");
|
||||
|
@ -265,13 +265,13 @@ void pci_init_board(void)
|
|||
if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE2)){
|
||||
SET_STD_PCIE_INFO(pci_info[num], 2);
|
||||
pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
|
||||
printf (" PCIE2 connected to Slot as %s (base addr %lx)\n",
|
||||
pcie_ep ? "Endpoint" : "Root Complex",
|
||||
pci_info[num].regs);
|
||||
printf("PCIE2: connected to Slot as %s (base addr %lx)\n",
|
||||
pcie_ep ? "Endpoint" : "Root Complex",
|
||||
pci_info[num].regs);
|
||||
first_free_busno = fsl_pci_init_port(&pci_info[num++],
|
||||
&pcie2_hose, first_free_busno);
|
||||
} else {
|
||||
printf (" PCIE2: disabled\n");
|
||||
printf("PCIE2: disabled\n");
|
||||
}
|
||||
|
||||
puts("\n");
|
||||
|
@ -283,14 +283,14 @@ void pci_init_board(void)
|
|||
if (!(devdisr & MPC86xx_DEVDISR_PCI1)) {
|
||||
SET_STD_PCI_INFO(pci_info[num], 1);
|
||||
pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs);
|
||||
printf(" PCI connected to PCI slots as %s" \
|
||||
printf("PCI: connected to PCI slots as %s" \
|
||||
" (base address %lx)\n",
|
||||
pci_agent ? "Agent" : "Host",
|
||||
pci_info[num].regs);
|
||||
first_free_busno = fsl_pci_init_port(&pci_info[num++],
|
||||
&pci1_hose, first_free_busno);
|
||||
} else {
|
||||
printf (" PCI: disabled\n");
|
||||
printf("PCI: disabled\n");
|
||||
}
|
||||
|
||||
puts("\n");
|
||||
|
|
|
@ -157,9 +157,9 @@ void pci_init_board(void)
|
|||
if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) {
|
||||
SET_STD_PCIE_INFO(pci_info[num], 1);
|
||||
pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
|
||||
printf(" PCIE1 connected to ULI as %s (base addr %lx)\n",
|
||||
pcie_ep ? "Endpoint" : "Root Complex",
|
||||
pci_info[num].regs);
|
||||
printf("PCIE1: connected to ULI as %s (base addr %lx)\n",
|
||||
pcie_ep ? "Endpoint" : "Root Complex",
|
||||
pci_info[num].regs);
|
||||
first_free_busno = fsl_pci_init_port(&pci_info[num++],
|
||||
&pcie1_hose, first_free_busno);
|
||||
|
||||
|
@ -171,22 +171,22 @@ void pci_init_board(void)
|
|||
+ CONFIG_SYS_PCIE1_MEM_SIZE - 0x1000000)));
|
||||
|
||||
} else {
|
||||
puts(" PCIE1: disabled\n");
|
||||
puts("PCIE1: disabled\n");
|
||||
}
|
||||
#else
|
||||
puts(" PCIE1: disabled\n");
|
||||
puts("PCIE1: disabled\n");
|
||||
#endif /* CONFIG_PCIE1 */
|
||||
|
||||
#ifdef CONFIG_PCIE2
|
||||
SET_STD_PCIE_INFO(pci_info[num], 2);
|
||||
pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
|
||||
printf(" PCIE2 connected as %s (base addr %lx)\n",
|
||||
pcie_ep ? "Endpoint" : "Root Complex",
|
||||
pci_info[num].regs);
|
||||
printf("PCIE2: connected as %s (base addr %lx)\n",
|
||||
pcie_ep ? "Endpoint" : "Root Complex",
|
||||
pci_info[num].regs);
|
||||
first_free_busno = fsl_pci_init_port(&pci_info[num++],
|
||||
&pcie2_hose, first_free_busno);
|
||||
#else
|
||||
puts(" PCIE2: disabled\n");
|
||||
puts("PCIE2: disabled\n");
|
||||
#endif /* CONFIG_PCIE2 */
|
||||
|
||||
}
|
||||
|
|
|
@ -225,7 +225,7 @@ static void configure_pcie(struct fsl_pci_info *info,
|
|||
set_next_law(info->mem_phys, law_size_bits(info->mem_size), info->law);
|
||||
set_next_law(info->io_phys, law_size_bits(info->io_size), info->law);
|
||||
is_endpoint = fsl_setup_hose(hose, info->regs);
|
||||
printf(" PCIE%u connected to %s as %s (base addr %lx)\n",
|
||||
printf("PCIE%u: connected to %s as %s (base addr %lx)\n",
|
||||
info->pci_num, connected,
|
||||
is_endpoint ? "Endpoint" : "Root Complex", info->regs);
|
||||
bus_number = fsl_pci_init_port(info, hose, bus_number);
|
||||
|
@ -255,7 +255,7 @@ void pci_init_board(void)
|
|||
SET_STD_PCIE_INFO(pci_info, 1);
|
||||
configure_pcie(&pci_info, &pcie1_hose, serdes_slot_name(PCIE1));
|
||||
} else {
|
||||
printf(" PCIE1: disabled\n");
|
||||
printf("PCIE1: disabled\n");
|
||||
}
|
||||
#else
|
||||
setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */
|
||||
|
@ -266,7 +266,7 @@ void pci_init_board(void)
|
|||
SET_STD_PCIE_INFO(pci_info, 2);
|
||||
configure_pcie(&pci_info, &pcie2_hose, serdes_slot_name(PCIE2));
|
||||
} else {
|
||||
printf(" PCIE2: disabled\n");
|
||||
printf("PCIE2: disabled\n");
|
||||
}
|
||||
#else
|
||||
setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */
|
||||
|
@ -277,7 +277,7 @@ void pci_init_board(void)
|
|||
SET_STD_PCIE_INFO(pci_info, 3);
|
||||
configure_pcie(&pci_info, &pcie3_hose, serdes_slot_name(PCIE3));
|
||||
} else {
|
||||
printf(" PCIE3: disabled\n");
|
||||
printf("PCIE3: disabled\n");
|
||||
}
|
||||
#else
|
||||
setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE3); /* disable */
|
||||
|
|
|
@ -65,13 +65,13 @@ void pci_init_board(void)
|
|||
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
|
||||
SET_STD_PCIE_INFO(pci_info[num], 2);
|
||||
pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
|
||||
printf(" PCIE2 connected to Slot 1 as %s (base addr %lx)\n",
|
||||
pcie_ep ? "Endpoint" : "Root Complex",
|
||||
pci_info[num].regs);
|
||||
printf("PCIE2: connected to Slot 1 as %s (base addr %lx)\n",
|
||||
pcie_ep ? "Endpoint" : "Root Complex",
|
||||
pci_info[num].regs);
|
||||
first_free_busno = fsl_pci_init_port(&pci_info[num++],
|
||||
&pcie2_hose, first_free_busno);
|
||||
} else {
|
||||
printf (" PCIE2: disabled\n");
|
||||
printf("PCIE2: disabled\n");
|
||||
}
|
||||
puts("\n");
|
||||
#else
|
||||
|
@ -84,13 +84,13 @@ void pci_init_board(void)
|
|||
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
|
||||
SET_STD_PCIE_INFO(pci_info[num], 1);
|
||||
pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
|
||||
printf(" PCIE1 connected to Slot 2 as %s (base addr %lx)\n",
|
||||
pcie_ep ? "Endpoint" : "Root Complex",
|
||||
pci_info[num].regs);
|
||||
printf("PCIE1: connected to Slot 2 as %s (base addr %lx)\n",
|
||||
pcie_ep ? "Endpoint" : "Root Complex",
|
||||
pci_info[num].regs);
|
||||
first_free_busno = fsl_pci_init_port(&pci_info[num++],
|
||||
&pcie1_hose, first_free_busno);
|
||||
} else {
|
||||
printf (" PCIE1: disabled\n");
|
||||
printf("PCIE1: disabled\n");
|
||||
}
|
||||
puts("\n");
|
||||
#else
|
||||
|
|
|
@ -218,9 +218,9 @@ void pci_init_board(void)
|
|||
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)) {
|
||||
SET_STD_PCIE_INFO(pci_info[num], 2);
|
||||
pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
|
||||
printf(" PCIE2 connected to ULI as %s (base addr %lx)\n",
|
||||
pcie_ep ? "Endpoint" : "Root Complex",
|
||||
pci_info[num].regs);
|
||||
printf("PCIE2: connected to ULI as %s (base addr %lx)\n",
|
||||
pcie_ep ? "Endpoint" : "Root Complex",
|
||||
pci_info[num].regs);
|
||||
first_free_busno = fsl_pci_init_port(&pci_info[num++],
|
||||
&pcie2_hose, first_free_busno);
|
||||
|
||||
|
@ -245,7 +245,7 @@ void pci_init_board(void)
|
|||
}
|
||||
#endif
|
||||
} else {
|
||||
printf(" PCIE2: disabled\n");
|
||||
printf("PCIE2: disabled\n");
|
||||
}
|
||||
puts("\n");
|
||||
#else
|
||||
|
@ -258,13 +258,13 @@ void pci_init_board(void)
|
|||
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)) {
|
||||
SET_STD_PCIE_INFO(pci_info[num], 3);
|
||||
pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs);
|
||||
printf(" PCIE3 connected to Slot 1 as %s (base addr %lx)\n",
|
||||
pcie_ep ? "Endpoint" : "Root Complex",
|
||||
pci_info[num].regs);
|
||||
printf("PCIE3: connected to Slot 1 as %s (base addr %lx)\n",
|
||||
pcie_ep ? "Endpoint" : "Root Complex",
|
||||
pci_info[num].regs);
|
||||
first_free_busno = fsl_pci_init_port(&pci_info[num++],
|
||||
&pcie3_hose, first_free_busno);
|
||||
} else {
|
||||
printf(" PCIE3: disabled\n");
|
||||
printf("PCIE3: disabled\n");
|
||||
}
|
||||
puts("\n");
|
||||
#else
|
||||
|
@ -277,13 +277,13 @@ void pci_init_board(void)
|
|||
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)) {
|
||||
SET_STD_PCIE_INFO(pci_info[num], 1);
|
||||
pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
|
||||
printf(" PCIE1 connected to Slot 2 as %s (base addr %lx)\n",
|
||||
pcie_ep ? "Endpoint" : "Root Complex",
|
||||
pci_info[num].regs);
|
||||
printf("PCIE1: connected to Slot 2 as %s (base addr %lx)\n",
|
||||
pcie_ep ? "Endpoint" : "Root Complex",
|
||||
pci_info[num].regs);
|
||||
first_free_busno = fsl_pci_init_port(&pci_info[num++],
|
||||
&pcie1_hose, first_free_busno);
|
||||
} else {
|
||||
printf(" PCIE1: disabled\n");
|
||||
printf("PCIE1: disabled\n");
|
||||
}
|
||||
puts("\n");
|
||||
#else
|
||||
|
|
|
@ -59,10 +59,10 @@ int checkboard (void)
|
|||
puts("Board: MicroSys PM854\n");
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
printf(" PCI1: 32 bit, %d MHz (compiled)\n",
|
||||
printf("PCI1: 32 bit, %d MHz (compiled)\n",
|
||||
CONFIG_SYS_CLK_FREQ / 1000000);
|
||||
#else
|
||||
printf(" PCI1: disabled\n");
|
||||
printf("PCI1: disabled\n");
|
||||
#endif
|
||||
|
||||
/*
|
||||
|
|
|
@ -213,10 +213,10 @@ int checkboard (void)
|
|||
puts("Board: MicroSys PM856\n");
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
printf(" PCI1: 32 bit, %d MHz (compiled)\n",
|
||||
printf("PCI1: 32 bit, %d MHz (compiled)\n",
|
||||
CONFIG_SYS_CLK_FREQ / 1000000);
|
||||
#else
|
||||
printf(" PCI1: disabled\n");
|
||||
printf("PCI1: disabled\n");
|
||||
#endif
|
||||
|
||||
/*
|
||||
|
|
|
@ -342,7 +342,7 @@ pci_init_board(void)
|
|||
uint pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
|
||||
uint pci_speed = CONFIG_SYS_CLK_FREQ; /* get_clock_freq() */
|
||||
|
||||
printf (" PCI host: %d bit, %s MHz, %s, %s\n",
|
||||
printf("PCI: Host, %d bit, %s MHz, %s, %s\n",
|
||||
(pci_32) ? 32 : 64,
|
||||
(pci_speed == 33000000) ? "33" :
|
||||
(pci_speed == 66000000) ? "66" : "unknown",
|
||||
|
@ -353,7 +353,7 @@ pci_init_board(void)
|
|||
first_free_busno = fsl_pci_init_port(&pci_info[num++],
|
||||
&pci1_hose, first_free_busno);
|
||||
} else {
|
||||
printf (" PCI: disabled\n");
|
||||
printf("PCI: disabled\n");
|
||||
}
|
||||
|
||||
puts("\n");
|
||||
|
@ -368,11 +368,11 @@ pci_init_board(void)
|
|||
|
||||
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
|
||||
SET_STD_PCIE_INFO(pci_info[num], 1);
|
||||
printf (" PCIE at base address %lx\n", pci_info[num].regs);
|
||||
printf("PCIE: base address %lx\n", pci_info[num].regs);
|
||||
first_free_busno = fsl_pci_init_port(&pci_info[num++],
|
||||
&pcie1_hose, first_free_busno);
|
||||
} else {
|
||||
printf (" PCIE: disabled\n");
|
||||
printf("PCIE: disabled\n");
|
||||
}
|
||||
|
||||
puts("\n");
|
||||
|
|
|
@ -221,29 +221,29 @@ void pci_init_board(void)
|
|||
if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) {
|
||||
SET_STD_PCIE_INFO(pci_info[num], 1);
|
||||
pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
|
||||
printf(" PCIE1 connected as %s (base addr %lx)\n",
|
||||
pcie_ep ? "Endpoint" : "Root Complex",
|
||||
pci_info[num].regs);
|
||||
printf("PCIE1: connected as %s (base addr %lx)\n",
|
||||
pcie_ep ? "Endpoint" : "Root Complex",
|
||||
pci_info[num].regs);
|
||||
first_free_busno = fsl_pci_init_port(&pci_info[num++],
|
||||
&pcie1_hose, first_free_busno);
|
||||
} else {
|
||||
puts(" PCIE1: disabled\n");
|
||||
puts("PCIE1: disabled\n");
|
||||
}
|
||||
#else
|
||||
puts(" PCIE1: disabled\n");
|
||||
puts("PCIE1: disabled\n");
|
||||
#endif /* CONFIG_PCIE1 */
|
||||
|
||||
#ifdef CONFIG_PCIE2
|
||||
|
||||
SET_STD_PCIE_INFO(pci_info[num], 2);
|
||||
pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
|
||||
printf(" PCIE2 connected as %s (base addr %lx)\n",
|
||||
pcie_ep ? "Endpoint" : "Root Complex",
|
||||
pci_info[num].regs);
|
||||
printf("PCIE2: connected as %s (base addr %lx)\n",
|
||||
pcie_ep ? "Endpoint" : "Root Complex",
|
||||
pci_info[num].regs);
|
||||
first_free_busno = fsl_pci_init_port(&pci_info[num++],
|
||||
&pcie2_hose, first_free_busno);
|
||||
#else
|
||||
puts(" PCIE2: disabled\n");
|
||||
puts("PCIE2: disabled\n");
|
||||
#endif /* CONFIG_PCIE2 */
|
||||
}
|
||||
|
||||
|
|
|
@ -567,7 +567,7 @@ void pci_init_board (void)
|
|||
if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
|
||||
SET_STD_PCI_INFO(pci_info[num], 1);
|
||||
pcie_ep = fsl_setup_hose(&pci1_hose, pci_info[num].regs);
|
||||
printf ("\n PCI1: %d bit, %s MHz, %s, %s, %s\n",
|
||||
printf("PCI1: %d bit, %s MHz, %s, %s, %s\n",
|
||||
(pci_32) ? 32 : 64,
|
||||
(pci_speed == 33333333) ? "33" :
|
||||
(pci_speed == 66666666) ? "66" : "unknown",
|
||||
|
@ -591,7 +591,7 @@ void pci_init_board (void)
|
|||
}
|
||||
#endif
|
||||
} else {
|
||||
printf(" PCI1: disabled\n");
|
||||
printf("PCI1: disabled\n");
|
||||
}
|
||||
#else
|
||||
setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1);
|
||||
|
@ -603,12 +603,12 @@ void pci_init_board (void)
|
|||
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)) {
|
||||
SET_STD_PCIE_INFO(pci_info[num], 1);
|
||||
pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
|
||||
printf(" PCIE1 connected as %s\n",
|
||||
printf("PCIE1: connected as %s\n",
|
||||
pcie_ep ? "Endpoint" : "Root Complex");
|
||||
first_free_busno = fsl_pci_init_port(&pci_info[num++],
|
||||
&pcie1_hose, first_free_busno);
|
||||
} else {
|
||||
printf(" PCIE1: disabled\n");
|
||||
printf("PCIE1: disabled\n");
|
||||
}
|
||||
#else
|
||||
setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE);
|
||||
|
|
|
@ -95,7 +95,7 @@ void pci_init_board(void)
|
|||
if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
|
||||
SET_STD_PCI_INFO(pci_info[num], 1);
|
||||
pcie_ep = fsl_setup_hose(&pci1_hose, pci_info[num].regs);
|
||||
printf("\n PCI1: %d bit %s, %s %d MHz, %s, %s\n",
|
||||
printf("PCI1: %d bit %s, %s %d MHz, %s, %s\n",
|
||||
pci_32 ? 32 : 64,
|
||||
pcix ? "PCIX" : "PCI",
|
||||
pci_spd_norm ? ">=" : "<=",
|
||||
|
@ -106,7 +106,7 @@ void pci_init_board(void)
|
|||
first_free_busno = fsl_pci_init_port(&pci_info[num++],
|
||||
&pci1_hose, first_free_busno);
|
||||
} else {
|
||||
printf(" PCI1: disabled\n");
|
||||
printf("PCI1: disabled\n");
|
||||
}
|
||||
#elif defined CONFIG_MPC8548
|
||||
/* PCI1 not present on MPC8572 */
|
||||
|
@ -119,12 +119,12 @@ void pci_init_board(void)
|
|||
if (pcie_configured && !(devdisr & MPC8xxx_DEVDISR_PCIE1)) {
|
||||
SET_STD_PCIE_INFO(pci_info[num], 1);
|
||||
pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
|
||||
printf(" PCIE1 connected as %s\n",
|
||||
printf("PCIE1: connected as %s\n",
|
||||
pcie_ep ? "Endpoint" : "Root Complex");
|
||||
first_free_busno = fsl_pci_init_port(&pci_info[num++],
|
||||
&pcie1_hose, first_free_busno);
|
||||
} else {
|
||||
printf(" PCIE1: disabled\n");
|
||||
printf("PCIE1: disabled\n");
|
||||
}
|
||||
#else
|
||||
setbits_be32(&gur->devdisr, MPC8xxx_DEVDISR_PCIE1);
|
||||
|
@ -136,12 +136,12 @@ void pci_init_board(void)
|
|||
if (pcie_configured && !(devdisr & MPC8xxx_DEVDISR_PCIE2)) {
|
||||
SET_STD_PCIE_INFO(pci_info[num], 2);
|
||||
pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
|
||||
printf(" PCIE2 connected as %s\n",
|
||||
printf("PCIE2: connected as %s\n",
|
||||
pcie_ep ? "Endpoint" : "Root Complex");
|
||||
first_free_busno = fsl_pci_init_port(&pci_info[num++],
|
||||
&pcie2_hose, first_free_busno);
|
||||
} else {
|
||||
printf(" PCIE2: disabled\n");
|
||||
printf("PCIE2: disabled\n");
|
||||
}
|
||||
#else
|
||||
setbits_be32(&gur->devdisr, MPC8xxx_DEVDISR_PCIE2);
|
||||
|
@ -153,12 +153,12 @@ void pci_init_board(void)
|
|||
if (pcie_configured && !(devdisr & MPC8xxx_DEVDISR_PCIE3)) {
|
||||
SET_STD_PCIE_INFO(pci_info[num], 3);
|
||||
pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs);
|
||||
printf(" PCIE3 connected as %s\n",
|
||||
printf("PCIE3: connected as %s\n",
|
||||
pcie_ep ? "Endpoint" : "Root Complex");
|
||||
first_free_busno = fsl_pci_init_port(&pci_info[num++],
|
||||
&pcie3_hose, first_free_busno);
|
||||
} else {
|
||||
printf(" PCIE3: disabled\n");
|
||||
printf("PCIE3: disabled\n");
|
||||
}
|
||||
#else
|
||||
setbits_be32(&gur->devdisr, MPC8xxx_DEVDISR_PCIE3);
|
||||
|
|
|
@ -391,11 +391,11 @@ void fsl_pci_init(struct pci_controller *hose, u32 cfg_addr, u32 cfg_data)
|
|||
* 1 == pci agent or pcie end-point
|
||||
*/
|
||||
if (!temp8) {
|
||||
printf(" Scanning PCI bus %02x\n",
|
||||
printf(" Scanning PCI bus %02x\n",
|
||||
hose->current_busno);
|
||||
hose->last_busno = pci_hose_scan_bus(hose, hose->current_busno);
|
||||
} else {
|
||||
debug(" Not scanning PCI bus %02x. PI=%x\n",
|
||||
debug(" Not scanning PCI bus %02x. PI=%x\n",
|
||||
hose->current_busno, temp8);
|
||||
hose->last_busno = hose->current_busno;
|
||||
}
|
||||
|
@ -482,9 +482,9 @@ int fsl_pci_init_port(struct fsl_pci_info *pci_info,
|
|||
}
|
||||
|
||||
pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, &pcie_cap);
|
||||
printf(" PCI%s%x on bus %02x - %02x\n", pcie_cap == PCI_CAP_ID_EXP ?
|
||||
"E" : "", pci_info->pci_num,
|
||||
hose->first_busno, hose->last_busno);
|
||||
printf("PCI%s%x: Bus %02x - %02x\n", pcie_cap == PCI_CAP_ID_EXP ?
|
||||
"E" : "", pci_info->pci_num,
|
||||
hose->first_busno, hose->last_busno);
|
||||
|
||||
return(hose->last_busno + 1);
|
||||
}
|
||||
|
|
Loading…
Add table
Reference in a new issue