mirror of
https://github.com/Fishwaldo/u-boot.git
synced 2025-03-15 11:41:31 +00:00
riscv: dts: Add StarFive JH7110 Devkits board device tree
Add device tree for StarFive JH7110 Devkits board. The code is ported from tag JH7110_DVK_515_v3.9.3 of Devkits repo. Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
This commit is contained in:
Hal Feng
parent
55255733cf
commit
8d2695797e
3 changed files with 401 additions and 0 deletions
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@ -7,6 +7,7 @@ dtb-$(CONFIG_TARGET_OPENPITON_RISCV64) += openpiton-riscv64.dtb
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dtb-$(CONFIG_TARGET_SIFIVE_UNLEASHED) += hifive-unleashed-a00.dtb
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dtb-$(CONFIG_TARGET_SIFIVE_UNMATCHED) += hifive-unmatched-a00.dtb
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dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb
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dtb-$(CONFIG_TARGET_STARFIVE_DEVKITS) += starfive_devkits.dtb
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dtb-$(CONFIG_TARGET_STARFIVE_VISIONFIVE2) += starfive_visionfive2.dtb
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dtb-$(CONFIG_TARGET_STARFIVE_EVB) += starfive_evb.dtb
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29
arch/riscv/dts/starfive_devkits-u-boot.dtsi
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29
arch/riscv/dts/starfive_devkits-u-boot.dtsi
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@ -0,0 +1,29 @@
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// SPDX-License-Identifier: GPL-2.0 OR MIT
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/*
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* Copyright (C) 2022 StarFive Technology Co., Ltd.
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*/
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#include "jh7110-u-boot.dtsi"
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/ {
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chosen {
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stdout-path = "/soc/serial@10000000:115200";
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u-boot,dm-spl;
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};
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firmware {
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spi0="/soc/qspi@11860000";
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u-boot,dm-spl;
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};
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config {
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u-boot,dm-spl;
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u-boot,spl-payload-offset = <0x100000>; /* loader2 @1044KB */
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};
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memory@80000000 {
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u-boot,dm-spl;
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device_type = "memory";
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reg = <0x0 0x40000000 0x1 0x0>;
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};
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};
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371
arch/riscv/dts/starfive_devkits.dts
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371
arch/riscv/dts/starfive_devkits.dts
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@ -0,0 +1,371 @@
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// SPDX-License-Identifier: GPL-2.0 OR MIT
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/*
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* Copyright (C) 2022 StarFive Technology Co., Ltd.
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*/
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/dts-v1/;
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#include "jh7110.dtsi"
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#include <dt-bindings/pinctrl/pinctrl-starfive-jh7110.h>
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#include <dt-bindings/gpio/gpio.h>
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/ {
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#address-cells = <2>;
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#size-cells = <2>;
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model = "StarFive JH7110 DevKits";
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compatible = "starfive,jh7110";
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aliases {
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spi0="/soc/spi@13010000";
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gpio0="/soc/gpio@13040000";
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ethernet0=&gmac0;
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ethernet1=&gmac1;
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mmc0=&sdio0;
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mmc1=&sdio1;
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i2c5=&i2c5;
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};
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chosen {
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stdout-path = "/soc/serial@10000000:115200";
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starfive,boot-hart-id = <1>;
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};
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memory@80000000 {
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device_type = "memory";
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reg = <0x0 0x40000000 0x1 0x0>;
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};
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soc {
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};
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gpio-restart {
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compatible = "gpio-restart";
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gpios = <&gpio 35 GPIO_ACTIVE_HIGH>;
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};
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};
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&cpu0 {
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status = "okay";
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};
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&clkgen {
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clocks = <&osc>, <&gmac1_rmii_refin>,
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<&stg_apb>, <&gmac0_rmii_refin>;
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clock-names = "osc", "gmac1_rmii_refin",
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"stg_apb", "gmac0_rmii_refin";
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};
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&gpio {
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status = "okay";
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gpio-controller;
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i2c2_pins: i2c2-0 {
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i2c-pins {
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pinmux = <GPIOMUX(3, GPOUT_LOW,
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GPOEN_SYS_I2C2_CLK,
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GPI_SYS_I2C2_CLK)>,
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<GPIOMUX(2, GPOUT_LOW,
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GPOEN_SYS_I2C2_DATA,
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GPI_SYS_I2C2_DATA)>;
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bias-disable; /* external pull-up */
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input-enable;
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input-schmitt-enable;
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};
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};
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i2c5_pins: i2c5-0 {
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i2c-pins {
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pinmux = <GPIOMUX(19, GPOUT_LOW,
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GPOEN_SYS_I2C5_CLK,
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GPI_SYS_I2C5_CLK)>,
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<GPIOMUX(20, GPOUT_LOW,
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GPOEN_SYS_I2C5_DATA,
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GPI_SYS_I2C5_DATA)>;
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bias-disable; /* external pull-up */
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input-enable;
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input-schmitt-enable;
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};
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};
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mmc0_pins: mmc0-pins {
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mmc0-pins-rest {
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pinmux = <GPIOMUX(22, GPOUT_SYS_SDIO0_RST,
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GPOEN_ENABLE, GPI_NONE)>;
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bias-pull-up;
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drive-strength = <12>;
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input-disable;
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input-schmitt-disable;
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slew-rate = <0>;
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};
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};
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sdcard1_pins: sdcard1-pins {
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sdcard1-pins0 {
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pinmux = <GPIOMUX(10, GPOUT_SYS_SDIO1_CLK,
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GPOEN_ENABLE, GPI_NONE)>;
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bias-pull-up;
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drive-strength = <12>;
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input-disable;
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input-schmitt-disable;
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slew-rate = <0>;
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};
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sdcard1-pins1 {
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pinmux = <GPIOMUX(9, GPOUT_SYS_SDIO1_CMD,
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GPOEN_SYS_SDIO1_CMD, GPI_SYS_SDIO1_CMD)>;
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bias-pull-up;
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drive-strength = <12>;
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input-enable;
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input-schmitt-enable;
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slew-rate = <0>;
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};
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sdcard1-pins2 {
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pinmux = <GPIOMUX(11, GPOUT_SYS_SDIO1_DATA0,
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GPOEN_SYS_SDIO1_DATA0, GPI_SYS_SDIO1_DATA0)>;
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bias-pull-up;
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drive-strength = <12>;
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input-enable;
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input-schmitt-enable;
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slew-rate = <0>;
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};
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sdcard1-pins3 {
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pinmux = <GPIOMUX(12, GPOUT_SYS_SDIO1_DATA1,
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GPOEN_SYS_SDIO1_DATA1, GPI_SYS_SDIO1_DATA1)>;
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bias-pull-up;
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drive-strength = <12>;
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input-enable;
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input-schmitt-enable;
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slew-rate = <0>;
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};
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sdcard1-pins4 {
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pinmux = <GPIOMUX(7, GPOUT_SYS_SDIO1_DATA2,
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GPOEN_SYS_SDIO1_DATA2, GPI_SYS_SDIO1_DATA2)>;
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bias-pull-up;
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drive-strength = <12>;
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input-enable;
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input-schmitt-enable;
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slew-rate = <0>;
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};
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sdcard1-pins5 {
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pinmux = <GPIOMUX(8, GPOUT_SYS_SDIO1_DATA3,
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GPOEN_SYS_SDIO1_DATA3, GPI_SYS_SDIO1_DATA3)>;
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bias-pull-up;
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drive-strength = <12>;
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input-enable;
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input-schmitt-enable;
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slew-rate = <0>;
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};
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};
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hdmi_pins: hdmi-0 {
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i2c-pins {
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pinmux = <GPIOMUX(0, GPOUT_SYS_HDMI_DDC_SCL,
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GPOEN_SYS_HDMI_DDC_SCL,
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GPI_SYS_HDMI_DDC_SCL)>,
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<GPIOMUX(1, GPOUT_SYS_HDMI_DDC_SDA,
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GPOEN_SYS_HDMI_DDC_SDA,
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GPI_SYS_HDMI_DDC_SDA)>;
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bias-pull-up;
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input-enable;
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};
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cec-pins {
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pinmux = <GPIOMUX(14, GPOUT_SYS_HDMI_CEC_SDA,
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GPOEN_SYS_HDMI_CEC_SDA,
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GPI_SYS_HDMI_CEC_SDA)>;
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bias-pull-up;
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input-enable;
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};
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hpd-pins {
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pinmux = <GPIOMUX(15, GPOUT_LOW,
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GPOEN_DISABLE,
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GPI_SYS_HDMI_HPD)>;
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input-enable;
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};
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};
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};
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&i2c2 {
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clock-frequency = <100000>;
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i2c-sda-hold-time-ns = <300>;
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i2c-sda-falling-time-ns = <510>;
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i2c-scl-falling-time-ns = <510>;
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auto_calc_scl_lhcnt;
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pinctrl-names = "default";
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pinctrl-0 = <&i2c2_pins>;
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status = "okay";
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seeed_panel: seeed_panel@45 {
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compatible = "starfive,seeed";
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reg = <0x45>;
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sel-gpios = <&ext_gpio 5 GPIO_ACTIVE_LOW>;
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};
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lt8911exb_i2c@29 {
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compatible = "lontium,lt8911exb";
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reg = <0x29>;
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reset-gpios = <&gpio 41 1>;
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pwm-gpios = <&gpio 33 1>;
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bl-gpios = <&ext_gpio 6 GPIO_ACTIVE_LOW>;
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};
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};
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&i2c5 {
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clock-frequency = <100000>;
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i2c-sda-hold-time-ns = <300>;
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i2c-sda-falling-time-ns = <510>;
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i2c-scl-falling-time-ns = <510>;
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pinctrl-names = "default";
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pinctrl-0 = <&i2c5_pins>;
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status = "okay";
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pmic_axp15060: axp15060_reg@36 {
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compatible = "stf,axp15060-regulator";
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reg = <0x36>;
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};
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eeprom@50 {
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compatible = "atmel,24c04";
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reg = <0x50>;
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pagesize = <16>;
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};
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ext_gpio: ext_gpio@74 {
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compatible = "ti,tca9539";
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reg = <0x74>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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};
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&sdio0 {
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assigned-clocks = <&clkgen JH7110_SDIO0_CLK_SDCARD>;
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assigned-clock-rates = <50000000>;
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fifo-depth = <32>;
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bus-width = <4>;
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&mmc0_pins>;
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};
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&sdio1 {
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assigned-clocks = <&clkgen JH7110_SDIO1_CLK_SDCARD>;
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assigned-clock-rates = <50000000>;
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fifo-depth = <32>;
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bus-width = <4>;
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&sdcard1_pins>;
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};
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&gmac0 {
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status = "okay";
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#address-cells = <1>;
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#size-cells = <0>;
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phy0: ethernet-phy@0 {
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rxc_dly_en = <0>;
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rx_delay_sel = <0xb>;
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tx_delay_sel_fe = <5>;
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tx_delay_sel = <0xa>;
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tx_inverted_10 = <0x1>;
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tx_inverted_100 = <0x1>;
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tx_inverted_1000 = <0x1>;
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};
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};
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&gmac1 {
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status = "okay";
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#address-cells = <1>;
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#size-cells = <0>;
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phy1: ethernet-phy@1 {
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rgmii_sw_dr_2 = <0x0>;
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rgmii_sw_dr = <0x3>;
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rgmii_sw_dr_rxc = <0x7>;
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tx_delay_sel_fe = <5>;
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tx_delay_sel = <0>;
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rxc_dly_en = <0>;
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rx_delay_sel = <0x2>;
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tx_inverted_10 = <0x1>;
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tx_inverted_100 = <0x1>;
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tx_inverted_1000 = <0x0>;
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};
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};
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&uart0 {
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reg-offset = <0>;
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current-speed = <115200>;
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status = "okay";
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};
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&gpioa {
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status = "disabled";
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};
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&usbdrd30 {
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clocks = <&clkgen JH7110_USB_125M>,
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<&clkgen JH7110_USB0_CLK_APP_125>,
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<&clkgen JH7110_USB0_CLK_LPM>,
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<&clkgen JH7110_USB0_CLK_STB>,
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<&clkgen JH7110_USB0_CLK_USB_APB>,
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<&clkgen JH7110_USB0_CLK_AXI>,
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<&clkgen JH7110_USB0_CLK_UTMI_APB>,
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<&clkgen JH7110_PCIE0_CLK_APB>;
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clock-names = "125m","app","lpm","stb","apb","axi","utmi", "phy";
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resets = <&rstgen RSTN_U0_CDN_USB_PWRUP>,
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<&rstgen RSTN_U0_CDN_USB_APB>,
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<&rstgen RSTN_U0_CDN_USB_AXI>,
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<&rstgen RSTN_U0_CDN_USB_UTMI_APB>,
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<&rstgen RSTN_U0_PLDA_PCIE_APB>;
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reset-names = "pwrup","apb","axi","utmi", "phy";
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starfive,usb2-only = <0>;
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status = "okay";
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};
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&usbdrd_cdns3 {
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dr_mode = "unknown";
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dr_num_mode = <1>;
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};
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&timer {
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status = "disabled";
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};
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&wdog {
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status = "disabled";
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};
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&clkvout {
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status = "okay";
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};
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&pdm {
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status = "disabled";
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};
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&dc8200 {
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status = "okay";
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};
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&mipi_dsi0 {
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status = "okay";
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rockchip,panel = <&seeed_panel>;
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data-lanes-num = <1>;
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status = "okay";
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};
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&hdmi{
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pinctrl-names = "default";
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pinctrl-0 = <&hdmi_pins>;
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status = "okay";
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};
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&pcie1 {
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power-gpios = <&ext_gpio 0 GPIO_ACTIVE_HIGH>;
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reset-gpios = <&gpio 18 GPIO_ACTIVE_LOW>;
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status = "okay";
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};
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Add table
Reference in a new issue