- Armada 8k: Add NAND support via PXA3xx NAND driver (Baruch)
- Armada 8k: Use ATF serdes init instead of the "old" U-Boot version
  (Baruch)
- Minor update to Octeon TX/TX2 defconfig (Stefan)
This commit is contained in:
Tom Rini 2020-10-29 11:30:29 -04:00
commit 8d7f3fcb4a
9 changed files with 238 additions and 1254 deletions

View file

@ -285,15 +285,18 @@
};
cpm_nand: nand@720000 {
compatible = "marvell,mvebu-pxa3xx-nand";
reg = <0x720000 0x100>;
compatible = "marvell,armada-8k-nand-controller",
"marvell,armada370-nand-controller";
reg = <0x720000 0x54>;
#address-cells = <1>;
clocks = <&cpm_syscon0 1 2>;
#size-cells = <0>;
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "core", "reg";
clocks = <&cpm_syscon0 1 2>,
<&cpm_syscon0 1 17>;
marvell,system-controller = <&cpm_syscon0>;
nand-enable-arbiter;
num-cs = <1>;
nand-ecc-strength = <4>;
nand-ecc-step-size = <512>;
status = "disabled";
};

View file

@ -267,6 +267,22 @@
utmi-port = <UTMI_PHY_TO_USB3_HOST0>;
status = "disabled";
};
cps_nand: nand@720000 {
compatible = "marvell,armada-8k-nand-controller",
"marvell,armada370-nand-controller";
reg = <0x720000 0x54>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "core", "reg";
clocks = <&cps_syscon0 1 2>,
<&cps_syscon0 1 17>;
marvell,system-controller = <&cps_syscon0>;
nand-enable-arbiter;
num-cs = <1>;
status = "disabled";
};
};
cps_pcie0: pcie@f4600000 {

View file

@ -86,6 +86,8 @@ CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_DM_ETH=y
CONFIG_NET_OCTEONTX2=y
CONFIG_OCTEONTX_SMI=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y

View file

@ -99,6 +99,8 @@ CONFIG_DM_ETH=y
CONFIG_E1000=y
CONFIG_E1000_SPI=y
CONFIG_CMD_E1000=y
CONFIG_NET_OCTEONTX2=y
CONFIG_OCTEONTX_SMI=y
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI=y

View file

@ -100,6 +100,8 @@ CONFIG_DM_ETH=y
CONFIG_E1000=y
CONFIG_E1000_SPI=y
CONFIG_CMD_E1000=y
CONFIG_NET_OCTEONTX=y
CONFIG_OCTEONTX_SMI=y
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI=y

View file

@ -97,6 +97,8 @@ CONFIG_DM_ETH=y
CONFIG_E1000=y
CONFIG_E1000_SPI=y
CONFIG_CMD_E1000=y
CONFIG_NET_OCTEONTX=y
CONFIG_OCTEONTX_SMI=y
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI=y

View file

@ -195,6 +195,9 @@ endif
config NAND_PXA3XX
bool "Support for NAND on PXA3xx and Armada 370/XP/38x"
select SYS_NAND_SELF_INIT
select DM_MTD
select REGMAP
select SYSCON
imply CMD_NAND
help
This enables the driver for the NAND flash device found on

View file

@ -22,6 +22,10 @@
#include <linux/mtd/mtd.h>
#include <linux/mtd/rawnand.h>
#include <linux/types.h>
#include <syscon.h>
#include <regmap.h>
#include <dm/uclass.h>
#include <dm/read.h>
#include "pxa3xx_nand.h"
@ -117,6 +121,10 @@ DECLARE_GLOBAL_DATA_PTR;
#define EXT_CMD_TYPE_LAST_RW 1 /* Last naked read/write */
#define EXT_CMD_TYPE_MONO 0 /* Monolithic read/write */
/* System control register and bit to enable NAND on some SoCs */
#define GENCONF_SOC_DEVICE_MUX 0x208
#define GENCONF_SOC_DEVICE_MUX_NFC_EN BIT(0)
/*
* This should be large enough to read 'ONFI' and 'JEDEC'.
* Let's use 7 bytes, which is the maximum ID count supported
@ -157,6 +165,7 @@ enum {
enum pxa3xx_nand_variant {
PXA3XX_NAND_VARIANT_PXA,
PXA3XX_NAND_VARIANT_ARMADA370,
PXA3XX_NAND_VARIANT_ARMADA_8K,
};
struct pxa3xx_nand_host {
@ -417,10 +426,21 @@ static struct nand_ecclayout ecc_layout_8KB_bch8bit = {
/* convert nano-seconds to nand flash controller clock cycles */
#define ns2cycle(ns, clk) (int)((ns) * (clk / 1000000) / 1000)
static enum pxa3xx_nand_variant pxa3xx_nand_get_variant(void)
static const struct udevice_id pxa3xx_nand_dt_ids[] = {
{
.compatible = "marvell,mvebu-pxa3xx-nand",
.data = PXA3XX_NAND_VARIANT_ARMADA370,
},
{
.compatible = "marvell,armada-8k-nand-controller",
.data = PXA3XX_NAND_VARIANT_ARMADA_8K,
},
{}
};
static enum pxa3xx_nand_variant pxa3xx_nand_get_variant(struct udevice *dev)
{
/* We only support the Armada 370/XP/38x for now */
return PXA3XX_NAND_VARIANT_ARMADA370;
return dev_get_driver_data(dev);
}
static void pxa3xx_nand_set_timing(struct pxa3xx_nand_host *host,
@ -697,7 +717,8 @@ static irqreturn_t pxa3xx_nand_irq(struct pxa3xx_nand_info *info)
info->retcode = ERR_UNCORERR;
if (status & NDSR_CORERR) {
info->retcode = ERR_CORERR;
if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370 &&
if ((info->variant == PXA3XX_NAND_VARIANT_ARMADA370 ||
info->variant == PXA3XX_NAND_VARIANT_ARMADA_8K) &&
info->ecc_bch)
info->ecc_err_cnt = NDSR_ERR_CNT(status);
else
@ -752,7 +773,8 @@ static irqreturn_t pxa3xx_nand_irq(struct pxa3xx_nand_info *info)
nand_writel(info, NDCB0, info->ndcb2);
/* NDCB3 register is available in NFCv2 (Armada 370/XP SoC) */
if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370)
if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370 ||
info->variant == PXA3XX_NAND_VARIANT_ARMADA_8K)
nand_writel(info, NDCB0, info->ndcb3);
}
@ -1666,7 +1688,8 @@ static int pxa3xx_nand_scan(struct mtd_info *mtd)
}
/* Device detection must be done with ECC disabled */
if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370)
if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370 ||
info->variant == PXA3XX_NAND_VARIANT_ARMADA_8K)
nand_writel(info, NDECCCTRL, 0x0);
if (nand_scan_ident(mtd, 1, NULL))
@ -1716,7 +1739,8 @@ static int pxa3xx_nand_scan(struct mtd_info *mtd)
* (aka split) command handling,
*/
if (mtd->writesize > info->chunk_size) {
if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370) {
if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370 ||
info->variant == PXA3XX_NAND_VARIANT_ARMADA_8K) {
chip->cmdfunc = nand_cmdfunc_extended;
} else {
dev_err(mtd->dev,
@ -1752,19 +1776,19 @@ static int pxa3xx_nand_scan(struct mtd_info *mtd)
return nand_scan_tail(mtd);
}
static int alloc_nand_resource(struct pxa3xx_nand_info *info)
static int alloc_nand_resource(struct udevice *dev, struct pxa3xx_nand_info *info)
{
struct pxa3xx_nand_platform_data *pdata;
struct pxa3xx_nand_host *host;
struct nand_chip *chip = NULL;
struct mtd_info *mtd;
int ret, cs;
int cs;
pdata = info->pdata;
if (pdata->num_cs <= 0)
return -ENODEV;
info->variant = pxa3xx_nand_get_variant();
info->variant = pxa3xx_nand_get_variant(dev);
for (cs = 0; cs < pdata->num_cs; cs++) {
chip = (struct nand_chip *)
((u8 *)&info[1] + sizeof(*host) * cs);
@ -1794,97 +1818,87 @@ static int alloc_nand_resource(struct pxa3xx_nand_info *info)
/* Allocate a buffer to allow flash detection */
info->buf_size = INIT_BUFFER_SIZE;
info->data_buff = kmalloc(info->buf_size, GFP_KERNEL);
if (info->data_buff == NULL) {
ret = -ENOMEM;
goto fail_disable_clk;
}
if (info->data_buff == NULL)
return -ENOMEM;
/* initialize all interrupts to be disabled */
disable_int(info, NDSR_MASK);
return 0;
/*
* Some SoCs like A7k/A8k need to enable manually the NAND
* controller to avoid being bootloader dependent. This is done
* through the use of a single bit in the System Functions registers.
*/
if (pxa3xx_nand_get_variant(dev) == PXA3XX_NAND_VARIANT_ARMADA_8K) {
struct regmap *sysctrl_base = syscon_regmap_lookup_by_phandle(
dev, "marvell,system-controller");
u32 reg;
kfree(info->data_buff);
fail_disable_clk:
return ret;
if (IS_ERR(sysctrl_base))
return PTR_ERR(sysctrl_base);
regmap_read(sysctrl_base, GENCONF_SOC_DEVICE_MUX, &reg);
reg |= GENCONF_SOC_DEVICE_MUX_NFC_EN;
regmap_write(sysctrl_base, GENCONF_SOC_DEVICE_MUX, reg);
}
return 0;
}
static int pxa3xx_nand_probe_dt(struct pxa3xx_nand_info *info)
static int pxa3xx_nand_probe_dt(struct udevice *dev, struct pxa3xx_nand_info *info)
{
struct pxa3xx_nand_platform_data *pdata;
const void *blob = gd->fdt_blob;
int node = -1;
pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
if (!pdata)
return -ENOMEM;
/* Get address decoding nodes from the FDT blob */
do {
node = fdt_node_offset_by_compatible(blob, node,
"marvell,mvebu-pxa3xx-nand");
if (node < 0)
break;
info->mmio_base = dev_read_addr_ptr(dev);
/* Bypass disabeld nodes */
if (!fdtdec_get_is_enabled(blob, node))
continue;
pdata->num_cs = dev_read_u32_default(dev, "num-cs", 1);
if (pdata->num_cs != 1) {
pr_err("pxa3xx driver supports single CS only\n");
return -EINVAL;
}
/* Get the first enabled NAND controler base address */
info->mmio_base =
(void __iomem *)fdtdec_get_addr_size_auto_noparent(
blob, node, "reg", 0, NULL, true);
if (dev_read_bool(dev, "nand-enable-arbiter"))
pdata->enable_arbiter = 1;
pdata->num_cs = fdtdec_get_int(blob, node, "num-cs", 1);
if (pdata->num_cs != 1) {
pr_err("pxa3xx driver supports single CS only\n");
break;
}
if (dev_read_bool(dev, "nand-keep-config"))
pdata->keep_config = 1;
if (fdtdec_get_bool(blob, node, "nand-enable-arbiter"))
pdata->enable_arbiter = 1;
/*
* ECC parameters.
* If these are not set, they will be selected according
* to the detected flash type.
*/
/* ECC strength */
pdata->ecc_strength = dev_read_u32_default(dev, "nand-ecc-strength", 0);
if (fdtdec_get_bool(blob, node, "nand-keep-config"))
pdata->keep_config = 1;
/* ECC step size */
pdata->ecc_step_size = dev_read_u32_default(dev, "nand-ecc-step-size",
0);
/*
* ECC parameters.
* If these are not set, they will be selected according
* to the detected flash type.
*/
/* ECC strength */
pdata->ecc_strength = fdtdec_get_int(blob, node,
"nand-ecc-strength", 0);
info->pdata = pdata;
/* ECC step size */
pdata->ecc_step_size = fdtdec_get_int(blob, node,
"nand-ecc-step-size", 0);
info->pdata = pdata;
/* Currently support only a single NAND controller */
return 0;
} while (node >= 0);
return -EINVAL;
return 0;
}
static int pxa3xx_nand_probe(struct pxa3xx_nand_info *info)
static int pxa3xx_nand_probe(struct udevice *dev)
{
struct mtd_info *mtd = &info->controller.active->mtd;
struct pxa3xx_nand_platform_data *pdata;
int ret, cs, probe_success;
struct pxa3xx_nand_info *info = dev_get_priv(dev);
ret = pxa3xx_nand_probe_dt(info);
ret = pxa3xx_nand_probe_dt(dev, info);
if (ret)
return ret;
pdata = info->pdata;
ret = alloc_nand_resource(info);
ret = alloc_nand_resource(dev, info);
if (ret) {
dev_err(mtd->dev, "alloc nand resource failed\n");
dev_err(dev, "alloc nand resource failed\n");
return ret;
}
@ -1918,22 +1932,24 @@ static int pxa3xx_nand_probe(struct pxa3xx_nand_info *info)
return 0;
}
/*
* Main initialization routine
*/
U_BOOT_DRIVER(pxa3xx_nand) = {
.name = "pxa3xx-nand",
.id = UCLASS_MTD,
.of_match = pxa3xx_nand_dt_ids,
.probe = pxa3xx_nand_probe,
.priv_auto_alloc_size = sizeof(struct pxa3xx_nand_info) +
sizeof(struct pxa3xx_nand_host) * CONFIG_SYS_MAX_NAND_DEVICE,
};
void board_nand_init(void)
{
struct pxa3xx_nand_info *info;
struct pxa3xx_nand_host *host;
struct udevice *dev;
int ret;
info = kzalloc(sizeof(*info) +
sizeof(*host) * CONFIG_SYS_MAX_NAND_DEVICE,
GFP_KERNEL);
if (!info)
return;
ret = pxa3xx_nand_probe(info);
if (ret)
return;
ret = uclass_get_device_by_driver(UCLASS_MTD,
DM_GET_DRIVER(pxa3xx_nand), &dev);
if (ret && ret != -ENODEV) {
pr_err("Failed to initialize %s. (error %d)\n", dev->name,
ret);
}
}

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