mirror of
https://github.com/Fishwaldo/u-boot.git
synced 2025-03-17 12:41:32 +00:00
- Armada 8k: Add NAND support via PXA3xx NAND driver (Baruch) - Armada 8k: Use ATF serdes init instead of the "old" U-Boot version (Baruch) - Minor update to Octeon TX/TX2 defconfig (Stefan)
This commit is contained in:
commit
8d7f3fcb4a
9 changed files with 238 additions and 1254 deletions
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@ -285,15 +285,18 @@
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};
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cpm_nand: nand@720000 {
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compatible = "marvell,mvebu-pxa3xx-nand";
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reg = <0x720000 0x100>;
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compatible = "marvell,armada-8k-nand-controller",
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"marvell,armada370-nand-controller";
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reg = <0x720000 0x54>;
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#address-cells = <1>;
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clocks = <&cpm_syscon0 1 2>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "core", "reg";
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clocks = <&cpm_syscon0 1 2>,
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<&cpm_syscon0 1 17>;
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marvell,system-controller = <&cpm_syscon0>;
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nand-enable-arbiter;
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num-cs = <1>;
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nand-ecc-strength = <4>;
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nand-ecc-step-size = <512>;
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status = "disabled";
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};
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@ -267,6 +267,22 @@
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utmi-port = <UTMI_PHY_TO_USB3_HOST0>;
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status = "disabled";
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};
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cps_nand: nand@720000 {
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compatible = "marvell,armada-8k-nand-controller",
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"marvell,armada370-nand-controller";
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reg = <0x720000 0x54>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "core", "reg";
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clocks = <&cps_syscon0 1 2>,
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<&cps_syscon0 1 17>;
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marvell,system-controller = <&cps_syscon0>;
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nand-enable-arbiter;
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num-cs = <1>;
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status = "disabled";
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};
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};
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cps_pcie0: pcie@f4600000 {
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@ -86,6 +86,8 @@ CONFIG_SPI_FLASH_MACRONIX=y
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CONFIG_SPI_FLASH_SPANSION=y
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CONFIG_SPI_FLASH_STMICRO=y
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CONFIG_DM_ETH=y
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CONFIG_NET_OCTEONTX2=y
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CONFIG_OCTEONTX_SMI=y
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CONFIG_PCI=y
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CONFIG_DM_PCI=y
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CONFIG_DM_PCI_COMPAT=y
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@ -99,6 +99,8 @@ CONFIG_DM_ETH=y
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CONFIG_E1000=y
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CONFIG_E1000_SPI=y
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CONFIG_CMD_E1000=y
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CONFIG_NET_OCTEONTX2=y
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CONFIG_OCTEONTX_SMI=y
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CONFIG_NVME=y
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CONFIG_PCI=y
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CONFIG_DM_PCI=y
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@ -100,6 +100,8 @@ CONFIG_DM_ETH=y
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CONFIG_E1000=y
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CONFIG_E1000_SPI=y
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CONFIG_CMD_E1000=y
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CONFIG_NET_OCTEONTX=y
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CONFIG_OCTEONTX_SMI=y
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CONFIG_NVME=y
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CONFIG_PCI=y
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CONFIG_DM_PCI=y
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@ -97,6 +97,8 @@ CONFIG_DM_ETH=y
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CONFIG_E1000=y
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CONFIG_E1000_SPI=y
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CONFIG_CMD_E1000=y
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CONFIG_NET_OCTEONTX=y
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CONFIG_OCTEONTX_SMI=y
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CONFIG_NVME=y
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CONFIG_PCI=y
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CONFIG_DM_PCI=y
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@ -195,6 +195,9 @@ endif
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config NAND_PXA3XX
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bool "Support for NAND on PXA3xx and Armada 370/XP/38x"
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select SYS_NAND_SELF_INIT
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select DM_MTD
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select REGMAP
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select SYSCON
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imply CMD_NAND
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help
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This enables the driver for the NAND flash device found on
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@ -22,6 +22,10 @@
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/rawnand.h>
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#include <linux/types.h>
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#include <syscon.h>
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#include <regmap.h>
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#include <dm/uclass.h>
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#include <dm/read.h>
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#include "pxa3xx_nand.h"
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@ -117,6 +121,10 @@ DECLARE_GLOBAL_DATA_PTR;
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#define EXT_CMD_TYPE_LAST_RW 1 /* Last naked read/write */
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#define EXT_CMD_TYPE_MONO 0 /* Monolithic read/write */
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/* System control register and bit to enable NAND on some SoCs */
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#define GENCONF_SOC_DEVICE_MUX 0x208
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#define GENCONF_SOC_DEVICE_MUX_NFC_EN BIT(0)
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/*
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* This should be large enough to read 'ONFI' and 'JEDEC'.
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* Let's use 7 bytes, which is the maximum ID count supported
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@ -157,6 +165,7 @@ enum {
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enum pxa3xx_nand_variant {
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PXA3XX_NAND_VARIANT_PXA,
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PXA3XX_NAND_VARIANT_ARMADA370,
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PXA3XX_NAND_VARIANT_ARMADA_8K,
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};
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struct pxa3xx_nand_host {
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@ -417,10 +426,21 @@ static struct nand_ecclayout ecc_layout_8KB_bch8bit = {
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/* convert nano-seconds to nand flash controller clock cycles */
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#define ns2cycle(ns, clk) (int)((ns) * (clk / 1000000) / 1000)
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static enum pxa3xx_nand_variant pxa3xx_nand_get_variant(void)
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static const struct udevice_id pxa3xx_nand_dt_ids[] = {
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{
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.compatible = "marvell,mvebu-pxa3xx-nand",
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.data = PXA3XX_NAND_VARIANT_ARMADA370,
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},
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{
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.compatible = "marvell,armada-8k-nand-controller",
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.data = PXA3XX_NAND_VARIANT_ARMADA_8K,
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},
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{}
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};
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static enum pxa3xx_nand_variant pxa3xx_nand_get_variant(struct udevice *dev)
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{
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/* We only support the Armada 370/XP/38x for now */
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return PXA3XX_NAND_VARIANT_ARMADA370;
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return dev_get_driver_data(dev);
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}
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static void pxa3xx_nand_set_timing(struct pxa3xx_nand_host *host,
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@ -697,7 +717,8 @@ static irqreturn_t pxa3xx_nand_irq(struct pxa3xx_nand_info *info)
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info->retcode = ERR_UNCORERR;
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if (status & NDSR_CORERR) {
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info->retcode = ERR_CORERR;
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if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370 &&
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if ((info->variant == PXA3XX_NAND_VARIANT_ARMADA370 ||
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info->variant == PXA3XX_NAND_VARIANT_ARMADA_8K) &&
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info->ecc_bch)
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info->ecc_err_cnt = NDSR_ERR_CNT(status);
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else
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@ -752,7 +773,8 @@ static irqreturn_t pxa3xx_nand_irq(struct pxa3xx_nand_info *info)
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nand_writel(info, NDCB0, info->ndcb2);
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/* NDCB3 register is available in NFCv2 (Armada 370/XP SoC) */
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if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370)
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if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370 ||
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info->variant == PXA3XX_NAND_VARIANT_ARMADA_8K)
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nand_writel(info, NDCB0, info->ndcb3);
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}
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@ -1666,7 +1688,8 @@ static int pxa3xx_nand_scan(struct mtd_info *mtd)
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}
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/* Device detection must be done with ECC disabled */
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if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370)
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if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370 ||
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info->variant == PXA3XX_NAND_VARIANT_ARMADA_8K)
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nand_writel(info, NDECCCTRL, 0x0);
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if (nand_scan_ident(mtd, 1, NULL))
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@ -1716,7 +1739,8 @@ static int pxa3xx_nand_scan(struct mtd_info *mtd)
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* (aka split) command handling,
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*/
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if (mtd->writesize > info->chunk_size) {
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if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370) {
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if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370 ||
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info->variant == PXA3XX_NAND_VARIANT_ARMADA_8K) {
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chip->cmdfunc = nand_cmdfunc_extended;
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} else {
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dev_err(mtd->dev,
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@ -1752,19 +1776,19 @@ static int pxa3xx_nand_scan(struct mtd_info *mtd)
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return nand_scan_tail(mtd);
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}
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static int alloc_nand_resource(struct pxa3xx_nand_info *info)
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static int alloc_nand_resource(struct udevice *dev, struct pxa3xx_nand_info *info)
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{
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struct pxa3xx_nand_platform_data *pdata;
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struct pxa3xx_nand_host *host;
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struct nand_chip *chip = NULL;
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struct mtd_info *mtd;
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int ret, cs;
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int cs;
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pdata = info->pdata;
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if (pdata->num_cs <= 0)
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return -ENODEV;
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info->variant = pxa3xx_nand_get_variant();
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info->variant = pxa3xx_nand_get_variant(dev);
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for (cs = 0; cs < pdata->num_cs; cs++) {
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chip = (struct nand_chip *)
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((u8 *)&info[1] + sizeof(*host) * cs);
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@ -1794,97 +1818,87 @@ static int alloc_nand_resource(struct pxa3xx_nand_info *info)
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/* Allocate a buffer to allow flash detection */
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info->buf_size = INIT_BUFFER_SIZE;
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info->data_buff = kmalloc(info->buf_size, GFP_KERNEL);
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if (info->data_buff == NULL) {
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ret = -ENOMEM;
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goto fail_disable_clk;
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}
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if (info->data_buff == NULL)
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return -ENOMEM;
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/* initialize all interrupts to be disabled */
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disable_int(info, NDSR_MASK);
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return 0;
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/*
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* Some SoCs like A7k/A8k need to enable manually the NAND
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* controller to avoid being bootloader dependent. This is done
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* through the use of a single bit in the System Functions registers.
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*/
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if (pxa3xx_nand_get_variant(dev) == PXA3XX_NAND_VARIANT_ARMADA_8K) {
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struct regmap *sysctrl_base = syscon_regmap_lookup_by_phandle(
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dev, "marvell,system-controller");
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u32 reg;
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kfree(info->data_buff);
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fail_disable_clk:
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return ret;
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if (IS_ERR(sysctrl_base))
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return PTR_ERR(sysctrl_base);
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regmap_read(sysctrl_base, GENCONF_SOC_DEVICE_MUX, ®);
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reg |= GENCONF_SOC_DEVICE_MUX_NFC_EN;
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regmap_write(sysctrl_base, GENCONF_SOC_DEVICE_MUX, reg);
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}
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return 0;
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}
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static int pxa3xx_nand_probe_dt(struct pxa3xx_nand_info *info)
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static int pxa3xx_nand_probe_dt(struct udevice *dev, struct pxa3xx_nand_info *info)
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{
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struct pxa3xx_nand_platform_data *pdata;
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const void *blob = gd->fdt_blob;
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int node = -1;
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pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
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if (!pdata)
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return -ENOMEM;
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/* Get address decoding nodes from the FDT blob */
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do {
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node = fdt_node_offset_by_compatible(blob, node,
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"marvell,mvebu-pxa3xx-nand");
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if (node < 0)
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break;
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info->mmio_base = dev_read_addr_ptr(dev);
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/* Bypass disabeld nodes */
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if (!fdtdec_get_is_enabled(blob, node))
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continue;
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pdata->num_cs = dev_read_u32_default(dev, "num-cs", 1);
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if (pdata->num_cs != 1) {
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pr_err("pxa3xx driver supports single CS only\n");
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return -EINVAL;
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}
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/* Get the first enabled NAND controler base address */
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info->mmio_base =
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(void __iomem *)fdtdec_get_addr_size_auto_noparent(
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blob, node, "reg", 0, NULL, true);
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if (dev_read_bool(dev, "nand-enable-arbiter"))
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pdata->enable_arbiter = 1;
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pdata->num_cs = fdtdec_get_int(blob, node, "num-cs", 1);
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if (pdata->num_cs != 1) {
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pr_err("pxa3xx driver supports single CS only\n");
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break;
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}
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if (dev_read_bool(dev, "nand-keep-config"))
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pdata->keep_config = 1;
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if (fdtdec_get_bool(blob, node, "nand-enable-arbiter"))
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pdata->enable_arbiter = 1;
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/*
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* ECC parameters.
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* If these are not set, they will be selected according
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* to the detected flash type.
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*/
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/* ECC strength */
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pdata->ecc_strength = dev_read_u32_default(dev, "nand-ecc-strength", 0);
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if (fdtdec_get_bool(blob, node, "nand-keep-config"))
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pdata->keep_config = 1;
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/* ECC step size */
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pdata->ecc_step_size = dev_read_u32_default(dev, "nand-ecc-step-size",
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0);
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/*
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* ECC parameters.
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* If these are not set, they will be selected according
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* to the detected flash type.
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*/
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/* ECC strength */
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pdata->ecc_strength = fdtdec_get_int(blob, node,
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"nand-ecc-strength", 0);
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info->pdata = pdata;
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/* ECC step size */
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pdata->ecc_step_size = fdtdec_get_int(blob, node,
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"nand-ecc-step-size", 0);
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info->pdata = pdata;
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/* Currently support only a single NAND controller */
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return 0;
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} while (node >= 0);
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return -EINVAL;
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return 0;
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}
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static int pxa3xx_nand_probe(struct pxa3xx_nand_info *info)
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static int pxa3xx_nand_probe(struct udevice *dev)
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{
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struct mtd_info *mtd = &info->controller.active->mtd;
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struct pxa3xx_nand_platform_data *pdata;
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int ret, cs, probe_success;
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struct pxa3xx_nand_info *info = dev_get_priv(dev);
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ret = pxa3xx_nand_probe_dt(info);
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ret = pxa3xx_nand_probe_dt(dev, info);
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if (ret)
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return ret;
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pdata = info->pdata;
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ret = alloc_nand_resource(info);
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ret = alloc_nand_resource(dev, info);
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if (ret) {
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dev_err(mtd->dev, "alloc nand resource failed\n");
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dev_err(dev, "alloc nand resource failed\n");
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return ret;
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}
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@ -1918,22 +1932,24 @@ static int pxa3xx_nand_probe(struct pxa3xx_nand_info *info)
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return 0;
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}
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/*
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* Main initialization routine
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*/
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U_BOOT_DRIVER(pxa3xx_nand) = {
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.name = "pxa3xx-nand",
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.id = UCLASS_MTD,
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.of_match = pxa3xx_nand_dt_ids,
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.probe = pxa3xx_nand_probe,
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.priv_auto_alloc_size = sizeof(struct pxa3xx_nand_info) +
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sizeof(struct pxa3xx_nand_host) * CONFIG_SYS_MAX_NAND_DEVICE,
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};
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void board_nand_init(void)
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{
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struct pxa3xx_nand_info *info;
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struct pxa3xx_nand_host *host;
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struct udevice *dev;
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int ret;
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info = kzalloc(sizeof(*info) +
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sizeof(*host) * CONFIG_SYS_MAX_NAND_DEVICE,
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GFP_KERNEL);
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if (!info)
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return;
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ret = pxa3xx_nand_probe(info);
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if (ret)
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return;
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ret = uclass_get_device_by_driver(UCLASS_MTD,
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DM_GET_DRIVER(pxa3xx_nand), &dev);
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if (ret && ret != -ENODEV) {
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pr_err("Failed to initialize %s. (error %d)\n", dev->name,
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ret);
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}
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}
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