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board: ge: bx50v3: Enable CONFIG_DM_SPI, CONFIG_DM_SPI_FLASH
Use SPI flash device model, and remove SPI pin configuration code since the pinctrl driver is used. Signed-off-by: Ian Ray <ian.ray@ge.com>
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parent
06f2e030d0
commit
8d8d3540eb
3 changed files with 29 additions and 25 deletions
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@ -8,6 +8,7 @@
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/dts-v1/;
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#include "imx6q.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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/ {
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model = "General Electric Bx50v3";
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@ -17,6 +18,16 @@
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&iomuxc {
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pinctrl-names = "default";
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pinctrl_ecspi1: ecspi1grp {
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fsl,pins = <
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MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
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MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
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MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
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/* SPI1 CS */
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MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0
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>;
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};
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pinctrl_usdhc3: usdhc3grp {
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fsl,pins = <
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MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
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@ -60,3 +71,19 @@
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&usdhc4 {
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status = "disabled";
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};
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/* SPI NOR */
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&ecspi1 {
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cs-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ecspi1>;
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status = "okay";
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flash: n25q032@0 {
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compatible = "jedec,spi-nor";
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#address-cells = <1>;
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#size-cells = <1>;
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spi-max-frequency = <20000000>;
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reg = <0>;
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};
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};
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@ -53,9 +53,6 @@ static struct vpd_cache vpd;
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#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
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PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST)
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#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
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PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
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#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
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PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
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PAD_CTL_ODE | PAD_CTL_SRE_FAST)
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@ -113,13 +110,6 @@ static void setup_iomux_enet(void)
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mdelay(1);
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}
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static iomux_v3_cfg_t const ecspi1_pads[] = {
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MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
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MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
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MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
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MX6_PAD_EIM_EB2__GPIO2_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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static struct i2c_pads_info i2c_pad_info1 = {
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.scl = {
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.i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | I2C_PAD,
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@ -159,18 +149,6 @@ static struct i2c_pads_info i2c_pad_info3 = {
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}
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};
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#ifdef CONFIG_MXC_SPI
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int board_spi_cs_gpio(unsigned bus, unsigned cs)
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{
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return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(2, 30)) : -1;
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}
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static void setup_spi(void)
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{
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imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
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}
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#endif
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static iomux_v3_cfg_t const pcie_pads[] = {
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MX6_PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),
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@ -594,9 +572,6 @@ int board_init(void)
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/* address of boot parameters */
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gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
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#ifdef CONFIG_MXC_SPI
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setup_spi();
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#endif
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return 0;
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}
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@ -59,3 +59,5 @@ CONFIG_BLK=y
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CONFIG_PINCTRL=y
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CONFIG_PINCTRL_IMX6=y
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CONFIG_DM_GPIO=y
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CONFIG_DM_SPI=y
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CONFIG_DM_SPI_FLASH=y
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