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[Blackfin][PATCH] code cleanup

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This commit is contained in:
Aubrey Li 2007-03-10 23:49:29 +08:00
parent ef26a08fef
commit 8db13d6315
19 changed files with 509 additions and 542 deletions
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4
board/bf533-ezkit/Makefile
View file

@ -1,9 +1,9 @@
#
# U-boot - Makefile
#
# Copyright (c) 2005-2007 Analog Device Inc.
# Copyright (c) 2007 Analog Device Inc.
#
# (C) Copyright 2000-2004
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this

1
board/bf533-ezkit/u-boot.lds.S
View file

@ -150,4 +150,3 @@ SECTIONS
_end = . ;
PROVIDE (end = .);
}

4
board/bf533-stamp/Makefile
View file

@ -1,9 +1,9 @@
#
# U-boot - Makefile
#
# Copyright (c) 2005-2007 Analog Device Inc.
# Copyright (c) 2007 Analog Device Inc.
#
# (C) Copyright 2000-2004
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this

1
board/bf533-stamp/u-boot.lds.S
View file

@ -150,4 +150,3 @@ SECTIONS
_end = . ;
PROVIDE (end = .);
}

1
cpu/bf533/init_sdram.S
View file

@ -177,4 +177,3 @@ skip:
RETS = [SP++];
ASTAT = [SP++];
RTS;

2
cpu/bf533/init_sdram_bootrom_initblock.S
View file

@ -172,10 +172,8 @@ skip:
SSYNC;
nop;
(P5:0) = [SP++];
(R7:0) = [SP++];
RETS = [SP++];
ASTAT = [SP++];
RTS;

31
include/asm-blackfin/arch-common/cdef_LPBlackfin.h
View file

@ -14,14 +14,11 @@
#endif
#include <asm/arch-common/def_LPBlackfin.h>
// Cache & SRAM Memory
/* Cache & SRAM Memory */
#define pSRAM_BASE_ADDRESS ((volatile void **)SRAM_BASE_ADDRESS)
#define pDMEM_CONTROL ((volatile unsigned long *)DMEM_CONTROL)
#define pDCPLB_STATUS ((volatile unsigned long *)DCPLB_STATUS)
#define pDCPLB_FAULT_ADDR ((volatile void **)DCPLB_FAULT_ADDR)
/*
#define MMR_TIMEOUT 0xFFE00010 // Memory-Mapped Register Timeout Register
*/
#define pDCPLB_ADDR0 ((volatile void **)DCPLB_ADDR0)
#define pDCPLB_ADDR1 ((volatile void **)DCPLB_ADDR1)
#define pDCPLB_ADDR2 ((volatile void **)DCPLB_ADDR2)
@ -55,15 +52,8 @@
#define pDCPLB_DATA14 ((volatile unsigned long *)DCPLB_DATA14)
#define pDCPLB_DATA15 ((volatile unsigned long *)DCPLB_DATA15)
#define pDTEST_COMMAND ((volatile unsigned long *)DTEST_COMMAND)
/*
#define DTEST_INDEX 0xFFE00304 // Data Test Index Register
*/
#define pDTEST_DATA0 ((volatile unsigned long *)DTEST_DATA0)
#define pDTEST_DATA1 ((volatile unsigned long *)DTEST_DATA1)
/*
#define DTEST_DATA2 0xFFE00408 // Data Test Data Register
#define DTEST_DATA3 0xFFE0040C // Data Test Data Register
*/
#define pIMEM_CONTROL ((volatile unsigned long *)IMEM_CONTROL)
#define pICPLB_STATUS ((volatile unsigned long *)ICPLB_STATUS)
#define pICPLB_FAULT_ADDR ((volatile void **)ICPLB_FAULT_ADDR)
@ -100,13 +90,10 @@
#define pICPLB_DATA14 ((volatile unsigned long *)ICPLB_DATA14)
#define pICPLB_DATA15 ((volatile unsigned long *)ICPLB_DATA15)
#define pITEST_COMMAND ((volatile unsigned long *)ITEST_COMMAND)
/*
#define ITEST_INDEX 0xFFE01304 // Instruction Test Index Register
*/
#define pITEST_DATA0 ((volatile unsigned long *)ITEST_DATA0)
#define pITEST_DATA1 ((volatile unsigned long *)ITEST_DATA1)
// Event/Interrupt Registers
/* Event/Interrupt Registers */
#define pEVT0 ((volatile void **)EVT0)
#define pEVT1 ((volatile void **)EVT1)
#define pEVT2 ((volatile void **)EVT2)
@ -127,24 +114,24 @@
#define pIPEND ((volatile unsigned long *)IPEND)
#define pILAT ((volatile unsigned long *)ILAT)
// Core Timer Registers
/* Core Timer Registers */
#define pTCNTL ((volatile unsigned long *)TCNTL)
#define pTPERIOD ((volatile unsigned long *)TPERIOD)
#define pTSCALE ((volatile unsigned long *)TSCALE)
#define pTCOUNT ((volatile unsigned long *)TCOUNT)
// Debug/MP/Emulation Registers
/* Debug/MP/Emulation Registers */
#define pDSPID ((volatile unsigned long *)DSPID)
#define pDBGCTL ((volatile unsigned long *)DBGCTL)
#define pDBGSTAT ((volatile unsigned long *)DBGSTAT)
#define pEMUDAT ((volatile unsigned long *)EMUDAT)
// Trace Buffer Registers
/* Trace Buffer Registers */
#define pTBUFCTL ((volatile unsigned long *)TBUFCTL)
#define pTBUFSTAT ((volatile unsigned long *)TBUFSTAT)
#define pTBUF ((volatile void **)TBUF)
// Watch Point Control Registers
/* Watch Point Control Registers */
#define pWPIACTL ((volatile unsigned long *)WPIACTL)
#define pWPIA0 ((volatile void **)WPIA0)
#define pWPIA1 ((volatile void **)WPIA1)
@ -165,13 +152,9 @@
#define pWPDACNT1 ((volatile unsigned long *)WPDACNT1)
#define pWPSTAT ((volatile unsigned long *)WPSTAT)
// Performance Monitor Registers
/* Performance Monitor Registers */
#define pPFCTL ((volatile unsigned long *)PFCTL)
#define pPFCNTR0 ((volatile unsigned long *)PFCNTR0)
#define pPFCNTR1 ((volatile unsigned long *)PFCNTR1)
/*
#define IPRIO 0xFFE02110 // Core Interrupt Priority Register
*/
#endif /* _CDEF_LPBLACKFIN_H */

6
include/configs/bf533-ezkit.h
View file

@ -15,7 +15,7 @@
#define CONFIG_CMDLINE_EDITING 1
#define CONFIG_LOADADDR 0x01000000 /* default load address */
#define CONFIG_BOOTCOMMAND "tftp $(loadaddr) linux"
//#define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw"
/* #define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw" */
#define CONFIG_DRIVER_SMC91111 1
#define CONFIG_SMC91111_BASE 0x20310300
@ -37,7 +37,7 @@
#define BF533_SPI_BOOT 0x0004 /* Bootmode 3: Boot from SPI flash */
/* Define the boot mode */
#define BFIN_BOOT_MODE BF533_BYPASS_BOOT
//#define BFIN_BOOT_MODE BF533_SPI_BOOT
/* #define BFIN_BOOT_MODE BF533_SPI_BOOT */
#define CONFIG_PANIC_HANG 1
@ -90,7 +90,7 @@
#define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ
#endif
#define CONFIG_MEM_SIZE 32 /* 128, 64, 32, 16 */
#define CONFIG_MEM_SIZ 32 /* 128, 64, 32, 16 */
#define CONFIG_MEM_ADD_WDTH 9 /* 8, 9, 10, 11 */
#define CONFIG_MEM_MT48LC16M16A2TG_75 1

16
include/configs/bf533-stamp.h
View file

@ -17,7 +17,7 @@
#define BF533_SPI_BOOT 0x0004 /* Bootmode 3: Boot from SPI flash */
/* Define the boot mode */
#define BFIN_BOOT_MODE BF533_BYPASS_BOOT
//#define BFIN_BOOT_MODE BF533_SPI_BOOT
/* #define BFIN_BOOT_MODE BF533_SPI_BOOT */
#define CONFIG_PANIC_HANG 1
@ -41,7 +41,6 @@
/*
* Board settings
*
*/
#define CONFIG_DRIVER_SMC91111 1
#define CONFIG_SMC91111_BASE 0x20300300
@ -67,7 +66,6 @@
/*
* Clock settings
*
*/
/* CONFIG_CLKIN_HZ is any value in Hz */
@ -96,10 +94,8 @@
#define CONFIG_SPI_BAUD_INITBLOCK 4
#endif
/*
* Network settings
*
*/
#if (CONFIG_DRIVER_SMC91111)
@ -121,7 +117,6 @@
/*
* Flash settings
*
*/
#define CFG_FLASH_CFI /* The flash is CFI compatible */
@ -165,7 +160,6 @@
/*
* SDRAM settings & memory map
*
*/
#define CONFIG_MEM_SIZE 128 /* 128, 64, 32, 16 */
@ -221,9 +215,9 @@
#undef CONFIG_SPI_FLASH_FAST_READ
#endif
#endif
/*
* Command settings
*
*/
#define CFG_LONGHELP 1
@ -232,6 +226,7 @@
#if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT)
#define CFG_AUTOLOAD "no" /*rarpb, bootp or dhcp commands will perform only a */
#endif
/* configuration lookup from the BOOTP/DHCP server, */
/* but not try to load any image using TFTP */
@ -261,7 +256,6 @@
CFG_CMD_JFFS2 | \
CFG_CMD_EEPROM | \
CFG_CMD_DATE)
#endif
#if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT)
@ -285,7 +279,7 @@
#define CONFIG_EXTRA_ENV_SETTINGS \
"ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \
"flashboot=bootm 0x20100000\0" \
""
"
#endif
#elif (BFIN_BOOT_MODE == BF533_SPI_BOOT)
@ -328,7 +322,6 @@
/*
* Console settings
*
*/
#define CONFIG_BAUDRATE 57600
@ -471,5 +464,4 @@
#define VDSP_ENTRY_ADDR 0xFFA00000
#endif
#endif

3
lib_blackfin/memcpy.S
View file

@ -33,9 +33,6 @@
* to the Free Software Foundation, Inc.,
* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
.align 2
.globl _memcpy_ASM;