GitHub-Mirror/u-boot
2
0
Fork 0
mirror of https://github.com/Fishwaldo/u-boot.git synced 2025-03-21 22:51:37 +00:00
Code Issues Projects Releases Packages Wiki Activity Actions

ARM: socfpga: Factor out handoff register configuration

Browse source 
Factor out the code for programming preloader handoff register values,
the ISWGRP Handoff 0 and 1. These registers later control which bridges
are enabled by the "bridge" command on Gen5 devices.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
This commit is contained in:
Marek Vasut 2019-04-16 23:05:24 +02:00
parent 6aebc0d11a
commit 8df653c325
2 changed files with 24 additions and 2 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

1
arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h
View file

@ -9,6 +9,7 @@
#include <dt-bindings/reset/altr,rst-mgr.h> #include <dt-bindings/reset/altr,rst-mgr.h>
void reset_deassert_peripherals_handoff(void); void reset_deassert_peripherals_handoff(void);
void socfpga_bridges_set_handoff_regs(bool h2f, bool lwh2f, bool f2h);
void socfpga_bridges_reset(int enable); void socfpga_bridges_reset(int enable);
struct socfpga_reset_manager { struct socfpga_reset_manager {

25
arch/arm/mach-socfpga/reset_manager_gen5.c
View file

@ -73,6 +73,28 @@ void reset_deassert_peripherals_handoff(void)
#define L3REGS_REMAP_HPS2FPGA_MASK 0x08 #define L3REGS_REMAP_HPS2FPGA_MASK 0x08
#define L3REGS_REMAP_OCRAM_MASK 0x01 #define L3REGS_REMAP_OCRAM_MASK 0x01
void socfpga_bridges_set_handoff_regs(bool h2f, bool lwh2f, bool f2h)
{
u32 brgmask = 0x0;
u32 l3rmask = L3REGS_REMAP_OCRAM_MASK;
if (h2f)
brgmask |= BIT(0);
else
l3rmask |= L3REGS_REMAP_HPS2FPGA_MASK;
if (lwh2f)
brgmask |= BIT(1);
else
l3rmask |= L3REGS_REMAP_LWHPS2FPGA_MASK;
if (f2h)
brgmask |= BIT(2);
writel(brgmask, &sysmgr_regs->iswgrp_handoff[0]);
writel(l3rmask, &sysmgr_regs->iswgrp_handoff[1]);
}
void socfpga_bridges_reset(int enable) void socfpga_bridges_reset(int enable)
{ {
const u32 l3mask = L3REGS_REMAP_LWHPS2FPGA_MASK | const u32 l3mask = L3REGS_REMAP_LWHPS2FPGA_MASK |
@ -83,8 +105,7 @@ void socfpga_bridges_reset(int enable)
/* brdmodrst */ /* brdmodrst */
writel(0xffffffff, &reset_manager_base->brg_mod_reset); writel(0xffffffff, &reset_manager_base->brg_mod_reset);
} else { } else {
writel(0, &sysmgr_regs->iswgrp_handoff[0]); socfpga_bridges_set_handoff_regs(false, false, false);
writel(l3mask, &sysmgr_regs->iswgrp_handoff[1]);
/* Check signal from FPGA. */ /* Check signal from FPGA. */
if (!fpgamgr_test_fpga_ready()) { if (!fpgamgr_test_fpga_ready()) {