GitHub-Mirror/u-boot
2
0
Fork 0
mirror of https://github.com/Fishwaldo/u-boot.git synced 2025-03-21 06:31:31 +00:00
Code Issues Projects Releases Packages Wiki Activity Actions

Merge git://git.denx.de/u-boot-imx

Browse source
This commit is contained in:
Tom Rini 2018-01-15 16:44:18 -05:00
commit 8e9801c283
45 changed files with 2113 additions and 503 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

1
arch/arm/dts/Makefile
View file

@ -385,6 +385,7 @@ dtb-$(CONFIG_MX6) += imx6ull-14x14-evk.dtb \
imx6q-icore-rqs.dtb \
imx6q-logicpd.dtb \
imx6sx-sabreauto.dtb \
imx6sx-sdb.dtb \
imx6ul-geam-kit.dtb \
imx6ul-isiot-emmc.dtb \
imx6ul-isiot-mmc.dtb \

138
arch/arm/dts/imx6sx-sdb.dts Normal file
View file

@ -0,0 +1,138 @@
/*
* Copyright (C) 2015 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include "imx6sx-sdb.dtsi"
/ {
model = "Freescale i.MX6 SoloX SDB RevB Board";
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
pmic: pfuze100@8 {
compatible = "fsl,pfuze200";
reg = <0x08>;
regulators {
sw1a_reg: sw1ab {
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1875000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <6250>;
};
sw2_reg: sw2 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
sw3a_reg: sw3a {
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1975000>;
regulator-boot-on;
regulator-always-on;
};
sw3b_reg: sw3b {
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1975000>;
regulator-boot-on;
regulator-always-on;
};
swbst_reg: swbst {
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5150000>;
};
snvs_reg: vsnvs {
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <3000000>;
regulator-boot-on;
regulator-always-on;
};
vref_reg: vrefddr {
regulator-boot-on;
regulator-always-on;
};
vgen1_reg: vgen1 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1550000>;
regulator-always-on;
};
vgen2_reg: vgen2 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1550000>;
};
vgen3_reg: vgen3 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vgen4_reg: vgen4 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vgen5_reg: vgen5 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vgen6_reg: vgen6 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
};
};
};
&qspi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_qspi2>;
status = "okay";
flash0: n25q256a@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "micron,n25q256a", "jedec,spi-nor";
spi-max-frequency = <29000000>;
reg = <0>;
};
flash1: n25q256a@1 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "micron,n25q256a", "jedec,spi-nor";
spi-max-frequency = <29000000>;
reg = <1>;
};
};
&reg_arm {
vin-supply = <&sw1a_reg>;
};
&reg_soc {
vin-supply = <&sw1a_reg>;
};

612
arch/arm/dts/imx6sx-sdb.dtsi Normal file
View file

@ -0,0 +1,612 @@
/*
* Copyright (C) 2014 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include "imx6sx.dtsi"
/ {
model = "Freescale i.MX6 SoloX SDB Board";
compatible = "fsl,imx6sx-sdb", "fsl,imx6sx";
chosen {
stdout-path = &uart1;
};
memory {
reg = <0x80000000 0x40000000>;
};
backlight {
compatible = "pwm-backlight";
pwms = <&pwm3 0 5000000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <6>;
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_keys>;
volume-up {
label = "Volume Up";
gpios = <&gpio1 18 GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEUP>;
};
volume-down {
label = "Volume Down";
gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEDOWN>;
};
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
vcc_sd3: regulator@0 {
compatible = "regulator-fixed";
reg = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_vcc_sd3>;
regulator-name = "VCC_SD3";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_usb_otg1_vbus: regulator@1 {
compatible = "regulator-fixed";
reg = <1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb_otg1>;
regulator-name = "usb_otg1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_usb_otg2_vbus: regulator@2 {
compatible = "regulator-fixed";
reg = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb_otg2>;
regulator-name = "usb_otg2_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_psu_5v: regulator@3 {
compatible = "regulator-fixed";
reg = <3>;
regulator-name = "PSU-5V0";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
reg_lcd_3v3: regulator@4 {
compatible = "regulator-fixed";
reg = <4>;
regulator-name = "lcd-3v3";
gpio = <&gpio3 27 0>;
enable-active-high;
};
reg_peri_3v3: regulator@5 {
compatible = "regulator-fixed";
reg = <5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_peri_3v3>;
regulator-name = "peri_3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio4 16 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-always-on;
};
reg_enet_3v3: regulator@6 {
compatible = "regulator-fixed";
reg = <6>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet_3v3>;
regulator-name = "enet_3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpios = <&gpio2 6 GPIO_ACTIVE_LOW>;
};
};
sound {
compatible = "fsl,imx6sx-sdb-wm8962", "fsl,imx-audio-wm8962";
model = "wm8962-audio";
ssi-controller = <&ssi2>;
audio-codec = <&codec>;
audio-routing =
"Headphone Jack", "HPOUTL",
"Headphone Jack", "HPOUTR",
"Ext Spk", "SPKOUTL",
"Ext Spk", "SPKOUTR",
"AMIC", "MICBIAS",
"IN3R", "AMIC";
mux-int-port = <2>;
mux-ext-port = <6>;
};
};
&audmux {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audmux>;
status = "okay";
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet1>;
phy-supply = <&reg_enet_3v3>;
phy-mode = "rgmii";
phy-handle = <&ethphy1>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy1: ethernet-phy@1 {
reg = <1>;
};
ethphy2: ethernet-phy@2 {
reg = <2>;
};
};
};
&fec2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet2>;
phy-mode = "rgmii";
phy-handle = <&ethphy2>;
status = "okay";
};
&i2c3 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
};
&i2c4 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4>;
status = "okay";
codec: wm8962@1a {
compatible = "wlf,wm8962";
reg = <0x1a>;
clocks = <&clks IMX6SX_CLK_AUDIO>;
DCVDD-supply = <&vgen4_reg>;
DBVDD-supply = <&vgen4_reg>;
AVDD-supply = <&vgen4_reg>;
CPVDD-supply = <&vgen4_reg>;
MICVDD-supply = <&vgen3_reg>;
PLLVDD-supply = <&vgen4_reg>;
SPKVDD1-supply = <&reg_psu_5v>;
SPKVDD2-supply = <&reg_psu_5v>;
};
};
&lcdif1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcd>;
lcd-supply = <&reg_lcd_3v3>;
display = <&display0>;
status = "okay";
display0: display0 {
bits-per-pixel = <16>;
bus-width = <24>;
display-timings {
native-mode = <&timing0>;
timing0: timing0 {
clock-frequency = <33500000>;
hactive = <800>;
vactive = <480>;
hback-porch = <89>;
hfront-porch = <164>;
vback-porch = <23>;
vfront-porch = <10>;
hsync-len = <10>;
vsync-len = <10>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <0>;
};
};
};
};
&pwm3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm3>;
status = "okay";
};
&snvs_poweroff {
status = "okay";
};
&sai1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai1>;
status = "disabled";
};
&ssi2 {
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&uart5 { /* for bluetooth */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart5>;
uart-has-rtscts;
status = "okay";
};
&usbotg1 {
vbus-supply = <&reg_usb_otg1_vbus>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb_otg1_id>;
status = "okay";
};
&usbotg2 {
vbus-supply = <&reg_usb_otg2_vbus>;
dr_mode = "host";
status = "okay";
};
&usbphy1 {
fsl,tx-d-cal = <106>;
};
&usbphy2 {
fsl,tx-d-cal = <106>;
};
&usdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;
non-removable;
no-1-8-v;
keep-power-in-suspend;
wakeup-source;
status = "okay";
};
&usdhc3 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc3>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
bus-width = <8>;
cd-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>;
keep-power-in-suspend;
wakeup-source;
vmmc-supply = <&vcc_sd3>;
status = "okay";
};
&usdhc4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc4>;
cd-gpios = <&gpio6 21 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio6 20 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
};
&iomuxc {
imx6x-sdb {
pinctrl_audmux: audmuxgrp {
fsl,pins = <
MX6SX_PAD_CSI_DATA00__AUDMUX_AUD6_TXC 0x130b0
MX6SX_PAD_CSI_DATA01__AUDMUX_AUD6_TXFS 0x130b0
MX6SX_PAD_CSI_HSYNC__AUDMUX_AUD6_TXD 0x120b0
MX6SX_PAD_CSI_VSYNC__AUDMUX_AUD6_RXD 0x130b0
MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK 0x130b0
>;
};
pinctrl_enet1: enet1grp {
fsl,pins = <
MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0xa0b1
MX6SX_PAD_ENET1_MDC__ENET1_MDC 0xa0b1
MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0xa0b1
MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0xa0b1
MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0xa0b1
MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0xa0b1
MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3 0xa0b1
MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0xa0b1
MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK 0x3081
MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x3081
MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x3081
MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 0x3081
MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x3081
MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x3081
MX6SX_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M 0x91
>;
};
pinctrl_enet_3v3: enet3v3grp {
fsl,pins = <
MX6SX_PAD_ENET2_COL__GPIO2_IO_6 0x80000000
>;
};
pinctrl_enet2: enet2grp {
fsl,pins = <
MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC 0xa0b9
MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0xa0b1
MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0xa0b1
MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2 0xa0b1
MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3 0xa0b1
MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0xa0b1
MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK 0x3081
MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x3081
MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x3081
MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2 0x3081
MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3 0x3081
MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x3081
>;
};
pinctrl_gpio_keys: gpio_keysgrp {
fsl,pins = <
MX6SX_PAD_CSI_DATA04__GPIO1_IO_18 0x17059
MX6SX_PAD_CSI_DATA05__GPIO1_IO_19 0x17059
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x4001b8b1
MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x4001b8b1
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX6SX_PAD_KEY_ROW4__I2C3_SDA 0x4001b8b1
MX6SX_PAD_KEY_COL4__I2C3_SCL 0x4001b8b1
>;
};
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX6SX_PAD_CSI_DATA07__I2C4_SDA 0x4001b8b1
MX6SX_PAD_CSI_DATA06__I2C4_SCL 0x4001b8b1
>;
};
pinctrl_lcd: lcdgrp {
fsl,pins = <
MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 0x4001b0b0
MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1 0x4001b0b0
MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2 0x4001b0b0
MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3 0x4001b0b0
MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4 0x4001b0b0
MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5 0x4001b0b0
MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6 0x4001b0b0
MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7 0x4001b0b0
MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8 0x4001b0b0
MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9 0x4001b0b0
MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10 0x4001b0b0
MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11 0x4001b0b0
MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12 0x4001b0b0
MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13 0x4001b0b0
MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14 0x4001b0b0
MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15 0x4001b0b0
MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16 0x4001b0b0
MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17 0x4001b0b0
MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18 0x4001b0b0
MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19 0x4001b0b0
MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20 0x4001b0b0
MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21 0x4001b0b0
MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22 0x4001b0b0
MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23 0x4001b0b0
MX6SX_PAD_LCD1_CLK__LCDIF1_CLK 0x4001b0b0
MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE 0x4001b0b0
MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC 0x4001b0b0
MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC 0x4001b0b0
MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x4001b0b0
>;
};
pinctrl_peri_3v3: peri3v3grp {
fsl,pins = <
MX6SX_PAD_QSPI1A_DATA0__GPIO4_IO_16 0x80000000
>;
};
pinctrl_pwm3: pwm3grp-1 {
fsl,pins = <
MX6SX_PAD_SD1_DATA2__PWM3_OUT 0x110b0
>;
};
pinctrl_qspi2: qspi2grp {
fsl,pins = <
MX6SX_PAD_NAND_WP_B__QSPI2_A_DATA_0 0x70f1
MX6SX_PAD_NAND_READY_B__QSPI2_A_DATA_1 0x70f1
MX6SX_PAD_NAND_CE0_B__QSPI2_A_DATA_2 0x70f1
MX6SX_PAD_NAND_CE1_B__QSPI2_A_DATA_3 0x70f1
MX6SX_PAD_NAND_CLE__QSPI2_A_SCLK 0x70f1
MX6SX_PAD_NAND_ALE__QSPI2_A_SS0_B 0x70f1
MX6SX_PAD_NAND_DATA01__QSPI2_B_DATA_0 0x70f1
MX6SX_PAD_NAND_DATA00__QSPI2_B_DATA_1 0x70f1
MX6SX_PAD_NAND_WE_B__QSPI2_B_DATA_2 0x70f1
MX6SX_PAD_NAND_RE_B__QSPI2_B_DATA_3 0x70f1
MX6SX_PAD_NAND_DATA02__QSPI2_B_SCLK 0x70f1
MX6SX_PAD_NAND_DATA03__QSPI2_B_SS0_B 0x70f1
>;
};
pinctrl_vcc_sd3: vccsd3grp {
fsl,pins = <
MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x17059
>;
};
pinctrl_sai1: sai1grp {
fsl,pins = <
MX6SX_PAD_CSI_DATA00__SAI1_TX_BCLK 0x130b0
MX6SX_PAD_CSI_DATA01__SAI1_TX_SYNC 0x130b0
MX6SX_PAD_CSI_HSYNC__SAI1_TX_DATA_0 0x120b0
MX6SX_PAD_CSI_VSYNC__SAI1_RX_DATA_0 0x130b0
MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK 0x130b0
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1
MX6SX_PAD_GPIO1_IO05__UART1_RX 0x1b0b1
>;
};
pinctrl_uart5: uart5grp {
fsl,pins = <
MX6SX_PAD_KEY_ROW3__UART5_RX 0x1b0b1
MX6SX_PAD_KEY_COL3__UART5_TX 0x1b0b1
MX6SX_PAD_KEY_ROW2__UART5_CTS_B 0x1b0b1
MX6SX_PAD_KEY_COL2__UART5_RTS_B 0x1b0b1
>;
};
pinctrl_usb_otg1: usbotg1grp {
fsl,pins = <
MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x10b0
>;
};
pinctrl_usb_otg1_id: usbotg1idgrp {
fsl,pins = <
MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID 0x17059
>;
};
pinctrl_usb_otg2: usbot2ggrp {
fsl,pins = <
MX6SX_PAD_GPIO1_IO12__GPIO1_IO_12 0x10b0
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x17059
MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x10059
MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x17059
MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x17059
MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x17059
MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x17059
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x17059
MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x10059
MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x17059
MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x17059
MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x17059
MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x17059
MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x17059
MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x17059
MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x17059
MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x17059
MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x17059 /* CD */
MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x17059 /* WP */
>;
};
pinctrl_usdhc3_100mhz: usdhc3grp-100mhz {
fsl,pins = <
MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170b9
MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100b9
MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170b9
MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170b9
MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170b9
MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170b9
MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170b9
MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170b9
MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170b9
MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170b9
>;
};
pinctrl_usdhc3_200mhz: usdhc3grp-200mhz {
fsl,pins = <
MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170f9
MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100f9
MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170f9
MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170f9
MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170f9
MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170f9
MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170f9
MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170f9
MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170f9
MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170f9
>;
};
pinctrl_usdhc4: usdhc4grp {
fsl,pins = <
MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059
MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059
MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059
MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059
MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059
MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059
MX6SX_PAD_SD4_DATA7__GPIO6_IO_21 0x17059 /* CD */
MX6SX_PAD_SD4_DATA6__GPIO6_IO_20 0x17059 /* WP */
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX6SX_PAD_GPIO1_IO13__WDOG1_WDOG_ANY 0x30b0
>;
};
};
};

5
arch/arm/dts/imx6ull-14x14-evk.dts
View file

@ -67,7 +67,7 @@
};
};
spi4 {
spi5 {
compatible = "spi-gpio";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi4>;
@ -455,7 +455,8 @@
flash0: n25q256a@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "micron,n25q256a";
/* compatible = "micron,n25q256a"; */
compatible = "spi-flash";
spi-max-frequency = <29000000>;
spi-nor,ddr-quad-read-dummy = <6>;
reg = <0>;

9
arch/arm/dts/imx6ull.dtsi
View file

@ -38,10 +38,11 @@
serial5 = &uart6;
serial6 = &uart7;
serial7 = &uart8;
spi0 = &ecspi1;
spi1 = &ecspi2;
spi2 = &ecspi3;
spi3 = &ecspi4;
spi0 = &qspi;
spi1 = &ecspi1;
spi2 = &ecspi2;
spi3 = &ecspi3;
spi4 = &ecspi4;
usbphy0 = &usbphy1;
usbphy1 = &usbphy2;
};

46
arch/arm/include/asm/mach-imx/hab.h
View file

@ -10,6 +10,34 @@
#include <linux/types.h>
/*
* IVT header definitions
* Security Reference Manual for i.MX 7Dual and 7Solo Applications Processors,
* Rev. 0, 03/2017
* Section : 6.7.1.1
*/
#define IVT_HEADER_MAGIC 0xD1
#define IVT_TOTAL_LENGTH 0x20
#define IVT_HEADER_V1 0x40
#define IVT_HEADER_V2 0x41
struct ivt_header {
uint8_t magic;
uint16_t length;
uint8_t version;
} __attribute__((packed));
struct ivt {
struct ivt_header hdr; /* IVT header above */
uint32_t entry; /* Absolute address of first instruction */
uint32_t reserved1; /* Reserved should be zero */
uint32_t dcd; /* Absolute address of the image DCD */
uint32_t boot; /* Absolute address of the boot data */
uint32_t self; /* Absolute address of the IVT */
uint32_t csf; /* Absolute address of the CSF */
uint32_t reserved2; /* Reserved should be zero */
};
/* -------- start of HAB API updates ------------*/
/* The following are taken from HAB4 SIS */
@ -85,6 +113,12 @@ enum hab_context {
HAB_CTX_MAX
};
enum hab_target {
HAB_TGT_MEMORY = 0x0f,
HAB_TGT_PERIPHERAL = 0xf0,
HAB_TGT_ANY = 0x55,
};
struct imx_sec_config_fuse_t {
int bank;
int word;
@ -104,6 +138,9 @@ typedef enum hab_status hab_rvt_entry_t(void);
typedef enum hab_status hab_rvt_exit_t(void);
typedef void *hab_rvt_authenticate_image_t(uint8_t, ptrdiff_t,
void **, size_t *, hab_loader_callback_f_t);
typedef enum hab_status hab_rvt_check_target_t(enum hab_target, const void *,
size_t);
typedef void hab_rvt_failsafe_t(void);
typedef void hapi_clock_init_t(void);
#define HAB_ENG_ANY 0x00 /* Select first compatible engine */
@ -130,9 +167,11 @@ typedef void hapi_clock_init_t(void);
#define HAB_RVT_ENTRY (*(uint32_t *)(HAB_RVT_BASE + 0x04))
#define HAB_RVT_EXIT (*(uint32_t *)(HAB_RVT_BASE + 0x08))
#define HAB_RVT_CHECK_TARGET (*(uint32_t *)(HAB_RVT_BASE + 0x0C))
#define HAB_RVT_AUTHENTICATE_IMAGE (*(uint32_t *)(HAB_RVT_BASE + 0x10))
#define HAB_RVT_REPORT_EVENT (*(uint32_t *)(HAB_RVT_BASE + 0x20))
#define HAB_RVT_REPORT_STATUS (*(uint32_t *)(HAB_RVT_BASE + 0x24))
#define HAB_RVT_FAILSAFE (*(uint32_t *)(HAB_RVT_BASE + 0x28))
#define HAB_RVT_REPORT_EVENT_NEW (*(uint32_t *)0x000000B8)
#define HAB_RVT_REPORT_STATUS_NEW (*(uint32_t *)0x000000BC)
@ -143,8 +182,13 @@ typedef void hapi_clock_init_t(void);
#define HAB_CID_ROM 0 /**< ROM Caller ID */
#define HAB_CID_UBOOT 1 /**< UBOOT Caller ID*/
#define IVT_SIZE 0x20
#define CSF_PAD_SIZE 0x2000
/* ----------- end of HAB API updates ------------*/
uint32_t authenticate_image(uint32_t ddr_start, uint32_t image_size);
int imx_hab_authenticate_image(uint32_t ddr_start, uint32_t image_size,
uint32_t ivt_offset);
bool imx_hab_is_enabled(void);
#endif

2
arch/arm/mach-imx/Makefile
View file

@ -28,7 +28,9 @@ obj-y += cache.o init.o
obj-$(CONFIG_SATA) += sata.o
obj-$(CONFIG_IMX_VIDEO_SKIP) += video.o
obj-$(CONFIG_IMX_RDC) += rdc-sema.o
ifneq ($(CONFIG_SPL_BUILD),y)
obj-$(CONFIG_IMX_BOOTAUX) += imx_bootaux.o
endif
obj-$(CONFIG_SECURE_BOOT) += hab.o
obj-$(CONFIG_SYSCOUNTER_TIMER) += syscounter.o
endif

481
arch/arm/mach-imx/hab.c
View file

@ -70,9 +70,40 @@
((hab_rvt_exit_t *)HAB_RVT_EXIT) \
)
#define IVT_SIZE 0x20
static inline void hab_rvt_failsafe_new(void)
{
}
#define hab_rvt_failsafe_p \
( \
(is_mx6dqp()) ? \
((hab_rvt_failsafe_t *)hab_rvt_failsafe_new) : \
(is_mx6dq() && (soc_rev() >= CHIP_REV_1_5)) ? \
((hab_rvt_failsafe_t *)hab_rvt_failsafe_new) : \
(is_mx6sdl() && (soc_rev() >= CHIP_REV_1_2)) ? \
((hab_rvt_failsafe_t *)hab_rvt_failsafe_new) : \
((hab_rvt_failsafe_t *)HAB_RVT_FAILSAFE) \
)
static inline enum hab_status hab_rvt_check_target_new(enum hab_target target,
const void *start,
size_t bytes)
{
return HAB_SUCCESS;
}
#define hab_rvt_check_target_p \
( \
(is_mx6dqp()) ? \
((hab_rvt_check_target_t *)hab_rvt_check_target_new) : \
(is_mx6dq() && (soc_rev() >= CHIP_REV_1_5)) ? \
((hab_rvt_check_target_t *)hab_rvt_check_target_new) : \
(is_mx6sdl() && (soc_rev() >= CHIP_REV_1_2)) ? \
((hab_rvt_check_target_t *)hab_rvt_check_target_new) : \
((hab_rvt_check_target_t *)HAB_RVT_CHECK_TARGET) \
)
#define ALIGN_SIZE 0x1000
#define CSF_PAD_SIZE 0x2000
#define MX6DQ_PU_IROM_MMU_EN_VAR 0x009024a8
#define MX6DLS_PU_IROM_MMU_EN_VAR 0x00901dd0
#define MX6SL_PU_IROM_MMU_EN_VAR 0x00900a18
@ -80,38 +111,30 @@
(is_soc_type(MXC_SOC_MX7ULP) ? 0x80000000 : \
(is_soc_type(MXC_SOC_MX7) ? 0x2000000 : 0x2))
/*
* +------------+ 0x0 (DDR_UIMAGE_START) -
* | Header | |
* +------------+ 0x40 |
* | | |
* | | |
* | | |
* | | |
* | Image Data | |
* . | |
* . | > Stuff to be authenticated ----+
* . | | |
* | | | |
* | | | |
* +------------+ | |
* | | | |
* | Fill Data | | |
* | | | |
* +------------+ Align to ALIGN_SIZE | |
* | IVT | | |
* +------------+ + IVT_SIZE - |
* | | |
* | CSF DATA | <---------------------------------------------------------+
* | |
* +------------+
* | |
* | Fill Data |
* | |
* +------------+ + CSF_PAD_SIZE
*/
static int ivt_header_error(const char *err_str, struct ivt_header *ivt_hdr)
{
printf("%s magic=0x%x length=0x%02x version=0x%x\n", err_str,
ivt_hdr->magic, ivt_hdr->length, ivt_hdr->version);
static bool is_hab_enabled(void);
return 1;
}
static int verify_ivt_header(struct ivt_header *ivt_hdr)
{
int result = 0;
if (ivt_hdr->magic != IVT_HEADER_MAGIC)
result = ivt_header_error("bad magic", ivt_hdr);
if (be16_to_cpu(ivt_hdr->length) != IVT_TOTAL_LENGTH)
result = ivt_header_error("bad length", ivt_hdr);
if (ivt_hdr->version != IVT_HEADER_V1 &&
ivt_hdr->version != IVT_HEADER_V2)
result = ivt_header_error("bad version", ivt_hdr);
return result;
}
#if !defined(CONFIG_SPL_BUILD)
@ -125,73 +148,81 @@ struct record {
bool any_rec_flag;
};
char *rsn_str[] = {"RSN = HAB_RSN_ANY (0x00)\n",
"RSN = HAB_ENG_FAIL (0x30)\n",
"RSN = HAB_INV_ADDRESS (0x22)\n",
"RSN = HAB_INV_ASSERTION (0x0C)\n",
"RSN = HAB_INV_CALL (0x28)\n",
"RSN = HAB_INV_CERTIFICATE (0x21)\n",
"RSN = HAB_INV_COMMAND (0x06)\n",
"RSN = HAB_INV_CSF (0x11)\n",
"RSN = HAB_INV_DCD (0x27)\n",
"RSN = HAB_INV_INDEX (0x0F)\n",
"RSN = HAB_INV_IVT (0x05)\n",
"RSN = HAB_INV_KEY (0x1D)\n",
"RSN = HAB_INV_RETURN (0x1E)\n",
"RSN = HAB_INV_SIGNATURE (0x18)\n",
"RSN = HAB_INV_SIZE (0x17)\n",
"RSN = HAB_MEM_FAIL (0x2E)\n",
"RSN = HAB_OVR_COUNT (0x2B)\n",
"RSN = HAB_OVR_STORAGE (0x2D)\n",
"RSN = HAB_UNS_ALGORITHM (0x12)\n",
"RSN = HAB_UNS_COMMAND (0x03)\n",
"RSN = HAB_UNS_ENGINE (0x0A)\n",
"RSN = HAB_UNS_ITEM (0x24)\n",
"RSN = HAB_UNS_KEY (0x1B)\n",
"RSN = HAB_UNS_PROTOCOL (0x14)\n",
"RSN = HAB_UNS_STATE (0x09)\n",
"RSN = INVALID\n",
NULL};
static char *rsn_str[] = {
"RSN = HAB_RSN_ANY (0x00)\n",
"RSN = HAB_ENG_FAIL (0x30)\n",
"RSN = HAB_INV_ADDRESS (0x22)\n",
"RSN = HAB_INV_ASSERTION (0x0C)\n",
"RSN = HAB_INV_CALL (0x28)\n",
"RSN = HAB_INV_CERTIFICATE (0x21)\n",
"RSN = HAB_INV_COMMAND (0x06)\n",
"RSN = HAB_INV_CSF (0x11)\n",
"RSN = HAB_INV_DCD (0x27)\n",
"RSN = HAB_INV_INDEX (0x0F)\n",
"RSN = HAB_INV_IVT (0x05)\n",
"RSN = HAB_INV_KEY (0x1D)\n",
"RSN = HAB_INV_RETURN (0x1E)\n",
"RSN = HAB_INV_SIGNATURE (0x18)\n",
"RSN = HAB_INV_SIZE (0x17)\n",
"RSN = HAB_MEM_FAIL (0x2E)\n",
"RSN = HAB_OVR_COUNT (0x2B)\n",
"RSN = HAB_OVR_STORAGE (0x2D)\n",
"RSN = HAB_UNS_ALGORITHM (0x12)\n",
"RSN = HAB_UNS_COMMAND (0x03)\n",
"RSN = HAB_UNS_ENGINE (0x0A)\n",
"RSN = HAB_UNS_ITEM (0x24)\n",
"RSN = HAB_UNS_KEY (0x1B)\n",
"RSN = HAB_UNS_PROTOCOL (0x14)\n",
"RSN = HAB_UNS_STATE (0x09)\n",
"RSN = INVALID\n",
NULL
};
char *sts_str[] = {"STS = HAB_SUCCESS (0xF0)\n",
"STS = HAB_FAILURE (0x33)\n",
"STS = HAB_WARNING (0x69)\n",
"STS = INVALID\n",
NULL};
static char *sts_str[] = {
"STS = HAB_SUCCESS (0xF0)\n",
"STS = HAB_FAILURE (0x33)\n",
"STS = HAB_WARNING (0x69)\n",
"STS = INVALID\n",
NULL
};
char *eng_str[] = {"ENG = HAB_ENG_ANY (0x00)\n",
"ENG = HAB_ENG_SCC (0x03)\n",
"ENG = HAB_ENG_RTIC (0x05)\n",
"ENG = HAB_ENG_SAHARA (0x06)\n",
"ENG = HAB_ENG_CSU (0x0A)\n",
"ENG = HAB_ENG_SRTC (0x0C)\n",
"ENG = HAB_ENG_DCP (0x1B)\n",
"ENG = HAB_ENG_CAAM (0x1D)\n",
"ENG = HAB_ENG_SNVS (0x1E)\n",
"ENG = HAB_ENG_OCOTP (0x21)\n",
"ENG = HAB_ENG_DTCP (0x22)\n",
"ENG = HAB_ENG_ROM (0x36)\n",
"ENG = HAB_ENG_HDCP (0x24)\n",
"ENG = HAB_ENG_RTL (0x77)\n",
"ENG = HAB_ENG_SW (0xFF)\n",
"ENG = INVALID\n",
NULL};
static char *eng_str[] = {
"ENG = HAB_ENG_ANY (0x00)\n",
"ENG = HAB_ENG_SCC (0x03)\n",
"ENG = HAB_ENG_RTIC (0x05)\n",
"ENG = HAB_ENG_SAHARA (0x06)\n",
"ENG = HAB_ENG_CSU (0x0A)\n",
"ENG = HAB_ENG_SRTC (0x0C)\n",
"ENG = HAB_ENG_DCP (0x1B)\n",
"ENG = HAB_ENG_CAAM (0x1D)\n",
"ENG = HAB_ENG_SNVS (0x1E)\n",
"ENG = HAB_ENG_OCOTP (0x21)\n",
"ENG = HAB_ENG_DTCP (0x22)\n",
"ENG = HAB_ENG_ROM (0x36)\n",
"ENG = HAB_ENG_HDCP (0x24)\n",
"ENG = HAB_ENG_RTL (0x77)\n",
"ENG = HAB_ENG_SW (0xFF)\n",
"ENG = INVALID\n",
NULL
};
char *ctx_str[] = {"CTX = HAB_CTX_ANY(0x00)\n",
"CTX = HAB_CTX_FAB (0xFF)\n",
"CTX = HAB_CTX_ENTRY (0xE1)\n",
"CTX = HAB_CTX_TARGET (0x33)\n",
"CTX = HAB_CTX_AUTHENTICATE (0x0A)\n",
"CTX = HAB_CTX_DCD (0xDD)\n",
"CTX = HAB_CTX_CSF (0xCF)\n",
"CTX = HAB_CTX_COMMAND (0xC0)\n",
"CTX = HAB_CTX_AUT_DAT (0xDB)\n",
"CTX = HAB_CTX_ASSERT (0xA0)\n",
"CTX = HAB_CTX_EXIT (0xEE)\n",
"CTX = INVALID\n",
NULL};
static char *ctx_str[] = {
"CTX = HAB_CTX_ANY(0x00)\n",
"CTX = HAB_CTX_FAB (0xFF)\n",
"CTX = HAB_CTX_ENTRY (0xE1)\n",
"CTX = HAB_CTX_TARGET (0x33)\n",
"CTX = HAB_CTX_AUTHENTICATE (0x0A)\n",
"CTX = HAB_CTX_DCD (0xDD)\n",
"CTX = HAB_CTX_CSF (0xCF)\n",
"CTX = HAB_CTX_COMMAND (0xC0)\n",
"CTX = HAB_CTX_AUT_DAT (0xDB)\n",
"CTX = HAB_CTX_ASSERT (0xA0)\n",
"CTX = HAB_CTX_EXIT (0xEE)\n",
"CTX = INVALID\n",
NULL
};
uint8_t hab_statuses[5] = {
static uint8_t hab_statuses[5] = {
HAB_STS_ANY,
HAB_FAILURE,
HAB_WARNING,
@ -199,7 +230,7 @@ uint8_t hab_statuses[5] = {
-1
};
uint8_t hab_reasons[26] = {
static uint8_t hab_reasons[26] = {
HAB_RSN_ANY,
HAB_ENG_FAIL,
HAB_INV_ADDRESS,
@ -228,7 +259,7 @@ uint8_t hab_reasons[26] = {
-1
};
uint8_t hab_contexts[12] = {
static uint8_t hab_contexts[12] = {
HAB_CTX_ANY,
HAB_CTX_FAB,
HAB_CTX_ENTRY,
@ -243,7 +274,7 @@ uint8_t hab_contexts[12] = {
-1
};
uint8_t hab_engines[16] = {
static uint8_t hab_engines[16] = {
HAB_ENG_ANY,
HAB_ENG_SCC,
HAB_ENG_RTIC,
@ -274,7 +305,7 @@ static inline uint8_t get_idx(uint8_t *list, uint8_t tgt)
return -1;
}
void process_event_record(uint8_t *event_data, size_t bytes)
static void process_event_record(uint8_t *event_data, size_t bytes)
{
struct record *rec = (struct record *)event_data;
@ -284,7 +315,7 @@ void process_event_record(uint8_t *event_data, size_t bytes)
printf("%s", eng_str[get_idx(hab_engines, rec->contents[3])]);
}
void display_event(uint8_t *event_data, size_t bytes)
static void display_event(uint8_t *event_data, size_t bytes)
{
uint32_t i;
@ -303,7 +334,7 @@ void display_event(uint8_t *event_data, size_t bytes)
process_event_record(event_data, bytes);
}
int get_hab_status(void)
static int get_hab_status(void)
{
uint32_t index = 0; /* Loop index */
uint8_t event_data[128]; /* Event data buffer */
@ -316,7 +347,7 @@ int get_hab_status(void)
hab_rvt_report_event = hab_rvt_report_event_p;
hab_rvt_report_status = hab_rvt_report_status_p;
if (is_hab_enabled())
if (imx_hab_is_enabled())
puts("\nSecure boot enabled\n");
else
puts("\nSecure boot disabled\n");
@ -348,7 +379,8 @@ int get_hab_status(void)
return 0;
}
int do_hab_status(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
static int do_hab_status(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
{
if ((argc != 1)) {
cmd_usage(cmdtp);
@ -361,22 +393,43 @@ int do_hab_status(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
}
static int do_authenticate_image(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
char * const argv[])
{
ulong addr, ivt_offset;
ulong addr, length, ivt_offset;
int rcode = 0;
if (argc < 3)
if (argc < 4)
return CMD_RET_USAGE;
addr = simple_strtoul(argv[1], NULL, 16);
ivt_offset = simple_strtoul(argv[2], NULL, 16);
length = simple_strtoul(argv[2], NULL, 16);
ivt_offset = simple_strtoul(argv[3], NULL, 16);
rcode = authenticate_image(addr, ivt_offset);
rcode = imx_hab_authenticate_image(addr, length, ivt_offset);
if (rcode == 0)
rcode = CMD_RET_SUCCESS;
else
rcode = CMD_RET_FAILURE;
return rcode;
}
static int do_hab_failsafe(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
{
hab_rvt_failsafe_t *hab_rvt_failsafe;
if (argc != 1) {
cmd_usage(cmdtp);
return 1;
}
hab_rvt_failsafe = hab_rvt_failsafe_p;
hab_rvt_failsafe();
return 0;
}
U_BOOT_CMD(
hab_status, CONFIG_SYS_MAXARGS, 1, do_hab_status,
"display HAB status",
@ -384,17 +437,23 @@ U_BOOT_CMD(
);
U_BOOT_CMD(
hab_auth_img, 3, 0, do_authenticate_image,
hab_auth_img, 4, 0, do_authenticate_image,
"authenticate image via HAB",
"addr ivt_offset\n"
"addr length ivt_offset\n"
"addr - image hex address\n"
"length - image hex length\n"
"ivt_offset - hex offset of IVT in the image"
);
U_BOOT_CMD(
hab_failsafe, CONFIG_SYS_MAXARGS, 1, do_hab_failsafe,
"run BootROM failsafe routine",
""
);
#endif /* !defined(CONFIG_SPL_BUILD) */
static bool is_hab_enabled(void)
bool imx_hab_is_enabled(void)
{
struct imx_sec_config_fuse_t *fuse =
(struct imx_sec_config_fuse_t *)&imx_sec_config_fuse;
@ -410,107 +469,133 @@ static bool is_hab_enabled(void)
return (reg & IS_HAB_ENABLED_BIT) == IS_HAB_ENABLED_BIT;
}
uint32_t authenticate_image(uint32_t ddr_start, uint32_t image_size)
int imx_hab_authenticate_image(uint32_t ddr_start, uint32_t image_size,
uint32_t ivt_offset)
{
uint32_t load_addr = 0;
size_t bytes;
ptrdiff_t ivt_offset = 0;
int result = 0;
uint32_t ivt_addr = 0;
int result = 1;
ulong start;
hab_rvt_authenticate_image_t *hab_rvt_authenticate_image;
hab_rvt_entry_t *hab_rvt_entry;
hab_rvt_exit_t *hab_rvt_exit;
hab_rvt_check_target_t *hab_rvt_check_target;
struct ivt *ivt;
struct ivt_header *ivt_hdr;
enum hab_status status;
hab_rvt_authenticate_image = hab_rvt_authenticate_image_p;
hab_rvt_entry = hab_rvt_entry_p;
hab_rvt_exit = hab_rvt_exit_p;
hab_rvt_check_target = hab_rvt_check_target_p;
if (is_hab_enabled()) {
printf("\nAuthenticate image from DDR location 0x%x...\n",
ddr_start);
hab_caam_clock_enable(1);
if (hab_rvt_entry() == HAB_SUCCESS) {
/* If not already aligned, Align to ALIGN_SIZE */
ivt_offset = (image_size + ALIGN_SIZE - 1) &
~(ALIGN_SIZE - 1);
start = ddr_start;
bytes = ivt_offset + IVT_SIZE + CSF_PAD_SIZE;
#ifdef DEBUG
printf("\nivt_offset = 0x%x, ivt addr = 0x%x\n",
ivt_offset, ddr_start + ivt_offset);
puts("Dumping IVT\n");
print_buffer(ddr_start + ivt_offset,
(void *)(ddr_start + ivt_offset),
4, 0x8, 0);
puts("Dumping CSF Header\n");
print_buffer(ddr_start + ivt_offset+IVT_SIZE,
(void *)(ddr_start + ivt_offset+IVT_SIZE),
4, 0x10, 0);
#if !defined(CONFIG_SPL_BUILD)
get_hab_status();
#endif
puts("\nCalling authenticate_image in ROM\n");
printf("\tivt_offset = 0x%x\n", ivt_offset);
printf("\tstart = 0x%08lx\n", start);
printf("\tbytes = 0x%x\n", bytes);
#endif
/*
* If the MMU is enabled, we have to notify the ROM
* code, or it won't flush the caches when needed.
* This is done, by setting the "pu_irom_mmu_enabled"
* word to 1. You can find its address by looking in
* the ROM map. This is critical for
* authenticate_image(). If MMU is enabled, without
* setting this bit, authentication will fail and may
* crash.
*/
/* Check MMU enabled */
if (is_soc_type(MXC_SOC_MX6) && get_cr() & CR_M) {
if (is_mx6dq()) {
/*
* This won't work on Rev 1.0.0 of
* i.MX6Q/D, since their ROM doesn't
* do cache flushes. don't think any
* exist, so we ignore them.
*/
if (!is_mx6dqp())
writel(1, MX6DQ_PU_IROM_MMU_EN_VAR);
} else if (is_mx6sdl()) {
writel(1, MX6DLS_PU_IROM_MMU_EN_VAR);
} else if (is_mx6sl()) {
writel(1, MX6SL_PU_IROM_MMU_EN_VAR);
}
}
load_addr = (uint32_t)hab_rvt_authenticate_image(
HAB_CID_UBOOT,
ivt_offset, (void **)&start,
(size_t *)&bytes, NULL);
if (hab_rvt_exit() != HAB_SUCCESS) {
puts("hab exit function fail\n");
load_addr = 0;
}
} else {
puts("hab entry function fail\n");
}
hab_caam_clock_enable(0);
#if !defined(CONFIG_SPL_BUILD)
get_hab_status();
#endif
} else {
if (!imx_hab_is_enabled()) {
puts("hab fuse not enabled\n");
return 0;
}
if ((!is_hab_enabled()) || (load_addr != 0))
result = 1;
printf("\nAuthenticate image from DDR location 0x%x...\n",
ddr_start);
hab_caam_clock_enable(1);
/* Calculate IVT address header */
ivt_addr = ddr_start + ivt_offset;
ivt = (struct ivt *)ivt_addr;
ivt_hdr = &ivt->hdr;
/* Verify IVT header bugging out on error */
if (verify_ivt_header(ivt_hdr))
goto hab_caam_clock_disable;
/* Verify IVT body */
if (ivt->self != ivt_addr) {
printf("ivt->self 0x%08x pointer is 0x%08x\n",
ivt->self, ivt_addr);
goto hab_caam_clock_disable;
}
start = ddr_start;
bytes = image_size;
if (hab_rvt_entry() != HAB_SUCCESS) {
puts("hab entry function fail\n");
goto hab_exit_failure_print_status;
}
status = hab_rvt_check_target(HAB_TGT_MEMORY, (void *)ddr_start, bytes);
if (status != HAB_SUCCESS) {
printf("HAB check target 0x%08x-0x%08x fail\n",
ddr_start, ddr_start + bytes);
goto hab_exit_failure_print_status;
}
#ifdef DEBUG
printf("\nivt_offset = 0x%x, ivt addr = 0x%x\n", ivt_offset, ivt_addr);
printf("ivt entry = 0x%08x, dcd = 0x%08x, csf = 0x%08x\n", ivt->entry,
ivt->dcd, ivt->csf);
puts("Dumping IVT\n");
print_buffer(ivt_addr, (void *)(ivt_addr), 4, 0x8, 0);
puts("Dumping CSF Header\n");
print_buffer(ivt->csf, (void *)(ivt->csf), 4, 0x10, 0);
#if !defined(CONFIG_SPL_BUILD)
get_hab_status();
#endif
puts("\nCalling authenticate_image in ROM\n");
printf("\tivt_offset = 0x%x\n", ivt_offset);
printf("\tstart = 0x%08lx\n", start);
printf("\tbytes = 0x%x\n", bytes);
#endif
/*
* If the MMU is enabled, we have to notify the ROM
* code, or it won't flush the caches when needed.
* This is done, by setting the "pu_irom_mmu_enabled"
* word to 1. You can find its address by looking in
* the ROM map. This is critical for
* authenticate_image(). If MMU is enabled, without
* setting this bit, authentication will fail and may
* crash.
*/
/* Check MMU enabled */
if (is_soc_type(MXC_SOC_MX6) && get_cr() & CR_M) {
if (is_mx6dq()) {
/*
* This won't work on Rev 1.0.0 of
* i.MX6Q/D, since their ROM doesn't
* do cache flushes. don't think any
* exist, so we ignore them.
*/
if (!is_mx6dqp())
writel(1, MX6DQ_PU_IROM_MMU_EN_VAR);
} else if (is_mx6sdl()) {
writel(1, MX6DLS_PU_IROM_MMU_EN_VAR);
} else if (is_mx6sl()) {
writel(1, MX6SL_PU_IROM_MMU_EN_VAR);
}
}
load_addr = (uint32_t)hab_rvt_authenticate_image(
HAB_CID_UBOOT,
ivt_offset, (void **)&start,
(size_t *)&bytes, NULL);
if (hab_rvt_exit() != HAB_SUCCESS) {
puts("hab exit function fail\n");
load_addr = 0;
}
hab_exit_failure_print_status:
#if !defined(CONFIG_SPL_BUILD)
get_hab_status();
#endif
hab_caam_clock_disable:
hab_caam_clock_enable(0);
if (load_addr != 0)
result = 0;
return result;
}

13
arch/arm/mach-imx/imx_bootaux.c
View file

@ -6,27 +6,22 @@
#include <common.h>
#include <command.h>
#include <linux/compiler.h>
/* Allow for arch specific config before we boot */
static int __arch_auxiliary_core_up(u32 core_id, u32 boot_private_data)
int __weak arch_auxiliary_core_up(u32 core_id, u32 boot_private_data)
{
/* please define platform specific arch_auxiliary_core_up() */
return CMD_RET_FAILURE;
}
int arch_auxiliary_core_up(u32 core_id, u32 boot_private_data)
__attribute__((weak, alias("__arch_auxiliary_core_up")));
/* Allow for arch specific config before we boot */
static int __arch_auxiliary_core_check_up(u32 core_id)
int __weak arch_auxiliary_core_check_up(u32 core_id)
{
/* please define platform specific arch_auxiliary_core_check_up() */
return 0;
}
int arch_auxiliary_core_check_up(u32 core_id)
__attribute__((weak, alias("__arch_auxiliary_core_check_up")));
/*
* To i.MX6SX and i.MX7D, the image supported by bootaux needs
* the reset vector at the head for the image, with SP and PC
@ -40,7 +35,7 @@ int arch_auxiliary_core_check_up(u32 core_id)
* The TCMUL is mapped to (M4_BOOTROM_BASE_ADDR) at A core side for
* accessing the M4 TCMUL.
*/
int do_bootaux(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
static int do_bootaux(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
ulong addr;
int ret, up;

4
arch/arm/mach-imx/mx5/clock.c
View file

@ -911,10 +911,11 @@ void mxc_set_sata_internal_clock(void)
}
#endif
#ifndef CONFIG_SPL_BUILD
/*
* Dump some core clockes.
*/
int do_mx5_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
static int do_mx5_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
u32 freq;
@ -947,3 +948,4 @@ U_BOOT_CMD(
"display clocks",
""
);
#endif

6
arch/arm/mach-imx/mx6/Kconfig
View file

@ -130,6 +130,7 @@ config TARGET_CM_FX6
bool "CM-FX6"
select SUPPORT_SPL
select MX6QDL
select BOARD_LATE_INIT
select DM
select DM_SERIAL
select DM_GPIO
@ -377,6 +378,10 @@ config TARGET_PFLA02
config TARGET_SECOMX6
bool "secomx6 boards"
config TARGET_SKSIMX6
bool "sks-imx6"
select SUPPORT_SPL
config TARGET_TBS2910
bool "TBS2910 Matrix ARM mini PC"
@ -482,6 +487,7 @@ source "board/liebherr/display5/Kconfig"
source "board/liebherr/mccmon6/Kconfig"
source "board/logicpd/imx6/Kconfig"
source "board/seco/Kconfig"
source "board/sks-kinkel/sksimx6/Kconfig"
source "board/solidrun/mx6cuboxi/Kconfig"
source "board/technexion/pico-imx6ul/Kconfig"
source "board/tbs/tbs2910/Kconfig"

4
arch/arm/mach-imx/mx6/ddr.c
View file

@ -908,7 +908,7 @@ void mx6sdl_dram_iocfg(unsigned width,
#define MR(val, ba, cmd, cs1) \
((val << 16) | (1 << 15) | (cmd << 4) | (cs1 << 3) | ba)
#define MMDC1(entry, value) do { \
if (!is_mx6sx() && !is_mx6ul() && !is_mx6sl()) \
if (!is_mx6sx() && !is_mx6ul() && !is_mx6ull() && !is_mx6sl()) \
mmdc1->entry = value; \
} while (0)
@ -1215,7 +1215,7 @@ void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo,
u16 mem_speed = ddr3_cfg->mem_speed;
mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
if (!is_mx6sx() && !is_mx6ul() && !is_mx6sl())
if (!is_mx6sx() && !is_mx6ul() && !is_mx6ull() && !is_mx6sl())
mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
/* Limit mem_speed for MX6D/MX6Q */

2
arch/arm/mach-imx/mx7/clock.c
View file

@ -1096,6 +1096,7 @@ void epdc_clock_disable(void)
}
#endif
#ifndef CONFIG_SPL_BUILD
/*
* Dump some core clockes.
*/
@ -1131,3 +1132,4 @@ U_BOOT_CMD(
"display clocks",
""
);
#endif

2
arch/arm/mach-imx/mx7ulp/clock.c
View file

@ -323,6 +323,7 @@ void hab_caam_clock_enable(unsigned char enable)
}
#endif
#ifndef CONFIG_SPL_BUILD
/*
* Dump some core clockes.
*/
@ -363,3 +364,4 @@ U_BOOT_CMD(
"display clocks",
""
);
#endif

45
arch/arm/mach-imx/spl.c
View file

@ -106,10 +106,13 @@ u32 spl_boot_device(void)
switch (boot_device_spl) {
case SD1_BOOT:
case MMC1_BOOT:
return BOOT_DEVICE_MMC1;
case SD2_BOOT:
case MMC2_BOOT:
return BOOT_DEVICE_MMC2;
case SD3_BOOT:
case MMC3_BOOT:
return BOOT_DEVICE_MMC1;
case NAND_BOOT:
return BOOT_DEVICE_NAND;
case SPI_NOR_BOOT:
return BOOT_DEVICE_SPI;
default:
@ -152,9 +155,41 @@ u32 spl_boot_mode(const u32 boot_device)
#if defined(CONFIG_SECURE_BOOT)
/*
* +------------+ 0x0 (DDR_UIMAGE_START) -
* | Header | |
* +------------+ 0x40 |
* | | |
* | | |
* | | |
* | | |
* | Image Data | |
* . | |
* . | > Stuff to be authenticated ----+
* . | | |
* | | | |
* | | | |
* +------------+ | |
* | | | |
* | Fill Data | | |
* | | | |
* +------------+ Align to ALIGN_SIZE | |
* | IVT | | |
* +------------+ + IVT_SIZE - |
* | | |
* | CSF DATA | <---------------------------------------------------------+
* | |
* +------------+
* | |
* | Fill Data |
* | |
* +------------+ + CSF_PAD_SIZE
*/
__weak void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
{
typedef void __noreturn (*image_entry_noargs_t)(void);
uint32_t offset;
image_entry_noargs_t image_entry =
(image_entry_noargs_t)(unsigned long)spl_image->entry_point;
@ -163,8 +198,10 @@ __weak void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
/* HAB looks for the CSF at the end of the authenticated data therefore,
* we need to subtract the size of the CSF from the actual filesize */
if (authenticate_image(spl_image->load_addr,
spl_image->size - CONFIG_CSF_SIZE)) {
offset = spl_image->size - CONFIG_CSF_SIZE;
if (!imx_hab_authenticate_image(spl_image->load_addr,
offset + IVT_SIZE + CSF_PAD_SIZE,
offset)) {
image_entry();
} else {
puts("spl: ERROR: image authentication unsuccessful\n");

21
board/compulab/cm_fx6/cm_fx6.c
View file

@ -621,6 +621,27 @@ int board_init(void)
return 0;
}
int board_late_init(void)
{
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
char baseboard_name[16];
int err;
if (is_mx6dq())
env_set("board_rev", "MX6Q");
else if (is_mx6dl())
env_set("board_rev", "MX6DL");
err = cl_eeprom_get_product_name((uchar *)baseboard_name, 0);
if (err)
return 0;
if (!strncmp("SB-FX6m", baseboard_name, 7))
env_set("board_name", "Utilite");
#endif
return 0;
}
int checkboard(void)
{
puts("Board: CM-FX6\n");

1
board/freescale/common/Makefile
View file

@ -61,6 +61,7 @@ obj-$(CONFIG_VSC_CROSSBAR) += vsc3316_3308.o
obj-$(CONFIG_IDT8T49N222A) += idt8t49n222a_serdes_clk.o
obj-$(CONFIG_ZM7300) += zm7300.o
obj-$(CONFIG_POWER_PFUZE100) += pfuze.o
obj-$(CONFIG_DM_PMIC_PFUZE100) += pfuze.o
obj-$(CONFIG_POWER_MC34VR500) += mc34vr500.o
obj-$(CONFIG_LS102XA_STREAM_ID) += ls102xa_stream_id.o

79
board/freescale/common/pfuze.c
View file

@ -92,4 +92,83 @@ struct pmic *pfuze_common_init(unsigned char i2cbus)
return p;
}
#else
int pfuze_mode_init(struct udevice *dev, u32 mode)
{
unsigned char offset, i, switch_num;
u32 id;
int ret;
id = pmic_reg_read(dev, PFUZE100_DEVICEID);
id = id & 0xf;
if (id == 0) {
switch_num = 6;
offset = PFUZE100_SW1CMODE;
} else if (id == 1) {
switch_num = 4;
offset = PFUZE100_SW2MODE;
} else {
printf("Not supported, id=%d\n", id);
return -EINVAL;
}
ret = pmic_reg_write(dev, PFUZE100_SW1ABMODE, mode);
if (ret < 0) {
printf("Set SW1AB mode error!\n");
return ret;
}
for (i = 0; i < switch_num - 1; i++) {
ret = pmic_reg_write(dev, offset + i * SWITCH_SIZE, mode);
if (ret < 0) {
printf("Set switch 0x%x mode error!\n",
offset + i * SWITCH_SIZE);
return ret;
}
}
return ret;
}
struct udevice *pfuze_common_init(void)
{
struct udevice *dev;
int ret;
unsigned int reg, dev_id, rev_id;
ret = pmic_get("pfuze100", &dev);
if (ret == -ENODEV)
return NULL;
dev_id = pmic_reg_read(dev, PFUZE100_DEVICEID);
rev_id = pmic_reg_read(dev, PFUZE100_REVID);
printf("PMIC: PFUZE100! DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
/* Set SW1AB stanby volage to 0.975V */
reg = pmic_reg_read(dev, PFUZE100_SW1ABSTBY);
reg &= ~SW1x_STBY_MASK;
reg |= SW1x_0_975V;
pmic_reg_write(dev, PFUZE100_SW1ABSTBY, reg);
/* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
reg = pmic_reg_read(dev, PFUZE100_SW1ABCONF);
reg &= ~SW1xCONF_DVSSPEED_MASK;
reg |= SW1xCONF_DVSSPEED_4US;
pmic_reg_write(dev, PFUZE100_SW1ABCONF, reg);
/* Set SW1C standby voltage to 0.975V */
reg = pmic_reg_read(dev, PFUZE100_SW1CSTBY);
reg &= ~SW1x_STBY_MASK;
reg |= SW1x_0_975V;
pmic_reg_write(dev, PFUZE100_SW1CSTBY, reg);
/* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */
reg = pmic_reg_read(dev, PFUZE100_SW1CCONF);
reg &= ~SW1xCONF_DVSSPEED_MASK;
reg |= SW1xCONF_DVSSPEED_4US;
pmic_reg_write(dev, PFUZE100_SW1CCONF, reg);
return dev;
}
#endif

5
board/freescale/common/pfuze.h
View file

@ -7,7 +7,12 @@
#ifndef __PFUZE_BOARD_HELPER__
#define __PFUZE_BOARD_HELPER__
#ifdef CONFIG_DM_PMIC_PFUZE100
struct udevice *pfuze_common_init(void);
int pfuze_mode_init(struct udevice *dev, u32 mode);
#else
struct pmic *pfuze_common_init(unsigned char i2cbus);
int pfuze_mode_init(struct pmic *p, u32 mode);
#endif
#endif

12
board/freescale/mx6memcal/Kconfig
View file

@ -45,20 +45,12 @@ choice
NXP SABRELite.
config UART1_CSI0_DAT10_11
bool "UART1 on CSI0_DAT10/11 (Wand)"
bool "UART1 on CSI0_DAT10/11 (Wand, SabreSD)"
depends on SERIAL_CONSOLE_UART1
help
Choose this configuration if you're using pads
CSI0_DAT10 and DAT11 for a console on UART1 as
is done on the i.MX6 Wand board.
config UART1_SD3_DAT6_7
bool "UART1 on SD3_DAT6/7 (SabreSD, SabreAuto)"
depends on SERIAL_CONSOLE_UART1
help
Choose this configuration if you're using pads
SD3_DAT6 and DAT7 for a console on UART1 as is
done on the NXP SABRESD or SABREAUTO designs.
is done on the i.MX6 Wand board and i.MX6 SabreSD.
config UART1_UART1
bool "UART1 on UART1 (i.MX6SL EVK, WaRP)"

3
board/freescale/mx6memcal/spl.c
View file

@ -419,6 +419,7 @@ void board_init_f(ulong dummy)
if (sysinfo.dsize != 1) {
if (is_cpu_type(MXC_CPU_MX6SX) ||
is_cpu_type(MXC_CPU_MX6UL) ||
is_cpu_type(MXC_CPU_MX6ULL) ||
is_cpu_type(MXC_CPU_MX6SL)) {
printf("cpu type 0x%x doesn't support 64-bit bus\n",
get_cpu_type());
@ -445,7 +446,7 @@ void board_init_f(ulong dummy)
} else {
errs = mmdc_do_dqs_calibration(&sysinfo);
if (errs) {
printf("error %d from write level calibration\n", errs);
printf("error %d from dqs calibration\n", errs);
} else {
printf("completed successfully\n");
mmdc_read_calibration(&sysinfo, &calibration);

382
board/freescale/mx6sxsabresd/mx6sxsabresd.c
View file

@ -26,8 +26,6 @@
#include <power/pmic.h>
#include <power/pfuze100_pmic.h>
#include "../common/pfuze.h"
#include <usb.h>
#include <usb/ehci-ci.h>
DECLARE_GLOBAL_DATA_PTR;
@ -39,11 +37,6 @@ DECLARE_GLOBAL_DATA_PTR;
PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
PAD_CTL_ODE)
#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
PAD_CTL_SPEED_HIGH | \
PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
@ -54,14 +47,12 @@ DECLARE_GLOBAL_DATA_PTR;
#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST)
#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
PAD_CTL_ODE)
#define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)
#define WDOG_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_PKE | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm)
int dram_init(void)
{
gd->ram_size = imx_ddr_size();
@ -74,44 +65,9 @@ static iomux_v3_cfg_t const uart1_pads[] = {
MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
};
static iomux_v3_cfg_t const usdhc2_pads[] = {
MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
static iomux_v3_cfg_t const wdog_b_pad = {
MX6_PAD_GPIO1_IO13__GPIO1_IO_13 | MUX_PAD_CTRL(WDOG_PAD_CTRL),
};
static iomux_v3_cfg_t const usdhc3_pads[] = {
MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DATA0__USDHC3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DATA1__USDHC3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DATA2__USDHC3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DATA3__USDHC3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DATA4__USDHC3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DATA5__USDHC3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DATA6__USDHC3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DATA7__USDHC3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
/* CD pin */
MX6_PAD_KEY_COL0__GPIO2_IO_10 | MUX_PAD_CTRL(NO_PAD_CTRL),
/* RST_B, used for power reset cycle */
MX6_PAD_KEY_COL1__GPIO2_IO_11 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
static iomux_v3_cfg_t const usdhc4_pads[] = {
MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DATA0__USDHC4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DATA1__USDHC4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DATA2__USDHC4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DATA3__USDHC4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DATA7__GPIO6_IO_21 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
static iomux_v3_cfg_t const fec1_pads[] = {
MX6_PAD_ENET1_MDC__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET1_MDIO__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
@ -166,9 +122,11 @@ static int setup_fec(void)
ARRAY_SIZE(phy_control_pads));
/* Enable the ENET power, active low */
gpio_request(IMX_GPIO_NR(2, 6), "enet_rst");
gpio_direction_output(IMX_GPIO_NR(2, 6) , 0);
/* Reset AR8031 PHY */
gpio_request(IMX_GPIO_NR(2, 7), "phy_rst");
gpio_direction_output(IMX_GPIO_NR(2, 7) , 0);
mdelay(10);
gpio_set_value(IMX_GPIO_NR(2, 7), 1);
@ -188,87 +146,29 @@ int board_eth_init(bd_t *bis)
return cpu_eth_init(bis);
}
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
/* I2C1 for PMIC */
static struct i2c_pads_info i2c_pad_info1 = {
.scl = {
.i2c_mode = MX6_PAD_GPIO1_IO00__I2C1_SCL | PC,
.gpio_mode = MX6_PAD_GPIO1_IO00__GPIO1_IO_0 | PC,
.gp = IMX_GPIO_NR(1, 0),
},
.sda = {
.i2c_mode = MX6_PAD_GPIO1_IO01__I2C1_SDA | PC,
.gpio_mode = MX6_PAD_GPIO1_IO01__GPIO1_IO_1 | PC,
.gp = IMX_GPIO_NR(1, 1),
},
};
int power_init_board(void)
{
struct pmic *p;
struct udevice *dev;
unsigned int reg;
int ret;
p = pfuze_common_init(I2C_PMIC);
if (!p)
dev = pfuze_common_init();
if (!dev)
return -ENODEV;
ret = pfuze_mode_init(p, APS_PFM);
ret = pfuze_mode_init(dev, APS_PFM);
if (ret < 0)
return ret;
/* Enable power of VGEN5 3V3, needed for SD3 */
pmic_reg_read(p, PFUZE100_VGEN5VOL, &reg);
reg = pmic_reg_read(dev, PFUZE100_VGEN5VOL);
reg &= ~LDO_VOL_MASK;
reg |= (LDOB_3_30V | (1 << LDO_EN));
pmic_reg_write(p, PFUZE100_VGEN5VOL, reg);
pmic_reg_write(dev, PFUZE100_VGEN5VOL, reg);
return 0;
}
#ifdef CONFIG_USB_EHCI_MX6
#define USB_OTHERREGS_OFFSET 0x800
#define UCTRL_PWR_POL (1 << 9)
static iomux_v3_cfg_t const usb_otg_pads[] = {
/* OGT1 */
MX6_PAD_GPIO1_IO09__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_GPIO1_IO10__ANATOP_OTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
/* OTG2 */
MX6_PAD_GPIO1_IO12__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)
};
static void setup_usb(void)
{
imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
ARRAY_SIZE(usb_otg_pads));
}
int board_usb_phy_mode(int port)
{
if (port == 1)
return USB_INIT_HOST;
else
return usb_phy_mode(port);
}
int board_ehci_hcd_init(int port)
{
u32 *usbnc_usb_ctrl;
if (port > 1)
return -EINVAL;
usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
port * 4);
/* Set Power polarity */
setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
return 0;
}
#endif
int board_phy_config(struct phy_device *phydev)
{
/*
@ -296,138 +196,12 @@ int board_early_init_f(void)
imx_iomux_v3_setup_multiple_pads(peri_3v3_pads,
ARRAY_SIZE(peri_3v3_pads));
/* Active high for ncp692 */
gpio_direction_output(IMX_GPIO_NR(4, 16) , 1);
#ifdef CONFIG_USB_EHCI_MX6
setup_usb();
#endif
return 0;
}
static struct fsl_esdhc_cfg usdhc_cfg[3] = {
{USDHC2_BASE_ADDR, 0, 4},
{USDHC3_BASE_ADDR},
{USDHC4_BASE_ADDR},
};
#define USDHC3_CD_GPIO IMX_GPIO_NR(2, 10)
#define USDHC3_PWR_GPIO IMX_GPIO_NR(2, 11)
#define USDHC4_CD_GPIO IMX_GPIO_NR(6, 21)
int board_mmc_get_env_dev(int devno)
{
return devno - 1;
}
int board_mmc_getcd(struct mmc *mmc)
{
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
int ret = 0;
switch (cfg->esdhc_base) {
case USDHC2_BASE_ADDR:
ret = 1; /* Assume uSDHC2 is always present */
break;
case USDHC3_BASE_ADDR:
ret = !gpio_get_value(USDHC3_CD_GPIO);
break;
case USDHC4_BASE_ADDR:
ret = !gpio_get_value(USDHC4_CD_GPIO);
break;
}
return ret;
}
int board_mmc_init(bd_t *bis)
{
#ifndef CONFIG_SPL_BUILD
int i, ret;
/*
* According to the board_mmc_init() the following map is done:
* (U-Boot device node) (Physical Port)
* mmc0 USDHC2
* mmc1 USDHC3
* mmc2 USDHC4
*/
for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
switch (i) {
case 0:
imx_iomux_v3_setup_multiple_pads(
usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
break;
case 1:
imx_iomux_v3_setup_multiple_pads(
usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
gpio_direction_input(USDHC3_CD_GPIO);
gpio_direction_output(USDHC3_PWR_GPIO, 1);
usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
break;
case 2:
imx_iomux_v3_setup_multiple_pads(
usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
gpio_direction_input(USDHC4_CD_GPIO);
usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
break;
default:
printf("Warning: you configured more USDHC controllers"
"(%d) than supported by the board\n", i + 1);
return -EINVAL;
}
ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
if (ret) {
printf("Warning: failed to initialize mmc dev %d\n", i);
return ret;
}
}
return 0;
#else
struct src *src_regs = (struct src *)SRC_BASE_ADDR;
u32 val;
u32 port;
val = readl(&src_regs->sbmr1);
if ((val & 0xc0) != 0x40) {
printf("Not boot from USDHC!\n");
return -EINVAL;
}
port = (val >> 11) & 0x3;
printf("port %d\n", port);
switch (port) {
case 1:
imx_iomux_v3_setup_multiple_pads(
usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
break;
case 2:
imx_iomux_v3_setup_multiple_pads(
usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
gpio_direction_input(USDHC3_CD_GPIO);
gpio_direction_output(USDHC3_PWR_GPIO, 1);
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
break;
case 3:
imx_iomux_v3_setup_multiple_pads(
usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
gpio_direction_input(USDHC4_CD_GPIO);
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR;
break;
}
gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
#endif
return devno;
}
#ifdef CONFIG_FSL_QSPI
@ -509,11 +283,13 @@ static int setup_lcd(void)
imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
/* Reset the LCD */
gpio_request(IMX_GPIO_NR(3, 27), "lcd_rst");
gpio_direction_output(IMX_GPIO_NR(3, 27) , 0);
udelay(500);
gpio_direction_output(IMX_GPIO_NR(3, 27) , 1);
/* Set Brightness to high */
gpio_request(IMX_GPIO_NR(6, 4), "lcd_bright");
gpio_direction_output(IMX_GPIO_NR(6, 4) , 1);
return 0;
@ -525,9 +301,18 @@ int board_init(void)
/* Address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
#ifdef CONFIG_SYS_I2C_MXC
setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
#endif
/*
* Because kernel set WDOG_B mux before pad with the common pinctrl
* framwork now and wdog reset will be triggered once set WDOG_B mux
* with default pad setting, we set pad setting here to workaround this.
* Since imx_iomux_v3_setup_pad also set mux before pad setting, we set
* as GPIO mux firstly here to workaround it.
*/
imx_iomux_v3_setup_pad(wdog_b_pad);
/* Active high for ncp692 */
gpio_request(IMX_GPIO_NR(4, 16), "ncp692_en");
gpio_direction_output(IMX_GPIO_NR(4, 16), 1);
#ifdef CONFIG_FSL_QSPI
board_qspi_init();
@ -566,6 +351,117 @@ int checkboard(void)
#include <spl.h>
#include <asm/arch/mx6-ddr.h>
static struct fsl_esdhc_cfg usdhc_cfg[3] = {
{USDHC2_BASE_ADDR, 0, 4},
{USDHC3_BASE_ADDR},
{USDHC4_BASE_ADDR},
};
#define USDHC3_CD_GPIO IMX_GPIO_NR(2, 10)
#define USDHC3_PWR_GPIO IMX_GPIO_NR(2, 11)
#define USDHC4_CD_GPIO IMX_GPIO_NR(6, 21)
static iomux_v3_cfg_t const usdhc2_pads[] = {
MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
};
static iomux_v3_cfg_t const usdhc3_pads[] = {
MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DATA0__USDHC3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DATA1__USDHC3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DATA2__USDHC3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DATA3__USDHC3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DATA4__USDHC3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DATA5__USDHC3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DATA6__USDHC3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DATA7__USDHC3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
/* CD pin */
MX6_PAD_KEY_COL0__GPIO2_IO_10 | MUX_PAD_CTRL(NO_PAD_CTRL),
/* RST_B, used for power reset cycle */
MX6_PAD_KEY_COL1__GPIO2_IO_11 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
static iomux_v3_cfg_t const usdhc4_pads[] = {
MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DATA0__USDHC4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DATA1__USDHC4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DATA2__USDHC4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DATA3__USDHC4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DATA7__GPIO6_IO_21 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
int board_mmc_init(bd_t *bis)
{
struct src *src_regs = (struct src *)SRC_BASE_ADDR;
u32 val;
u32 port;
val = readl(&src_regs->sbmr1);
if ((val & 0xc0) != 0x40) {
printf("Not boot from USDHC!\n");
return -EINVAL;
}
port = (val >> 11) & 0x3;
printf("port %d\n", port);
switch (port) {
case 1:
imx_iomux_v3_setup_multiple_pads(
usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
break;
case 2:
imx_iomux_v3_setup_multiple_pads(
usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
gpio_direction_input(USDHC3_CD_GPIO);
gpio_direction_output(USDHC3_PWR_GPIO, 1);
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
break;
case 3:
imx_iomux_v3_setup_multiple_pads(
usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
gpio_direction_input(USDHC4_CD_GPIO);
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR;
break;
}
gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
}
int board_mmc_getcd(struct mmc *mmc)
{
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
int ret = 0;
switch (cfg->esdhc_base) {
case USDHC2_BASE_ADDR:
ret = 1; /* Assume uSDHC2 is always present */
break;
case USDHC3_BASE_ADDR:
ret = !gpio_get_value(USDHC3_CD_GPIO);
break;
case USDHC4_BASE_ADDR:
ret = !gpio_get_value(USDHC4_CD_GPIO);
break;
}
return ret;
}
const struct mx6sx_iomux_ddr_regs mx6_ddr_ioregs = {
.dram_dqm0 = 0x00000028,
.dram_dqm1 = 0x00000028,

4
board/gateworks/gw_ventana/eeprom.c
View file

@ -119,7 +119,7 @@ struct ventana_eeprom_config econfig[] = {
{ /* Sentinel */ }
};
#ifdef CONFIG_CMD_EECONFIG
#if defined(CONFIG_CMD_EECONFIG) && !defined(CONFIG_SPL_BUILD)
static struct ventana_eeprom_config *get_config(const char *name)
{
struct ventana_eeprom_config *cfg = econfig;
@ -135,7 +135,7 @@ static struct ventana_eeprom_config *get_config(const char *name)
static u8 econfig_bytes[sizeof(ventana_info.config)];
static int econfig_init = -1;
int do_econfig(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
static int do_econfig(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
struct ventana_eeprom_config *cfg;
struct ventana_board_info *info = &ventana_info;

2
board/gateworks/gw_ventana/gsc.c
View file

@ -172,7 +172,7 @@ int gsc_boot_wd_disable(void)
return 1;
}
#ifdef CONFIG_CMD_GSC
#if defined(CONFIG_CMD_GSC) && !defined(CONFIG_SPL_BUILD)
static int do_gsc_sleep(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
{

11
board/sks-kinkel/sksimx6/Kconfig Normal file
View file

@ -0,0 +1,11 @@
if TARGET_SKSIMX6
config SYS_BOARD
default "sksimx6"
config SYS_VENDOR
default "sks-kinkel"
config SYS_CONFIG_NAME
default "sksimx6"
endif

6
board/sks-kinkel/sksimx6/MAINTAINERS Normal file
View file

@ -0,0 +1,6 @@
SKS-Kinkel sksimx6
M: Stefano Babic <sbabic@denx.de>
S: Maintained
F: board/sks-kinkel/sksimx6/
F: include/configs/sksimx6.h
F: configs/sksimx6_defconfig

3
board/sks-kinkel/sksimx6/Makefile Normal file
View file

@ -0,0 +1,3 @@
# SPDX-License-Identifier: GPL-2.0+
#
obj-y := sksimx6.o

426
board/sks-kinkel/sksimx6/sksimx6.c Normal file
View file

@ -0,0 +1,426 @@
/*
* Copyright (C) 2016 Stefano Babic <sbabic@denx.de>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-pins.h>
#include <linux/errno.h>
#include <asm/gpio.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/video.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <asm/arch/crm_regs.h>
#include <asm/io.h>
#include <asm/arch/sys_proto.h>
#include <spl.h>
#include <netdev.h>
#include <miiphy.h>
#include <micrel.h>
#include <common.h>
#include <malloc.h>
#include <fuse.h>
DECLARE_GLOBAL_DATA_PTR;
#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
PAD_CTL_SRE_FAST | PAD_CTL_HYS)
#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
PAD_CTL_ODE | PAD_CTL_SRE_FAST)
#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
static iomux_v3_cfg_t const uart1_pads[] = {
IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
};
static iomux_v3_cfg_t const gpios_pads[] = {
IOMUX_PADS(PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
};
static iomux_v3_cfg_t const usdhc2_pads[] = {
IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL)),/* CD */
};
static iomux_v3_cfg_t const enet_pads[] = {
IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK |
MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL)),
};
iomux_v3_cfg_t const enet_pads1[] = {
/* pin 35 - 1 (PHY_AD2) on reset */
IOMUX_PADS(PAD_RGMII_RXC__GPIO6_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL)),
/* pin 32 - 1 - (MODE0) all */
IOMUX_PADS(PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL)),
/* pin 31 - 1 - (MODE1) all */
IOMUX_PADS(PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL)),
/* pin 28 - 1 - (MODE2) all */
IOMUX_PADS(PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL)),
/* pin 27 - 1 - (MODE3) all */
IOMUX_PADS(PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)),
/* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
IOMUX_PADS(PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL)),
/* pin 42 PHY nRST */
IOMUX_PADS(PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL)),
};
static int mx6_rgmii_rework(struct phy_device *phydev)
{
/* min rx data delay */
ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW,
0x0);
/* min tx data delay */
ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW,
0x0);
/* max rx/tx clock delay, min rx/tx control */
ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_CLOCK_SKEW,
0xf0f0);
return 0;
}
int board_phy_config(struct phy_device *phydev)
{
mx6_rgmii_rework(phydev);
if (phydev->drv->config)
return phydev->drv->config(phydev);
return 0;
}
#define ENET_NRST IMX_GPIO_NR(1, 25)
void setup_iomux_enet(void)
{
SETUP_IOMUX_PADS(enet_pads);
}
int board_eth_init(bd_t *bis)
{
uint32_t base = IMX_FEC_BASE;
struct mii_dev *bus = NULL;
struct phy_device *phydev = NULL;
int ret;
setup_iomux_enet();
bus = fec_get_miibus(base, -1);
if (!bus)
return -EINVAL;
/* scan phy */
phydev = phy_find_by_mask(bus, (0xf << CONFIG_FEC_MXC_PHYADDR),
PHY_INTERFACE_MODE_RGMII);
if (!phydev) {
ret = -EINVAL;
goto free_bus;
}
ret = fec_probe(bis, -1, base, bus, phydev);
if (ret)
goto free_phydev;
return 0;
free_phydev:
free(phydev);
free_bus:
free(bus);
return ret;
}
int board_early_init_f(void)
{
SETUP_IOMUX_PADS(uart1_pads);
return 0;
}
int board_init(void)
{
/* Address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
/* Take in reset the ATMega processor */
SETUP_IOMUX_PADS(gpios_pads);
gpio_direction_output(IMX_GPIO_NR(5, 4), 0);
return 0;
}
int dram_init(void)
{
gd->ram_size = imx_ddr_size();
return 0;
}
struct fsl_esdhc_cfg usdhc_cfg[1] = {
{USDHC2_BASE_ADDR, 0},
};
#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 0)
int board_mmc_getcd(struct mmc *mmc)
{
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
int ret = 0;
if (cfg->esdhc_base == USDHC2_BASE_ADDR)
ret = 1;
return ret;
}
int board_mmc_init(bd_t *bis)
{
int ret;
SETUP_IOMUX_PADS(usdhc2_pads);
gpio_direction_input(USDHC2_CD_GPIO);
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
usdhc_cfg[0].max_bus_width = 4;
ret = fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
if (ret) {
printf("Warning: failed to initialize mmc dev \n");
return ret;
}
return 0;
}
#if defined(CONFIG_SPL_BUILD)
#include <asm/arch/mx6-ddr.h>
/*
* Driving strength:
* 0x30 == 40 Ohm
* 0x28 == 48 Ohm
*/
#define IMX6SDL_DRIVE_STRENGTH 0x230
/* configure MX6SOLO/DUALLITE mmdc DDR io registers */
struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
.dram_sdclk_0 = IMX6SDL_DRIVE_STRENGTH,
.dram_sdclk_1 = IMX6SDL_DRIVE_STRENGTH,
.dram_cas = IMX6SDL_DRIVE_STRENGTH,
.dram_ras = IMX6SDL_DRIVE_STRENGTH,
.dram_reset = IMX6SDL_DRIVE_STRENGTH,
.dram_sdcke0 = IMX6SDL_DRIVE_STRENGTH,
.dram_sdcke1 = IMX6SDL_DRIVE_STRENGTH,
.dram_sdba2 = 0x00000000,
.dram_sdodt0 = IMX6SDL_DRIVE_STRENGTH,
.dram_sdodt1 = IMX6SDL_DRIVE_STRENGTH,
.dram_sdqs0 = IMX6SDL_DRIVE_STRENGTH,
.dram_sdqs1 = IMX6SDL_DRIVE_STRENGTH,
.dram_sdqs2 = IMX6SDL_DRIVE_STRENGTH,
.dram_sdqs3 = IMX6SDL_DRIVE_STRENGTH,
.dram_sdqs4 = IMX6SDL_DRIVE_STRENGTH,
.dram_sdqs5 = IMX6SDL_DRIVE_STRENGTH,
.dram_sdqs6 = IMX6SDL_DRIVE_STRENGTH,
.dram_sdqs7 = IMX6SDL_DRIVE_STRENGTH,
.dram_dqm0 = IMX6SDL_DRIVE_STRENGTH,
.dram_dqm1 = IMX6SDL_DRIVE_STRENGTH,
.dram_dqm2 = IMX6SDL_DRIVE_STRENGTH,
.dram_dqm3 = IMX6SDL_DRIVE_STRENGTH,
.dram_dqm4 = IMX6SDL_DRIVE_STRENGTH,
.dram_dqm5 = IMX6SDL_DRIVE_STRENGTH,
.dram_dqm6 = IMX6SDL_DRIVE_STRENGTH,
.dram_dqm7 = IMX6SDL_DRIVE_STRENGTH,
};
/* configure MX6SOLO/DUALLITE mmdc GRP io registers */
struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
.grp_ddr_type = 0x000c0000,
.grp_ddrmode_ctl = 0x00020000,
.grp_ddrpke = 0x00000000,
.grp_addds = IMX6SDL_DRIVE_STRENGTH,
.grp_ctlds = IMX6SDL_DRIVE_STRENGTH,
.grp_ddrmode = 0x00020000,
.grp_b0ds = IMX6SDL_DRIVE_STRENGTH,
.grp_b1ds = IMX6SDL_DRIVE_STRENGTH,
.grp_b2ds = IMX6SDL_DRIVE_STRENGTH,
.grp_b3ds = IMX6SDL_DRIVE_STRENGTH,
.grp_b4ds = IMX6SDL_DRIVE_STRENGTH,
.grp_b5ds = IMX6SDL_DRIVE_STRENGTH,
.grp_b6ds = IMX6SDL_DRIVE_STRENGTH,
.grp_b7ds = IMX6SDL_DRIVE_STRENGTH,
};
/* MT41K128M16JT-125 */
static struct mx6_ddr3_cfg mt41k128m16jt_125 = {
/* quad = 1066, duallite = 800 */
.mem_speed = 1066,
.density = 2,
.width = 16,
.banks = 8,
.rowaddr = 14,
.coladdr = 10,
.pagesz = 2,
.trcd = 1375,
.trcmin = 4875,
.trasmin = 3500,
.SRT = 0,
};
static struct mx6_mmdc_calibration mx6dl_1g_mmdc_calib = {
.p0_mpwldectrl0 = 0x0043004E,
.p0_mpwldectrl1 = 0x003D003F,
.p1_mpwldectrl0 = 0x00230021,
.p1_mpwldectrl1 = 0x0028003E,
.p0_mpdgctrl0 = 0x42580250,
.p0_mpdgctrl1 = 0x0238023C,
.p1_mpdgctrl0 = 0x422C0238,
.p1_mpdgctrl1 = 0x02180228,
.p0_mprddlctl = 0x44464A46,
.p1_mprddlctl = 0x44464A42,
.p0_mpwrdlctl = 0x36343236,
.p1_mpwrdlctl = 0x36343230,
};
/* DDR 64bit 1GB */
static struct mx6_ddr_sysinfo mem_qdl = {
.dsize = 2,
.cs1_mirror = 0,
/* config for full 4GB range so that get_mem_size() works */
.cs_density = 32,
.ncs = 1,
.bi_on = 1,
.rtt_nom = 1,
.rtt_wr = 1,
.ralat = 5,
.walat = 0,
.mif3_mode = 3,
.rst_to_cke = 0x23,
.sde_to_rst = 0x10,
.refsel = 1, /* Refresh cycles at 32KHz */
.refr = 7, /* 8 refresh commands per refresh cycle */
};
static void ccgr_init(void)
{
struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
/* set the default clock gate to save power */
writel(0x00C03F3F, &ccm->CCGR0);
writel(0x0030FC03, &ccm->CCGR1);
writel(0x0FFFC000, &ccm->CCGR2);
writel(0x3FF00000, &ccm->CCGR3);
writel(0x00FFF300, &ccm->CCGR4);
writel(0xFFFFFFFF, &ccm->CCGR5);
writel(0x000003FF, &ccm->CCGR6);
}
static void spl_dram_init(void)
{
if (is_cpu_type(MXC_CPU_MX6DL)) {
mt41k128m16jt_125.mem_speed = 800;
mem_qdl.rtt_nom = 1;
mem_qdl.rtt_wr = 1;
mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
mx6_dram_cfg(&mem_qdl, &mx6dl_1g_mmdc_calib, &mt41k128m16jt_125);
} else {
printf("Wrong CPU for this board\n");
return;
}
udelay(100);
#ifdef CONFIG_MX6_DDRCAL
/* Perform DDR DRAM calibration */
mmdc_do_write_level_calibration(&mem_qdl);
mmdc_do_dqs_calibration(&mem_qdl);
#endif
}
static void check_bootcfg(void)
{
u32 val5, val6;
fuse_sense(0, 5, &val5);
fuse_sense(0, 6, &val6);
/* Check if boot from MMC */
if (val6 & 0x10) {
puts("BT_FUSE_SEL already fused, will do nothing\n");
return;
}
fuse_prog(0, 5, 0x00000840);
/* BT_FUSE_SEL */
fuse_prog(0, 6, 0x00000010);
do_reset(NULL, 0, 0, NULL);
}
void board_init_f(ulong dummy)
{
ccgr_init();
/* setup AIPS and disable watchdog */
arch_cpu_init();
gpr_init();
/* iomux */
board_early_init_f();
/* setup GP timer */
timer_init();
/* UART clocks enabled and gd valid - init serial console */
preloader_console_init();
/* DDR initialization */
spl_dram_init();
/* Set fuses for new boards and reboot if not set */
check_bootcfg();
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
/* load/boot image from boot device */
board_init_r(NULL, 0);
}
#endif

9
board/toradex/apalis_imx6/pf0100.c
View file

@ -10,6 +10,7 @@
#include <common.h>
#include <i2c.h>
#include <linux/compiler.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-pins.h>
@ -23,7 +24,7 @@
/*#define DEBUG */
/* use Apalis GPIO1 to switch on VPGM, ON: 1 */
static iomux_v3_cfg_t const pmic_prog_pads[] = {
static __maybe_unused iomux_v3_cfg_t const pmic_prog_pads[] = {
MX6_PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
# define PMIC_PROG_VOLTAGE IMX_GPIO_NR(2, 4)
};
@ -161,7 +162,8 @@ unsigned pmic_init(void)
return programmed;
}
int pf0100_prog(void)
#ifndef CONFIG_SPL_BUILD
static int pf0100_prog(void)
{
unsigned char bus = 1;
unsigned char val;
@ -208,7 +210,7 @@ int pf0100_prog(void)
return CMD_RET_SUCCESS;
}
int do_pf0100_prog(cmd_tbl_t *cmdtp, int flag, int argc,
static int do_pf0100_prog(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
{
int ret;
@ -226,3 +228,4 @@ U_BOOT_CMD(
"Program the OTP fuses on the PMIC PF0100",
""
);
#endif

3
board/toradex/apalis_imx6/pf0100.h
View file

@ -50,7 +50,4 @@
/* i.e. 0: unprogrammed, 3: programmed, other: undefined prog. state */
unsigned pmic_init(void);
/* programmes OTP fuses to values required on a Toradex Apalis iMX6 */
int pf0100_prog(void);
#endif /* PF0100_H_ */

8
board/toradex/colibri_imx6/pf0100.c
View file

@ -23,7 +23,7 @@
/*#define DEBUG */
/* use GPIO: EXT_IO1 to switch on VPGM, ON: 1 */
static iomux_v3_cfg_t const pmic_prog_pads[] = {
static __maybe_unused iomux_v3_cfg_t const pmic_prog_pads[] = {
MX6_PAD_NANDF_D3__GPIO2_IO03 | MUX_PAD_CTRL(NO_PAD_CTRL),
# define PMIC_PROG_VOLTAGE IMX_GPIO_NR(2, 3)
};
@ -144,7 +144,8 @@ unsigned pmic_init(void)
return programmed;
}
int pf0100_prog(void)
#ifndef CONFIG_SPL_BUILD
static int pf0100_prog(void)
{
unsigned char bus = 1;
unsigned char val;
@ -191,7 +192,7 @@ int pf0100_prog(void)
return CMD_RET_SUCCESS;
}
int do_pf0100_prog(cmd_tbl_t *cmdtp, int flag, int argc,
static int do_pf0100_prog(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
{
int ret;
@ -209,3 +210,4 @@ U_BOOT_CMD(
"Program the OTP fuses on the PMIC PF0100",
""
);
#endif

3
board/toradex/colibri_imx6/pf0100.h
View file

@ -50,7 +50,4 @@
/* i.e. 0: unprogrammed, 3: programmed, other: undefined prog. state */
unsigned pmic_init(void);
/* programmes OTP fuses to values required on a Toradex Apalis iMX6 */
int pf0100_prog(void);
#endif /* PF0100_H_ */

2
configs/cm_fx6_defconfig
View file

@ -16,7 +16,7 @@ CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
CONFIG_BOOTCOMMAND="run distro_bootcmd; run legacy_bootcmd"
CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd; run legacy_bootcmd"
CONFIG_SPL=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x80
CONFIG_SPL_I2C_SUPPORT=y

15
configs/mx6sxsabresd_defconfig
View file

@ -3,6 +3,7 @@ CONFIG_ARCH_MX6=y
CONFIG_TARGET_MX6SXSABRESD=y
# CONFIG_CMD_BMODE is not set
CONFIG_NXP_BOARD_REVISION=y
CONFIG_DEFAULT_DEVICE_TREE="imx6sx-sdb"
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sxsabresd/imximage.cfg"
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
@ -27,13 +28,25 @@ CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_CONTROL=y
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_PHYLIB=y
CONFIG_PCI=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_DM_PMIC=y
CONFIG_DM_PMIC_PFUZE100=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_PFUZE100=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_VIDEO=y
CONFIG_OF_LIBFDT=y

15
configs/mx6sxsabresd_spl_defconfig
View file

@ -10,6 +10,7 @@ CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
# CONFIG_CMD_BMODE is not set
CONFIG_NXP_BOARD_REVISION=y
CONFIG_DEFAULT_DEVICE_TREE="imx6sx-sdb"
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
@ -36,12 +37,24 @@ CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_CONTROL=y
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
CONFIG_SPI_FLASH=y
CONFIG_PHYLIB=y
CONFIG_PCI=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_DM_PMIC=y
CONFIG_DM_PMIC_PFUZE100=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_PFUZE100=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_VIDEO=y
CONFIG_OF_LIBFDT=y

6
configs/mx6ull_14x14_evk_defconfig
View file

@ -10,6 +10,7 @@ CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
@ -24,7 +25,12 @@ CONFIG_DM_GPIO=y
CONFIG_DM_74X164=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_SPI=y
CONFIG_FSL_QSPI=y

6
configs/mx6ull_14x14_evk_plugin_defconfig
View file

@ -11,6 +11,7 @@ CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
@ -25,7 +26,12 @@ CONFIG_DM_GPIO=y
CONFIG_DM_74X164=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_SPI=y
CONFIG_FSL_QSPI=y

47
configs/sksimx6_defconfig Normal file
View file

@ -0,0 +1,47 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_MX6_DDRCAL=y
CONFIG_TARGET_SKSIMX6=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6QDL"
CONFIG_BOOTDELAY=1
CONFIG_SILENT_CONSOLE=y
CONFIG_SILENT_U_BOOT_ONLY=y
CONFIG_VERSION_VARIABLE=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_MMC=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_DM=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_PHY_MICREL_KSZ8XXX=y
CONFIG_NETDEVICES=y
CONFIG_FEC_MXC=y
CONFIG_DM_THERMAL=y
CONFIG_OF_LIBFDT=y

17
drivers/misc/mxc_ocotp.c
View file

@ -342,6 +342,23 @@ int fuse_sense(u32 bank, u32 word, u32 *val)
static int prepare_write(struct ocotp_regs **regs, u32 bank, u32 word,
const char *caller)
{
#ifdef CONFIG_MX7ULP
u32 val;
int ret;
/* Only bank 0 and 1 are redundancy mode, others are ECC mode */
if (bank != 0 && bank != 1) {
ret = fuse_sense(bank, word, &val);
if (ret)
return ret;
if (val != 0) {
printf("mxc_ocotp: The word has been programmed, no more write\n");
return -EPERM;
}
}
#endif
return prepare_access(regs, bank, word, true, caller);
}

15
drivers/pci/pcie_imx.c
View file

@ -517,10 +517,12 @@ static int imx6_pcie_init_phy(void)
__weak int imx6_pcie_toggle_power(void)
{
#ifdef CONFIG_PCIE_IMX_POWER_GPIO
gpio_request(CONFIG_PCIE_IMX_POWER_GPIO, "pcie_power");
gpio_direction_output(CONFIG_PCIE_IMX_POWER_GPIO, 0);
mdelay(20);
gpio_set_value(CONFIG_PCIE_IMX_POWER_GPIO, 1);
mdelay(20);
gpio_free(CONFIG_PCIE_IMX_POWER_GPIO);
#endif
return 0;
}
@ -556,10 +558,12 @@ __weak int imx6_pcie_toggle_reset(void)
* state due to being previously used in U-Boot.
*/
#ifdef CONFIG_PCIE_IMX_PERST_GPIO
gpio_request(CONFIG_PCIE_IMX_PERST_GPIO, "pcie_reset");
gpio_direction_output(CONFIG_PCIE_IMX_PERST_GPIO, 0);
mdelay(20);
gpio_set_value(CONFIG_PCIE_IMX_PERST_GPIO, 1);
mdelay(20);
gpio_free(CONFIG_PCIE_IMX_PERST_GPIO);
#else
puts("WARNING: Make sure the PCIe #PERST line is connected!\n");
#endif
@ -611,6 +615,17 @@ static int imx_pcie_link_up(void)
imx_pcie_regions_setup();
/*
* By default, the subordinate is set equally to the secondary
* bus (0x01) when the RC boots.
* This means that theoretically, only bus 1 is reachable from the RC.
* Force the PCIe RC subordinate to 0xff, otherwise no downstream
* devices will be detected if the enumeration is applied strictly.
*/
tmp = readl(MX6_DBI_ADDR + 0x18);
tmp |= (0xff << 16);
writel(tmp, MX6_DBI_ADDR + 0x18);
/*
* FIXME: Force the PCIe RC to Gen1 operation
* The RC must be forced into Gen1 mode before bringing the link

18
drivers/spi/fsl_qspi.c
View file

@ -20,7 +20,8 @@
DECLARE_GLOBAL_DATA_PTR;
#define RX_BUFFER_SIZE 0x80
#ifdef CONFIG_MX6SX
#if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || \
defined(CONFIG_MX6ULL) || defined(CONFIG_MX7D)
#define TX_BUFFER_SIZE 0x200
#else
#define TX_BUFFER_SIZE 0x40
@ -268,7 +269,8 @@ static void qspi_set_lut(struct fsl_qspi_priv *priv)
INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) |
PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
#endif
#ifdef CONFIG_MX6SX
#if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || \
defined(CONFIG_MX6ULL) || defined(CONFIG_MX7D)
/*
* To MX6SX, OPRND0(TX_BUFFER_SIZE) can not work correctly.
* So, Use IDATSZ in IPCR to determine the size and here set 0.
@ -905,6 +907,11 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
qspi->slave.max_write_size = TX_BUFFER_SIZE;
mcr_val = qspi_read32(qspi->priv.flags, &regs->mcr);
/* Set endianness to LE for i.mx */
if (IS_ENABLED(CONFIG_MX6) || IS_ENABLED(CONFIG_MX7))
mcr_val = QSPI_MCR_END_CFD_LE;
qspi_write32(qspi->priv.flags, &regs->mcr,
QSPI_MCR_RESERVED_MASK | QSPI_MCR_MDIS_MASK |
(mcr_val & QSPI_MCR_END_CFD_MASK));
@ -1023,6 +1030,11 @@ static int fsl_qspi_probe(struct udevice *bus)
}
mcr_val = qspi_read32(priv->flags, &priv->regs->mcr);
/* Set endianness to LE for i.mx */
if (IS_ENABLED(CONFIG_MX6) || IS_ENABLED(CONFIG_MX7))
mcr_val = QSPI_MCR_END_CFD_LE;
qspi_write32(priv->flags, &priv->regs->mcr,
QSPI_MCR_RESERVED_MASK | QSPI_MCR_MDIS_MASK |
(mcr_val & QSPI_MCR_END_CFD_MASK));
@ -1227,6 +1239,8 @@ static const struct dm_spi_ops fsl_qspi_ops = {
static const struct udevice_id fsl_qspi_ids[] = {
{ .compatible = "fsl,vf610-qspi" },
{ .compatible = "fsl,imx6sx-qspi" },
{ .compatible = "fsl,imx6ul-qspi" },
{ .compatible = "fsl,imx7d-qspi" },
{ }
};

7
include/configs/cm_fx6.h
View file

@ -67,6 +67,7 @@
#define CONFIG_ENV_OFFSET (768 * 1024)
#ifndef CONFIG_SPL_BUILD
#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
#define CONFIG_EXTRA_ENV_SETTINGS \
"fdt_high=0xffffffff\0" \
"initrd_high=0xffffffff\0" \
@ -75,6 +76,7 @@
"kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
"pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
"scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \
"fdtfile=undefined\0" \
"stdin=serial,usbkbd\0" \
"stdout=serial,vga\0" \
"stderr=serial,vga\0" \
@ -152,6 +154,11 @@
"fi;" \
"run setupnandboot;" \
"run nandboot;\0" \
"findfdt="\
"if test $board_name = Utilite && test $board_rev = MX6Q ; then " \
"setenv fdtfile imx6q-utilite-pro.dtb; fi; " \
"if test $fdtfile = undefined; then " \
"echo WARNING: Could not determine dtb to use; fi; \0" \
BOOTENV
#define CONFIG_PREBOOT "usb start;sf probe"

9
include/configs/mx6sxsabresd.h
View file

@ -145,19 +145,12 @@
#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC4_BASE_ADDR
/* I2C Configs */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
#define CONFIG_SYS_I2C_SPEED 100000
/* PMIC */
#define CONFIG_POWER
#define CONFIG_POWER_I2C
#define CONFIG_POWER_PFUZE100
#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
/* Network */
#define CONFIG_FEC_MXC
#define CONFIG_MII
@ -210,7 +203,7 @@
#endif
#endif
#define CONFIG_ENV_OFFSET (8 * SZ_64K)
#define CONFIG_ENV_OFFSET (14 * SZ_64K)
#define CONFIG_ENV_SIZE SZ_8K
#define CONFIG_SYS_FSL_USDHC_NUM 3

10
include/configs/mx6ullevk.h
View file

@ -164,4 +164,14 @@
#define CONFIG_SOFT_SPI
#ifdef CONFIG_FSL_QSPI
#define CONFIG_SYS_FSL_QSPI_AHB
#define CONFIG_SF_DEFAULT_BUS 0
#define CONFIG_SF_DEFAULT_CS 0
#define CONFIG_SF_DEFAULT_SPEED 40000000
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
#define FSL_QSPI_FLASH_NUM 1
#define FSL_QSPI_FLASH_SIZE SZ_32M
#endif
#endif

101
include/configs/sksimx6.h Normal file
View file

@ -0,0 +1,101 @@
/*
* Copyright (C) Stefano Babic <sbabic@denx.de>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __SKSIMX6_CONFIG_H
#define __SKSIMX6_CONFIG_H
#include <config_distro_defaults.h>
#include "mx6_common.h"
#include "imx6_spl.h"
/* Thermal */
#define CONFIG_IMX_THERMAL
/* Serial */
#define CONFIG_MXC_UART
#define CONFIG_MXC_UART_BASE UART1_BASE
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (8 * SZ_1M)
/* Ethernet */
#define IMX_FEC_BASE ENET_BASE_ADDR
#define CONFIG_FEC_XCV_TYPE RGMII
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_FEC_MXC_PHYADDR 0x01
#define CONFIG_MII
#define CONFIG_PHY_MICREL_KSZ9021
/* I2C Configs */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
#define CONFIG_SYS_I2C_MXC_I2C2
#define CONFIG_SYS_I2C_SPEED 100000
/* Filesystem support */
/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
#define CONFIG_SYS_INIT_SP_OFFSET \
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
/* MMC Configs */
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_FSL_USDHC_NUM 1
/* Environment organization */
#define CONFIG_ENV_SIZE (16 * 1024)
#define CONFIG_ENV_OFFSET (6 * 64 * 1024)
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
CONFIG_ENV_SIZE)
#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
/* Default environment */
#define CONFIG_EXTRA_ENV_SETTINGS \
"addcons=setenv bootargs ${bootargs} " \
"console=${console},${baudrate}\0" \
"addip=setenv bootargs ${bootargs} " \
"ip=${ipaddr}:${serverip}:${gatewayip}:" \
"${netmask}:${hostname}:${netdev}:off\0" \
"addmisc=setenv bootargs ${bootargs} ${miscargs}\0" \
"bootcmd=run mmcboot\0" \
"bootfile=uImage\0" \
"bootimage=uImage\0" \
"console=ttymxc0\0" \
"fdt_addr_r=0x18000000\0" \
"fdt_file=imx6dl-sks-cts.dtb\0" \
"fdt_high=0xffffffff\0" \
"kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
"miscargs=quiet\0" \
"mmcargs=setenv bootargs root=${mmcroot} rw rootwait\0" \
"mmcboot=if run mmcload;then " \
"run mmcargs addcons addmisc;" \
"bootm;fi\0" \
"mmcload=mmc rescan;" \
"load mmc 0:${mmcpart} ${kernel_addr_r} boot/fitImage\0"\
"mmcpart=1\0" \
"mmcroot=/dev/mmcblk0p1\0" \
"net_nfs=tftp ${kernel_addr_r} ${board_name}/${bootfile};" \
"tftp ${fdt_addr_r} ${board_name}/${fdt_file};" \
"run nfsargs addip addcons addmisc;" \
"bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
"nfsargs=setenv bootargs root=/dev/nfs " \
"nfsroot=${serverip}:${nfsroot},v3 panic=1\0"
#endif