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mxc: Define architecture identifier
Define ARCH_MXC for i.MX devices. This is useful to identify features or behaviors common to all i.MX SoCs. The i.MX28 is omitted because its architecture is a bit different (like imx/mxc vs. mxs in Linux). Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Andy Fleming <afleming@gmail.com> Cc: Kim Phillips <kim.phillips@freescale.com>
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@ -1,5 +1,8 @@
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#ifndef _IMX_REGS_H
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#define _IMX_REGS_H
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#define ARCH_MXC
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/* ------------------------------------------------------------------------
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* Motorola IMX system registers
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* ------------------------------------------------------------------------
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@ -172,6 +172,8 @@ struct aips_regs {
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#endif
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#define ARCH_MXC
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/* AIPS 1 */
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#define IMX_AIPS1_BASE (0x43F00000)
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#define IMX_MAX_BASE (0x43F04000)
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@ -196,6 +196,8 @@ struct fuse_bank0_regs {
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#endif
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#define ARCH_MXC
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#define IMX_IO_BASE 0x10000000
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#define IMX_AIPI1_BASE (0x00000 + IMX_IO_BASE)
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@ -541,6 +541,8 @@ struct esdc_regs {
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#endif
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#define ARCH_MXC
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#define __REG(x) (*((volatile u32 *)(x)))
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#define __REG16(x) (*((volatile u16 *)(x)))
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#define __REG8(x) (*((volatile u8 *)(x)))
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@ -25,6 +25,8 @@
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#ifndef __ASM_ARCH_MX35_H
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#define __ASM_ARCH_MX35_H
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#define ARCH_MXC
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/*
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* IRAM
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*/
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@ -23,6 +23,8 @@
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#ifndef __ASM_ARCH_MX5_IMX_REGS_H__
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#define __ASM_ARCH_MX5_IMX_REGS_H__
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#define ARCH_MXC
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#if defined(CONFIG_MX51)
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#define IRAM_BASE_ADDR 0x1FFE0000 /* internal ram */
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#define IPU_SOC_BASE_ADDR 0x40000000
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@ -19,6 +19,8 @@
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#ifndef __ASM_ARCH_MX6_IMX_REGS_H__
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#define __ASM_ARCH_MX6_IMX_REGS_H__
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#define ARCH_MXC
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#define CONFIG_SYS_CACHELINE_SIZE 32
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#define ROMCP_ARB_BASE_ADDR 0x00000000
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