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ppc4xx: Change LWMON5 to not use OCM for init-ram and POST anymore
This patch configures the LWMON5 port to use d-cache as init-ram and the unused GPT0_COMP6 as POST WORD storage. Signed-off-by: Stefan Roese <sr@denx.de>
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1754f50b71
commit
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3 changed files with 14 additions and 11 deletions
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@ -57,7 +57,7 @@ tlbtab:
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#ifdef CFG_INIT_RAM_DCACHE
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/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
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tlbentry(CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G)
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tlbentry(CFG_INIT_RAM_ADDR, SZ_4K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G)
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#endif
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/* TLB-entry for PCI Memory */
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@ -71,15 +71,20 @@
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/*-----------------------------------------------------------------------
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* Initial RAM & stack pointer
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*----------------------------------------------------------------------*/
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/* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */
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#define CFG_INIT_RAM_ADDR CFG_OCM_BASE /* OCM */
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#define CFG_OCM_DATA_ADDR CFG_OCM_BASE
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/*
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* On LWMON5 we use D-cache as init-ram and stack pointer. We also move
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* the POST_WORD from OCM to a 440EPx register that preserves it's
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* content during reset (GPT0_COM6). This way we reserve the OCM (16k)
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* for logbuffer only.
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*/
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#define CFG_INIT_RAM_DCACHE 1 /* d-cache as init ram */
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#define CFG_INIT_RAM_ADDR 0x70000000 /* DCache */
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#define CFG_INIT_RAM_END (4 << 10)
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#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data*/
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
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#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4)
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#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR
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#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
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#define CFG_POST_ALT_WORD_ADDR (CFG_PERIPHERAL_BASE + GPT0_COMP6)
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/* unused GPT0 COMP reg */
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/*-----------------------------------------------------------------------
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* Serial Port
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@ -1354,8 +1354,6 @@
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#define plb1_bearl (PLB_ARBITER_BASE+ 0x0C)
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#define plb1_bearh (PLB_ARBITER_BASE+ 0x0D)
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#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
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defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
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/* Pin Function Control Register 1 */
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#define SDR0_PFC1 0x4101
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#define SDR0_PFC1_U1ME_MASK 0x02000000 /* UART1 Mode Enable */
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@ -1421,7 +1419,7 @@
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#define SDR0_MFR_PKT_REJ_EN1 0x00080000 /* Pkt Rej. Enable on EMAC3(1) */
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#define SDR0_MFR_PKT_REJ_POL 0x00200000 /* Packet Reject Polarity */
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#endif /* defined(CONFIG_440EP) || defined(CONFIG_440GR) */
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#define GPT0_COMP6 0x00000098
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#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
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#define SDR0_USB2D0CR 0x0320
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