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spl:starfive: remove function spl_cpu_fre_150/125

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replace them with spl_cpu_set_rate.

Signed-off-by: samin <samin.guo@starfivetech.com>
This commit is contained in:
samin 2022-06-13 12:39:01 +08:00 • committed by Yanhong Wang
parent 61f294b11c
commit 90a8248c00
1 changed files with 0 additions and 33 deletions
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33
board/starfive/evb/spl.c
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@ -58,43 +58,10 @@ struct image_header *spl_get_load_buffer(ssize_t offset, size_t size)
return (struct image_header *)(STARFIVE_SPL_BOOT_LOAD_ADDR);
}
/* set PLL0 output to 1.5GHz*/
__maybe_unused static void spl_cpu_fre_150(void)
{
clrsetbits_le32(SYS_SYSCON_BASE + SYS_SYSCON_24, PLL0_DACPD_MASK,
BIT(PLL0_DACPD_SHIFT) & PLL0_DACPD_MASK);
clrsetbits_le32(SYS_SYSCON_BASE + SYS_SYSCON_24, PLL0_DSMPD_MASK,
BIT(PLL0_DSMPD_SHIFT) & PLL0_DSMPD_MASK);
clrsetbits_le32(SYS_SYSCON_BASE + SYS_SYSCON_36, PLL0_PREDIV_MASK,
BIT(PLL0_PREDIV_SHIFT) & PLL0_PREDIV_MASK);
clrsetbits_le32(SYS_SYSCON_BASE + SYS_SYSCON_28, PLL0_FBDIV_MASK,
(125 << PLL0_FBDIV_SHIFT) & PLL0_FBDIV_MASK);
clrsetbits_le32(SYS_SYSCON_BASE + SYS_SYSCON_32, PLL0_POSTDIV1_MASK,
BIT(PLL0_POSTDIV1_SHIFT) & PLL0_POSTDIV1_MASK);
}
/* set PLL0 output to 1.25GHz*/
static void spl_cpu_fre_125(void)
{
clrsetbits_le32(SYS_SYSCON_BASE + SYS_SYSCON_24, PLL0_DACPD_MASK,
BIT(PLL0_DACPD_SHIFT) & PLL0_DACPD_MASK);
clrsetbits_le32(SYS_SYSCON_BASE + SYS_SYSCON_24, PLL0_DSMPD_MASK,
BIT(PLL0_DSMPD_SHIFT) & PLL0_DSMPD_MASK);
clrsetbits_le32(SYS_SYSCON_BASE + SYS_SYSCON_36, PLL0_PREDIV_MASK,
BIT(PLL0_PREDIV_SHIFT) & PLL0_PREDIV_MASK);
clrsetbits_le32(SYS_SYSCON_BASE + SYS_SYSCON_28, PLL0_FBDIV_MASK,
(52 << PLL0_FBDIV_SHIFT) & PLL0_FBDIV_MASK);
clrsetbits_le32(SYS_SYSCON_BASE + SYS_SYSCON_32, PLL0_POSTDIV1_MASK,
(0 << PLL0_POSTDIV1_SHIFT) & PLL0_POSTDIV1_MASK);
}
void board_init_f(ulong dummy)
{
int ret;
spl_cpu_fre_125();
/*DDR control depend clk init*/
clrsetbits_le32(SYS_CRG_BASE, CLK_CPU_ROOT_SW_MASK,
BIT(CLK_CPU_ROOT_SW_SHIFT) & CLK_CPU_ROOT_SW_MASK);