mirror of
https://github.com/Fishwaldo/u-boot.git
synced 2025-03-18 13:11:31 +00:00
Xilinx/FPGA changes for v2020.04
ARM64: - Add INIT_SPL_RELATIVE dependency SPL: - FIT image fix - Enable customization of bl2_plat_get_bl31_params() Pytest: - Add test for octal/hex conversions Microblaze: - Fix manual relocation for one SPI instance Nand: - Convert zynq/zynqmp drivers to DM Xilinx: - Enable boot script location via Kconfig - Support OF_SEPARATE in board FDT selection - Remove low level uart setup it is done later by code - Add support for DEVICE_TREE variable passing for SPL Zynq: - Enable jtag boot mode via distro boot - Removing unused baseaddresses from hardware.h - DT fixups ZynqMP: - Fix emmc boot sequence - Simplify spl logic around bss and board_init_r() - Support psu_post_config_data() calling - Tune mini-nand DTS - Fix psu wiring for a2197 boards - Add runtime MMC device boot order filling in spl - Clear ATF handoff handling with custom bl2_plat_get_bl31_params() - Add support u-boot.its generation - Use single image configuration for all platforms - Enable PANIC_HANG via Kconfig - DT fixups - Firmware fixes - Add support for zcu208 and zcu1285 Versal: - Fix emmc boot sequence - Enable board_late_init() by default -----BEGIN PGP SIGNATURE----- iF0EABECAB0WIQQbPNTMvXmYlBPRwx7KSWXLKUoMIQUCXiAK2AAKCRDKSWXLKUoM IX3VAJ41GJXBwP7Z9hX9RFhsqOu0M+NdegCdFvMUaCQ1bSvgAMOnDL+JeB21+Qo= =qSbv -----END PGP SIGNATURE----- Merge tag 'xilinx-for-v2020.04' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze Xilinx/FPGA changes for v2020.04 ARM64: - Add INIT_SPL_RELATIVE dependency SPL: - FIT image fix - Enable customization of bl2_plat_get_bl31_params() Pytest: - Add test for octal/hex conversions Microblaze: - Fix manual relocation for one SPI instance Nand: - Convert zynq/zynqmp drivers to DM Xilinx: - Enable boot script location via Kconfig - Support OF_SEPARATE in board FDT selection - Remove low level uart setup it is done later by code - Add support for DEVICE_TREE variable passing for SPL Zynq: - Enable jtag boot mode via distro boot - Removing unused baseaddresses from hardware.h - DT fixups ZynqMP: - Fix emmc boot sequence - Simplify spl logic around bss and board_init_r() - Support psu_post_config_data() calling - Tune mini-nand DTS - Fix psu wiring for a2197 boards - Add runtime MMC device boot order filling in spl - Clear ATF handoff handling with custom bl2_plat_get_bl31_params() - Add support u-boot.its generation - Use single image configuration for all platforms - Enable PANIC_HANG via Kconfig - DT fixups - Firmware fixes - Add support for zcu208 and zcu1285 Versal: - Fix emmc boot sequence - Enable board_late_init() by default
This commit is contained in:
Tom Rini
commit
92329e2413
119 changed files with 1676 additions and 3898 deletions
3
Kconfig
3
Kconfig
|
|
@ -254,7 +254,7 @@ config BUILD_TARGET
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default "u-boot-spl.kwb" if ARCH_MVEBU && SPL
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default "u-boot-elf.srec" if RCAR_GEN3
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default "u-boot.itb" if SPL_LOAD_FIT && (ARCH_ROCKCHIP || \
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ARCH_SUNXI || RISCV)
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ARCH_SUNXI || RISCV || ARCH_ZYNQMP)
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default "u-boot.kwb" if KIRKWOOD
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default "u-boot-with-spl.bin" if ARCH_AT91 && SPL_NAND_SUPPORT
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default "u-boot-with-spl.imx" if ARCH_MX6 && SPL
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@ -500,6 +500,7 @@ config SPL_FIT_GENERATOR
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depends on SPL_FIT
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default "board/sunxi/mksunxi_fit_atf.sh" if SPL_LOAD_FIT && ARCH_SUNXI
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default "arch/arm/mach-rockchip/make_fit_atf.py" if SPL_LOAD_FIT && ARCH_ROCKCHIP
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default "arch/arm/mach-zynqmp/mkimage_fit_atf.sh" if SPL_LOAD_FIT && ARCH_ZYNQMP
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default "arch/riscv/lib/mkimage_fit_opensbi.sh" if SPL_LOAD_FIT && RISCV
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help
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Specifies a (platform specific) script file to generate the FIT
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@ -12,6 +12,7 @@ config ARM64
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if ARM64
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config POSITION_INDEPENDENT
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bool "Generate position-independent pre-relocation code"
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select INIT_SP_RELATIVE
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help
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U-Boot expects to be linked to a specific hard-coded address, and to
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be loaded to and run from that address. This option lifts that
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@ -282,6 +282,8 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \
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zynqmp-zcu111-revA.dtb \
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zynqmp-zcu1275-revA.dtb \
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zynqmp-zcu1275-revB.dtb \
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zynqmp-zcu1285-revA.dtb \
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zynqmp-zcu208-revA.dtb \
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zynqmp-zcu216-revA.dtb \
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zynqmp-zc1232-revA.dtb \
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zynqmp-zc1254-revA.dtb \
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@ -62,6 +62,39 @@
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regulator-always-on;
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};
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replicator {
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compatible = "arm,coresight-static-replicator";
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clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
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clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
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out-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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/* replicator output ports */
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port@0 {
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reg = <0>;
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replicator_out_port0: endpoint {
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remote-endpoint = <&tpiu_in_port>;
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};
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};
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port@1 {
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reg = <1>;
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replicator_out_port1: endpoint {
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remote-endpoint = <&etb_in_port>;
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};
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};
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};
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in-ports {
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/* replicator input port */
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port {
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replicator_in_port0: endpoint {
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remote-endpoint = <&funnel_out_port>;
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};
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};
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};
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};
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amba: amba {
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u-boot,dm-pre-reloc;
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compatible = "simple-bus";
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@ -415,5 +448,107 @@
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reg = <0xf8005000 0x1000>;
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timeout-sec = <10>;
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};
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etb@f8801000 {
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compatible = "arm,coresight-etb10", "arm,primecell";
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reg = <0xf8801000 0x1000>;
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clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
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clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
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in-ports {
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port {
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etb_in_port: endpoint {
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remote-endpoint = <&replicator_out_port1>;
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};
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};
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};
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};
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tpiu@f8803000 {
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compatible = "arm,coresight-tpiu", "arm,primecell";
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reg = <0xf8803000 0x1000>;
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clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
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clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
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in-ports {
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port {
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tpiu_in_port: endpoint {
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remote-endpoint = <&replicator_out_port0>;
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};
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};
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};
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};
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funnel@f8804000 {
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compatible = "arm,coresight-static-funnel", "arm,primecell";
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reg = <0xf8804000 0x1000>;
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clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
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clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
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/* funnel output ports */
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out-ports {
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port {
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funnel_out_port: endpoint {
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remote-endpoint =
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<&replicator_in_port0>;
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};
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};
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};
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in-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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/* funnel input ports */
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port@0 {
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reg = <0>;
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funnel0_in_port0: endpoint {
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remote-endpoint = <&ptm0_out_port>;
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};
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};
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port@1 {
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reg = <1>;
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funnel0_in_port1: endpoint {
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remote-endpoint = <&ptm1_out_port>;
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};
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};
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port@2 {
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reg = <2>;
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funnel0_in_port2: endpoint {
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};
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};
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/* The other input ports are not connect to anything */
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};
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};
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ptm@f889c000 {
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compatible = "arm,coresight-etm3x", "arm,primecell";
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reg = <0xf889c000 0x1000>;
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clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
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clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
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cpu = <&cpu0>;
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out-ports {
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port {
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ptm0_out_port: endpoint {
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remote-endpoint = <&funnel0_in_port0>;
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};
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};
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};
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};
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ptm@f889d000 {
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compatible = "arm,coresight-etm3x", "arm,primecell";
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reg = <0xf889d000 0x1000>;
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clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
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clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
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cpu = <&cpu1>;
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out-ports {
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port {
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ptm1_out_port: endpoint {
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remote-endpoint = <&funnel0_in_port1>;
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};
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};
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};
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};
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};
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};
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@ -47,6 +47,14 @@
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};
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};
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&nand0 {
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status = "okay";
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};
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&smcc {
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status = "okay";
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};
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&spi0 {
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status = "okay";
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num-cs = <4>;
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@ -2,7 +2,7 @@
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/*
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* Clock specification for Xilinx ZynqMP
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*
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* (C) Copyright 2017, Xilinx, Inc.
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* (C) Copyright 2017 - 2019, Xilinx, Inc.
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*
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* Michal Simek <michal.simek@xilinx.com>
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*/
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@ -173,26 +173,30 @@
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};
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&gem0 {
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clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM0_REF>, <&zynqmp_clk GEM0_TX>,
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<&zynqmp_clk GEM0_RX>, <&zynqmp_clk GEM_TSU>;
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clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM0_REF>,
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<&zynqmp_clk GEM0_TX>, <&zynqmp_clk GEM0_RX>,
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<&zynqmp_clk GEM_TSU>;
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clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
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};
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&gem1 {
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clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM1_REF>, <&zynqmp_clk GEM1_TX>,
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<&zynqmp_clk GEM1_RX>, <&zynqmp_clk GEM_TSU>;
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clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM1_REF>,
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<&zynqmp_clk GEM1_TX>, <&zynqmp_clk GEM1_RX>,
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<&zynqmp_clk GEM_TSU>;
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clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
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};
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&gem2 {
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clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM2_REF>, <&zynqmp_clk GEM2_TX>,
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<&zynqmp_clk GEM2_RX>, <&zynqmp_clk GEM_TSU>;
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clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM2_REF>,
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<&zynqmp_clk GEM2_TX>, <&zynqmp_clk GEM2_RX>,
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<&zynqmp_clk GEM_TSU>;
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clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
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};
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&gem3 {
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clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM3_REF>, <&zynqmp_clk GEM3_TX>,
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<&zynqmp_clk GEM3_RX>, <&zynqmp_clk GEM_TSU>;
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clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM3_REF>,
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<&zynqmp_clk GEM3_TX>, <&zynqmp_clk GEM3_RX>,
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<&zynqmp_clk GEM_TSU>;
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clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
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};
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|
|
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@ -61,13 +61,13 @@
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clock-accuracy = <100>;
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};
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dpdma_clk: dpdma_clk {
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dpdma_clk: dpdma-clk {
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compatible = "fixed-clock";
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#clock-cells = <0x0>;
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clock-frequency = <533000000>;
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};
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drm_clock: drm_clock {
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drm_clock: drm-clock {
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compatible = "fixed-clock";
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#clock-cells = <0x0>;
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clock-frequency = <262750000>;
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|
|
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@ -50,55 +50,6 @@
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#size-cells = <1>;
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arasan,has-mdma;
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num-cs = <2>;
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partition@0 { /* for testing purpose */
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label = "nand-fsbl-uboot";
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reg = <0x0 0x0 0x400000>;
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};
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partition@1 { /* for testing purpose */
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label = "nand-linux";
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reg = <0x0 0x400000 0x1400000>;
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};
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partition@2 { /* for testing purpose */
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label = "nand-device-tree";
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reg = <0x0 0x1800000 0x400000>;
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};
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partition@3 { /* for testing purpose */
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label = "nand-rootfs";
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reg = <0x0 0x1C00000 0x1400000>;
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};
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partition@4 { /* for testing purpose */
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label = "nand-bitstream";
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reg = <0x0 0x3000000 0x400000>;
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};
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partition@5 { /* for testing purpose */
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label = "nand-misc";
|
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reg = <0x0 0x3400000 0xFCC00000>;
|
||||
};
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||||
partition@6 { /* for testing purpose */
|
||||
label = "nand1-fsbl-uboot";
|
||||
reg = <0x1 0x0 0x400000>;
|
||||
};
|
||||
partition@7 { /* for testing purpose */
|
||||
label = "nand1-linux";
|
||||
reg = <0x1 0x400000 0x1400000>;
|
||||
};
|
||||
partition@8 { /* for testing purpose */
|
||||
label = "nand1-device-tree";
|
||||
reg = <0x1 0x1800000 0x400000>;
|
||||
};
|
||||
partition@9 { /* for testing purpose */
|
||||
label = "nand1-rootfs";
|
||||
reg = <0x1 0x1C00000 0x1400000>;
|
||||
};
|
||||
partition@10 { /* for testing purpose */
|
||||
label = "nand1-bitstream";
|
||||
reg = <0x1 0x3000000 0x400000>;
|
||||
};
|
||||
partition@11 { /* for testing purpose */
|
||||
label = "nand1-misc";
|
||||
reg = <0x1 0x3400000 0xFCC00000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -11,7 +11,7 @@
|
|||
/dts-v1/;
|
||||
|
||||
#include "zynqmp.dtsi"
|
||||
#include "zynqmp-clk.dtsi"
|
||||
#include "zynqmp-clk-ccf.dtsi"
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
|
@ -53,7 +53,7 @@
|
|||
label = "sw4";
|
||||
gpios = <&gpio 23 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_POWER>;
|
||||
gpio-key,wakeup;
|
||||
wakeup-source;
|
||||
autorepeat;
|
||||
};
|
||||
};
|
||||
|
|
@ -95,7 +95,7 @@
|
|||
linux,default-trigger = "bluetooth-power";
|
||||
};
|
||||
|
||||
vbus_det { /* U5 USB5744 VBUS detection via MIO25 */
|
||||
vbus-det { /* U5 USB5744 VBUS detection via MIO25 */
|
||||
label = "vbus_det";
|
||||
gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "on";
|
||||
|
|
@ -120,9 +120,10 @@
|
|||
regulator-boot-on;
|
||||
};
|
||||
|
||||
sdio_pwrseq: sdio_pwrseq {
|
||||
sdio_pwrseq: sdio-pwrseq {
|
||||
compatible = "mmc-pwrseq-simple";
|
||||
reset-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; /* WIFI_EN */
|
||||
post-power-on-delay-ms = <10>;
|
||||
};
|
||||
|
||||
ina226 {
|
||||
|
|
|
|||
|
|
@ -51,14 +51,14 @@
|
|||
label = "sw19";
|
||||
gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
|
||||
linux,code = <KEY_DOWN>;
|
||||
gpio-key,wakeup;
|
||||
wakeup-source;
|
||||
autorepeat;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
heartbeat_led {
|
||||
heartbeat-led {
|
||||
label = "heartbeat";
|
||||
gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
|
|
@ -213,25 +213,25 @@
|
|||
gpio-line-names = "PS_GTR_LAN_SEL0", "PS_GTR_LAN_SEL1", "PS_GTR_LAN_SEL2", "PS_GTR_LAN_SEL3",
|
||||
"PCI_CLK_DIR_SEL", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B",
|
||||
"", "", "", "", "", "", "", "", "";
|
||||
gtr_sel0 {
|
||||
gtr-sel0 {
|
||||
gpio-hog;
|
||||
gpios = <0 0>;
|
||||
output-low; /* PCIE = 0, DP = 1 */
|
||||
line-name = "sel0";
|
||||
};
|
||||
gtr_sel1 {
|
||||
gtr-sel1 {
|
||||
gpio-hog;
|
||||
gpios = <1 0>;
|
||||
output-high; /* PCIE = 0, DP = 1 */
|
||||
line-name = "sel1";
|
||||
};
|
||||
gtr_sel2 {
|
||||
gtr-sel2 {
|
||||
gpio-hog;
|
||||
gpios = <2 0>;
|
||||
output-high; /* PCIE = 0, USB0 = 1 */
|
||||
line-name = "sel2";
|
||||
};
|
||||
gtr_sel3 {
|
||||
gtr-sel3 {
|
||||
gpio-hog;
|
||||
gpios = <3 0>;
|
||||
output-high; /* PCIE = 0, SATA = 1 */
|
||||
|
|
|
|||
|
|
@ -25,7 +25,7 @@
|
|||
/* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */
|
||||
};
|
||||
/* Cleanup from RevA */
|
||||
/delete-node/ phy@21;
|
||||
/delete-node/ ethernet-phy@21;
|
||||
};
|
||||
|
||||
/* Fix collision with u61 */
|
||||
|
|
|
|||
|
|
@ -51,14 +51,14 @@
|
|||
label = "sw19";
|
||||
gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
|
||||
linux,code = <KEY_DOWN>;
|
||||
gpio-key,wakeup;
|
||||
wakeup-source;
|
||||
autorepeat;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
heartbeat_led {
|
||||
heartbeat-led {
|
||||
label = "heartbeat";
|
||||
gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
|
|
@ -653,7 +653,6 @@
|
|||
/* SD1 with level shifter */
|
||||
&sdhci1 {
|
||||
status = "okay";
|
||||
no-1-8-v;
|
||||
xlnx,mio_bank = <1>;
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -51,14 +51,14 @@
|
|||
label = "sw19";
|
||||
gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
|
||||
linux,code = <KEY_DOWN>;
|
||||
gpio-key,wakeup;
|
||||
wakeup-source;
|
||||
autorepeat;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
heartbeat_led {
|
||||
heartbeat-led {
|
||||
label = "heartbeat";
|
||||
gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
|
|
@ -566,7 +566,6 @@
|
|||
/* SD1 with level shifter */
|
||||
&sdhci1 {
|
||||
status = "okay";
|
||||
no-1-8-v;
|
||||
disable-wp;
|
||||
xlnx,mio_bank = <1>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -75,6 +75,10 @@
|
|||
|
||||
&sdhci1 {
|
||||
status = "okay";
|
||||
/*
|
||||
* 1.0 revision has level shifter and this property should be
|
||||
* removed for supporting UHS mode
|
||||
*/
|
||||
no-1-8-v;
|
||||
xlnx,mio_bank = <1>;
|
||||
};
|
||||
|
|
|
|||
245
arch/arm/dts/zynqmp-zcu1285-revA.dts
Normal file
245
arch/arm/dts/zynqmp-zcu1285-revA.dts
Normal file
|
|
@ -0,0 +1,245 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* dts file for Xilinx ZynqMP ZCU1285 RevA
|
||||
*
|
||||
* (C) Copyright 2018 - 2019, Xilinx, Inc.
|
||||
*
|
||||
* Michal Simek <michal.simek@xilinx.com>
|
||||
* Siva Durga Prasad Paladugu <sivadur@xilinx.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "zynqmp.dtsi"
|
||||
#include "zynqmp-clk-ccf.dtsi"
|
||||
|
||||
/ {
|
||||
model = "ZynqMP ZCU1285 RevA";
|
||||
compatible = "xlnx,zynqmp-zcu1285-revA", "xlnx,zynqmp-zcu1285",
|
||||
"xlnx,zynqmp";
|
||||
|
||||
aliases {
|
||||
serial0 = &uart0;
|
||||
serial1 = &dcc;
|
||||
spi0 = &qspi;
|
||||
mmc0 = &sdhci1;
|
||||
i2c = &i2c0; /* EMIO */
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs = "earlycon";
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x0 0x0 0x80000000>;
|
||||
};
|
||||
|
||||
ina226-u60 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u60 0>, <&u60 1>, <&u60 2>, <&u60 3>;
|
||||
};
|
||||
ina226-u61 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u61 0>, <&u61 1>, <&u61 2>, <&u61 3>;
|
||||
};
|
||||
ina226-u63 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u63 0>, <&u63 1>, <&u63 2>, <&u63 3>;
|
||||
};
|
||||
ina226-u65 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;
|
||||
};
|
||||
ina226-u64 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u64 0>, <&u64 1>, <&u64 2>, <&u64 3>;
|
||||
};
|
||||
};
|
||||
|
||||
&dcc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
i2c-mux@75 {
|
||||
compatible = "nxp,pca9548"; /* u22 */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x75>;
|
||||
|
||||
i2c@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0>;
|
||||
/* PMBUS */
|
||||
max20751@74 { /* u23 */
|
||||
compatible = "maxim,max20751";
|
||||
reg = <0x74>;
|
||||
};
|
||||
max20751@70 { /* u89 */
|
||||
compatible = "maxim,max20751";
|
||||
reg = <0x70>;
|
||||
};
|
||||
max15301@a { /* u28 */
|
||||
compatible = "maxim,max15301";
|
||||
reg = <0xa>;
|
||||
};
|
||||
max15303@b { /* u48 */
|
||||
compatible = "maxim,max15303";
|
||||
reg = <0xb>;
|
||||
};
|
||||
max15303@d { /* u27 */
|
||||
compatible = "maxim,max15303";
|
||||
reg = <0xd>;
|
||||
};
|
||||
max15303@e { /* u11 */
|
||||
compatible = "maxim,max15303";
|
||||
reg = <0xe>;
|
||||
};
|
||||
max15303@f { /* u96 */
|
||||
compatible = "maxim,max15303";
|
||||
reg = <0xf>;
|
||||
};
|
||||
max15303@11 { /* u47 */
|
||||
compatible = "maxim,max15303";
|
||||
reg = <0x11>;
|
||||
};
|
||||
max15303@12 { /* u24 */
|
||||
compatible = "maxim,max15303";
|
||||
reg = <0x12>;
|
||||
};
|
||||
max15301@13 { /* u29 */
|
||||
compatible = "maxim,max15301";
|
||||
reg = <0x13>;
|
||||
};
|
||||
max15303@14 { /* u51 */
|
||||
compatible = "maxim,max15303";
|
||||
reg = <0x14>;
|
||||
};
|
||||
max15303@15 { /* u30 */
|
||||
compatible = "maxim,max15303";
|
||||
reg = <0x15>;
|
||||
};
|
||||
max15303@16 { /* u102 */
|
||||
compatible = "maxim,max15303";
|
||||
reg = <0x16>;
|
||||
};
|
||||
max15301@17 { /* u50 */
|
||||
compatible = "maxim,max15301";
|
||||
reg = <0x17>;
|
||||
};
|
||||
max15301@18 { /* u31 */
|
||||
compatible = "maxim,max15301";
|
||||
reg = <0x18>;
|
||||
};
|
||||
};
|
||||
i2c@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <1>;
|
||||
/* CM_I2C */
|
||||
};
|
||||
i2c@2 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <2>;
|
||||
/* SYS_EEPROM */
|
||||
eeprom: eeprom@54 { /* u101 */
|
||||
compatible = "atmel,24c32"; /* 24LC32A */
|
||||
reg = <0x54>;
|
||||
};
|
||||
};
|
||||
i2c@3 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <3>;
|
||||
/* FMC1 */
|
||||
};
|
||||
i2c@4 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <4>;
|
||||
/* FMC2 */
|
||||
};
|
||||
i2c@5 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <5>;
|
||||
/* ANALOG_PMBUS */
|
||||
u60: ina226@40 { /* u60 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-u60";
|
||||
reg = <0x40>;
|
||||
shunt-resistor = <1000>;
|
||||
};
|
||||
u61: ina226@41 { /* u61 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-u61";
|
||||
reg = <0x41>;
|
||||
shunt-resistor = <1000>;
|
||||
};
|
||||
u63: ina226@42 { /* u63 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-u63";
|
||||
reg = <0x42>;
|
||||
shunt-resistor = <1000>;
|
||||
};
|
||||
u65: ina226@43 { /* u65 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-u65";
|
||||
reg = <0x43>;
|
||||
shunt-resistor = <1000>;
|
||||
};
|
||||
u64: ina226@44 { /* u64 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-u64";
|
||||
reg = <0x44>;
|
||||
shunt-resistor = <1000>;
|
||||
};
|
||||
};
|
||||
i2c@6 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <6>;
|
||||
/* ANALOG_CM_I2C */
|
||||
};
|
||||
i2c@7 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <7>;
|
||||
/* FMC3 */
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&qspi {
|
||||
status = "okay";
|
||||
flash@0 {
|
||||
compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x0>;
|
||||
spi-tx-bus-width = <1>;
|
||||
spi-rx-bus-width = <1>;
|
||||
spi-max-frequency = <108000000>; /* Based on DC1 spec */
|
||||
};
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhci1 {
|
||||
status = "okay";
|
||||
xlnx,mio_bank = <1>;
|
||||
};
|
||||
588
arch/arm/dts/zynqmp-zcu208-revA.dts
Normal file
588
arch/arm/dts/zynqmp-zcu208-revA.dts
Normal file
|
|
@ -0,0 +1,588 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* dts file for Xilinx ZynqMP ZCU208
|
||||
*
|
||||
* (C) Copyright 2017 - 2019, Xilinx, Inc.
|
||||
*
|
||||
* Michal Simek <michal.simek@xilinx.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "zynqmp.dtsi"
|
||||
#include "zynqmp-clk-ccf.dtsi"
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/phy/phy.h>
|
||||
|
||||
/ {
|
||||
model = "ZynqMP ZCU208 RevA";
|
||||
compatible = "xlnx,zynqmp-zcu208-revA", "xlnx,zynqmp-zcu208", "xlnx,zynqmp";
|
||||
|
||||
aliases {
|
||||
ethernet0 = &gem3;
|
||||
gpio0 = &gpio;
|
||||
i2c0 = &i2c0;
|
||||
i2c1 = &i2c1;
|
||||
mmc0 = &sdhci1;
|
||||
rtc0 = &rtc;
|
||||
serial0 = &uart0;
|
||||
serial1 = &dcc;
|
||||
spi0 = &qspi;
|
||||
usb0 = &usb0;
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs = "earlycon";
|
||||
stdout-path = "serial0:115200n8";
|
||||
xlnx,eeprom = &eeprom;
|
||||
};
|
||||
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
autorepeat;
|
||||
sw19 {
|
||||
label = "sw19";
|
||||
gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
|
||||
linux,code = <KEY_DOWN>;
|
||||
gpio-key,wakeup;
|
||||
autorepeat;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
heartbeat_led {
|
||||
label = "heartbeat";
|
||||
gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
};
|
||||
|
||||
ina226-vccint {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>;
|
||||
};
|
||||
ina226-vccint-io-bram-ps {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>;
|
||||
};
|
||||
ina226-vcc1v8 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>;
|
||||
};
|
||||
ina226-vcc1v2 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>;
|
||||
};
|
||||
ina226-vadj-fmc {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>;
|
||||
};
|
||||
ina226-mgtavcc {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>;
|
||||
};
|
||||
ina226-mgt1v2 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>;
|
||||
};
|
||||
ina226-mgt1v8 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>;
|
||||
};
|
||||
ina226-vccint-ams {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>;
|
||||
};
|
||||
ina226-dac-avtt {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>;
|
||||
};
|
||||
ina226-dac-avccaux {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>, <&dac_avccaux 3>;
|
||||
};
|
||||
ina226-adc-avcc {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>;
|
||||
};
|
||||
ina226-adc-avccaux {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>, <&adc_avccaux 3>;
|
||||
};
|
||||
ina226-dac-avcc {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>;
|
||||
};
|
||||
};
|
||||
|
||||
&dcc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan4 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan5 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan6 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan7 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan8 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gem3 {
|
||||
status = "okay";
|
||||
phy-handle = <&phy0>;
|
||||
phy-mode = "rgmii-id";
|
||||
phy0: ethernet-phy@c {
|
||||
reg = <0xc>;
|
||||
ti,rx-internal-delay = <0x8>;
|
||||
ti,tx-internal-delay = <0xa>;
|
||||
ti,fifo-depth = <0x1>;
|
||||
ti,dp83867-rxctrl-strap-quirk;
|
||||
};
|
||||
};
|
||||
|
||||
&gpio {
|
||||
status = "okay";
|
||||
gpio-line-names = "QSPI_LWR_CLK", "QSPI_LWR_DQ1", "QSPI_LWR_DQ2", "QSPI_LWR_DQ3", "QSPI_LWR_DQ0", /* 0 - 4 */
|
||||
"QSPI_LWR_CS_B", "", "QSPI_UPR_CS_B", "QSPI_UPR_DQ0", "QSPI_UPR_DQ1", /* 5 - 9 */
|
||||
"QSPI_UPR_DQ2", "QSPI_UPR_DQ3", "QSPI_UPR_CLK", "PS_GPIO2", "I2C0_SCL", /* 10 - 14 */
|
||||
"I2C0_SDA", "I2C1_SCL", "I2C1_SDA", "UART0_TXD", "UART0_RXD", /* 15 - 19 */
|
||||
"", "", "BUTTON", "LED", "", /* 20 - 24 */
|
||||
"", "PMU_INPUT", "", "", "", /* 25 - 29 */
|
||||
"", "", "PMU_GPO0", "PMU_GPO1", "PMU_GPO2", /* 30 - 34 */
|
||||
"PMU_GPO3", "PMU_GPO4", "PMU_GPO5", "PS_GPIO1", "SDIO_SEL", /* 35 - 39 */
|
||||
"SDIO_DIR_CMD", "SDIO_DIR_DAT0", "SDIO_DIR_DAT1", "", "", /* 40 - 44 */
|
||||
"SDIO_DETECT", "SDIO_DAT0", "SDIO_DAT1", "SDIO_DAT2", "SDIO_DAT3", /* 45 - 49 */
|
||||
"SDIO_CMD", "SDIO_CLK", "USB_CLK", "USB_DIR", "USB_DATA2", /* 50 - 54 */
|
||||
"USB_NXT", "USB_DATA0", "USB_DATA1", "USB_STP", "USB_DATA3", /* 55 - 59 */
|
||||
"USB_DATA4", "USB_DATA5", "USB_DATA6", "USB_DATA7", "ENET_TX_CLK", /* 60 - 64 */
|
||||
"ENET_TX_D0", "ENET_TX_D1", "ENET_TX_D2", "ENET_TX_D3", "ENET_TX_CTRL", /* 65 - 69 */
|
||||
"ENET_RX_CLK", "ENET_RX_D0", "ENET_RX_D1", "ENET_RX_D2", "ENET_RX_D3", /* 70 - 74 */
|
||||
"ENET_RX_CTRL", "ENET_MDC", "ENET_MDIO", /* 75 - 77, MIO end and EMIO start */
|
||||
"", "", /* 78 - 79 */
|
||||
"", "", "", "", "", /* 80 - 84 */
|
||||
"", "", "", "", "", /* 85 -89 */
|
||||
"", "", "", "", "", /* 90 - 94 */
|
||||
"", "", "", "", "", /* 95 - 99 */
|
||||
"", "", "", "", "", /* 100 - 104 */
|
||||
"", "", "", "", "", /* 105 - 109 */
|
||||
"", "", "", "", "", /* 110 - 114 */
|
||||
"", "", "", "", "", /* 115 - 119 */
|
||||
"", "", "", "", "", /* 120 - 124 */
|
||||
"", "", "", "", "", /* 125 - 129 */
|
||||
"", "", "", "", "", /* 130 - 134 */
|
||||
"", "", "", "", "", /* 135 - 139 */
|
||||
"", "", "", "", "", /* 140 - 144 */
|
||||
"", "", "", "", "", /* 145 - 149 */
|
||||
"", "", "", "", "", /* 150 - 154 */
|
||||
"", "", "", "", "", /* 155 - 159 */
|
||||
"", "", "", "", "", /* 160 - 164 */
|
||||
"", "", "", "", "", /* 165 - 169 */
|
||||
"", "", "", ""; /* 170 - 174 */
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
tca6416_u15: gpio@20 { /* u15 */
|
||||
compatible = "ti,tca6416";
|
||||
reg = <0x20>;
|
||||
gpio-controller; /* interrupt not connected */
|
||||
#gpio-cells = <2>;
|
||||
gpio-line-names = "MAX6643_OT_B", "MAX6643_FANFAIL_B", "MIO26_PMU_INPUT_LS", "DAC_AVTT_VOUT_SEL", /* 0 - 3 */
|
||||
"", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B", "MAX6643_FULL_SPEED", /* 4 - 7 */
|
||||
"FMCP_HSPC_PRSNT_M2C_B", "", "", "VCCINT_VRHOT_B", /* 10 - 13 */
|
||||
"", "8A34001_EXP_RST_B", "IRPS5401_ALERT_B", "INA226_PMBUS_ALERT"; /* 14 - 17 */
|
||||
};
|
||||
|
||||
i2c-mux@75 { /* u17 */
|
||||
compatible = "nxp,pca9544";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x75>;
|
||||
i2c@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0>;
|
||||
/* PS_PMBUS */
|
||||
/* PMBUS_ALERT done via pca9544 */
|
||||
vccint: ina226@40 { /* u65 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-vccint";
|
||||
reg = <0x40>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
vccint_io_bram_ps: ina226@41 { /* u57 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-vccint-io-bram-ps";
|
||||
reg = <0x41>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
vcc1v8: ina226@42 { /* u60 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-vcc1v8";
|
||||
reg = <0x42>;
|
||||
shunt-resistor = <2000>;
|
||||
};
|
||||
vcc1v2: ina226@43 { /* u58 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-vcc1v2";
|
||||
reg = <0x43>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
vadj_fmc: ina226@45 { /* u62 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-vadj-fmc";
|
||||
reg = <0x45>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
mgtavcc: ina226@46 { /* u67 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-mgtavcc";
|
||||
reg = <0x46>;
|
||||
shunt-resistor = <2000>;
|
||||
};
|
||||
mgt1v2: ina226@47 { /* u63 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-mgt1v2";
|
||||
reg = <0x47>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
mgt1v8: ina226@48 { /* u64 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-mgt1v8";
|
||||
reg = <0x48>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
vccint_ams: ina226@49 { /* u61 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-vccint-ams";
|
||||
reg = <0x49>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
dac_avtt: ina226@4a { /* u59 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-dac-avtt";
|
||||
reg = <0x4a>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
dac_avccaux: ina226@4b { /* u124 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-dac-avccaux";
|
||||
reg = <0x4b>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
adc_avcc: ina226@4c { /* u75 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-adc-avcc";
|
||||
reg = <0x4c>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
adc_avccaux: ina226@4d { /* u71 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-adc-avccaux";
|
||||
reg = <0x4d>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
dac_avcc: ina226@4e { /* u77 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-dac-avcc";
|
||||
reg = <0x4e>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
};
|
||||
i2c@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <1>;
|
||||
/* NC */
|
||||
};
|
||||
i2c@2 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <2>;
|
||||
/* u104 - ir35215 0x10/0x40 */
|
||||
/* u127 - ir38164 0x1b/0x4b */
|
||||
/* u112 - ir38164 0x13/0x43 */
|
||||
/* u123 - ir38164 0x1c/0x4c */
|
||||
|
||||
irps5401_44: irps54012@44 { /* IRPS5401 - u53 */
|
||||
#clock-cells = <0>;
|
||||
compatible = "infineon,irps5401";
|
||||
reg = <0x44>; /* i2c addr 0x14 */
|
||||
};
|
||||
irps5401_45: irps54012@45 { /* IRPS5401 - u55 */
|
||||
#clock-cells = <0>;
|
||||
compatible = "infineon,irps5401";
|
||||
reg = <0x45>; /* i2c addr 0x15 */
|
||||
};
|
||||
/* J21 header too */
|
||||
|
||||
};
|
||||
i2c@3 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <3>;
|
||||
/* SYSMON */
|
||||
};
|
||||
};
|
||||
/* u38 MPS430 */
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
i2c-mux@74 {
|
||||
compatible = "nxp,pca9548"; /* u20 */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x74>;
|
||||
/* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */
|
||||
i2c_eeprom: i2c@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0>;
|
||||
/*
|
||||
* IIC_EEPROM 1kB memory which uses 256B blocks
|
||||
* where every block has different address.
|
||||
* 0 - 256B address 0x54
|
||||
* 256B - 512B address 0x55
|
||||
* 512B - 768B address 0x56
|
||||
* 768B - 1024B address 0x57
|
||||
*/
|
||||
eeprom: eeprom@54 { /* u21 */
|
||||
compatible = "atmel,24c128";
|
||||
reg = <0x54>;
|
||||
};
|
||||
};
|
||||
i2c_si5341: i2c@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <1>;
|
||||
si5341: clock-generator@36 { /* SI5341 - u43 */
|
||||
compatible = "si5341";
|
||||
reg = <0x36>;
|
||||
};
|
||||
|
||||
};
|
||||
i2c_si570_user_c0: i2c@2 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <2>;
|
||||
si570_1: clock-generator@5d { /* USER C0 SI570 - u47 */
|
||||
#clock-cells = <0>;
|
||||
compatible = "silabs,si570";
|
||||
reg = <0x5d>;
|
||||
temperature-stability = <50>;
|
||||
factory-fout = <300000000>;
|
||||
clock-frequency = <300000000>;
|
||||
clock-output-names = "si570_user_c0";
|
||||
};
|
||||
};
|
||||
i2c_si570_mgt: i2c@3 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <3>;
|
||||
si570_2: clock-generator@5d { /* USER MGT SI570 - u48 */
|
||||
#clock-cells = <0>;
|
||||
compatible = "silabs,si570";
|
||||
reg = <0x5d>;
|
||||
temperature-stability = <50>;
|
||||
factory-fout = <156250000>;
|
||||
clock-frequency = <148500000>;
|
||||
clock-output-names = "si570_mgt";
|
||||
};
|
||||
};
|
||||
i2c_8a34001: i2c@4 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <4>;
|
||||
/* U409B - 8a34001 */
|
||||
};
|
||||
i2c_clk104: i2c@5 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <5>;
|
||||
/* CLK104_SDA */
|
||||
};
|
||||
i2c@6 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <6>;
|
||||
/* RFMCP connector */
|
||||
};
|
||||
/* 7 NC */
|
||||
};
|
||||
|
||||
i2c-mux@75 {
|
||||
compatible = "nxp,pca9548"; /* u22 */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x75>;
|
||||
/* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */
|
||||
i2c@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0>;
|
||||
/* FMCP_HSPC_IIC */
|
||||
};
|
||||
i2c_si570_user_c1: i2c@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <1>;
|
||||
si570_3: clock-generator@5d { /* USER C1 SI570 - u130 */
|
||||
#clock-cells = <0>;
|
||||
compatible = "silabs,si570";
|
||||
reg = <0x5d>;
|
||||
temperature-stability = <50>;
|
||||
factory-fout = <300000000>;
|
||||
clock-frequency = <300000000>;
|
||||
clock-output-names = "si570_user_c1";
|
||||
};
|
||||
};
|
||||
i2c@2 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <2>;
|
||||
/* SYSMON */
|
||||
};
|
||||
i2c@3 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <3>;
|
||||
/* DDR4 SODIMM */
|
||||
};
|
||||
i2c@4 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <4>;
|
||||
/* SFP3 */
|
||||
};
|
||||
i2c@5 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <5>;
|
||||
/* SFP2 */
|
||||
};
|
||||
i2c@6 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <6>;
|
||||
/* SFP1 */
|
||||
};
|
||||
i2c@7 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <7>;
|
||||
/* SFP0 */
|
||||
};
|
||||
};
|
||||
/* MSP430 */
|
||||
};
|
||||
|
||||
&qspi {
|
||||
status = "okay";
|
||||
is-dual = <1>;
|
||||
flash@0 {
|
||||
compatible = "m25p80", "jedec,spi-nor"; /* U11 and U12 MT25QU02GCBBE12 1Gb */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0>;
|
||||
spi-tx-bus-width = <1>;
|
||||
spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
|
||||
spi-max-frequency = <108000000>; /* Based on DC1 spec */
|
||||
};
|
||||
};
|
||||
|
||||
&rtc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sata {
|
||||
status = "okay";
|
||||
/* SATA OOB timing settings */
|
||||
ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
|
||||
ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
|
||||
ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
|
||||
ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
|
||||
ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
|
||||
ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
|
||||
ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
|
||||
ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
|
||||
phy-names = "sata-phy";
|
||||
phys = <&lane3 PHY_TYPE_SATA 1 3 125000000>;
|
||||
};
|
||||
|
||||
/* SD1 with level shifter */
|
||||
&sdhci1 {
|
||||
status = "okay";
|
||||
disable-wp;
|
||||
xlnx,mio_bank = <1>;
|
||||
};
|
||||
|
||||
&serdes {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* ULPI SMSC USB3320 */
|
||||
&usb0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&dwc3_0 {
|
||||
status = "okay";
|
||||
dr_mode = "host";
|
||||
snps,usb3_lpm_capable;
|
||||
phy-names = "usb3-phy";
|
||||
phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;
|
||||
};
|
||||
|
|
@ -253,7 +253,7 @@
|
|||
#io-channel-cells = <1>;
|
||||
label = "ina226-vccint-io-bram-ps";
|
||||
reg = <0x41>;
|
||||
shunt-resistor = <2000>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
vcc1v8: ina226@42 { /* u60 */
|
||||
compatible = "ti,ina226";
|
||||
|
|
@ -302,7 +302,7 @@
|
|||
#io-channel-cells = <1>;
|
||||
label = "ina226-vccint-ams";
|
||||
reg = <0x49>;
|
||||
shunt-resistor = <2000>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
dac_avtt: ina226@4a { /* u59 */
|
||||
compatible = "ti,ina226";
|
||||
|
|
@ -401,7 +401,7 @@
|
|||
* 768B - 1024B address 0x57
|
||||
*/
|
||||
eeprom: eeprom@54 { /* u21 */
|
||||
compatible = "atmel,24c08";
|
||||
compatible = "atmel,24c128";
|
||||
reg = <0x54>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -25,7 +25,7 @@
|
|||
#size-cells = <0>;
|
||||
|
||||
cpu0: cpu@0 {
|
||||
compatible = "arm,cortex-a53", "arm,armv8";
|
||||
compatible = "arm,cortex-a53";
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
operating-points-v2 = <&cpu_opp_table>;
|
||||
|
|
@ -34,7 +34,7 @@
|
|||
};
|
||||
|
||||
cpu1: cpu@1 {
|
||||
compatible = "arm,cortex-a53", "arm,armv8";
|
||||
compatible = "arm,cortex-a53";
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
reg = <0x1>;
|
||||
|
|
@ -43,7 +43,7 @@
|
|||
};
|
||||
|
||||
cpu2: cpu@2 {
|
||||
compatible = "arm,cortex-a53", "arm,armv8";
|
||||
compatible = "arm,cortex-a53";
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
reg = <0x2>;
|
||||
|
|
@ -52,7 +52,7 @@
|
|||
};
|
||||
|
||||
cpu3: cpu@3 {
|
||||
compatible = "arm,cortex-a53", "arm,armv8";
|
||||
compatible = "arm,cortex-a53";
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
reg = <0x3>;
|
||||
|
|
@ -74,7 +74,7 @@
|
|||
};
|
||||
};
|
||||
|
||||
cpu_opp_table: cpu_opp_table {
|
||||
cpu_opp_table: cpu-opp-table {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
opp00 {
|
||||
|
|
@ -252,7 +252,7 @@
|
|||
};
|
||||
};
|
||||
|
||||
amba_apu: amba_apu@0 {
|
||||
amba_apu: amba-apu@0 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
|
|
@ -626,12 +626,12 @@
|
|||
compatible = "xlnx,zynqmp-gpio-1.0";
|
||||
status = "disabled";
|
||||
#gpio-cells = <0x2>;
|
||||
gpio-controller;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 16 4>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x0 0xff0a0000 0x0 0x1000>;
|
||||
gpio-controller;
|
||||
power-domains = <&zynqmp_firmware PD_GPIO>;
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -9,13 +9,8 @@
|
|||
#define ZYNQ_SYS_CTRL_BASEADDR 0xF8000000
|
||||
#define ZYNQ_DEV_CFG_APB_BASEADDR 0xF8007000
|
||||
#define ZYNQ_SCU_BASEADDR 0xF8F00000
|
||||
#define ZYNQ_QSPI_BASEADDR 0xE000D000
|
||||
#define ZYNQ_SMC_BASEADDR 0xE000E000
|
||||
#define ZYNQ_NAND_BASEADDR 0xE1000000
|
||||
#define ZYNQ_DDRC_BASEADDR 0xF8006000
|
||||
#define ZYNQ_EFUSE_BASEADDR 0xF800D000
|
||||
#define ZYNQ_USB_BASEADDR0 0xE0002000
|
||||
#define ZYNQ_USB_BASEADDR1 0xE0003000
|
||||
#define ZYNQ_OCM_BASEADDR 0xFFFC0000
|
||||
|
||||
/* Bootmode setting values */
|
||||
|
|
|
|||
|
|
@ -117,17 +117,6 @@ config SPL_ZYNQMP_ALT_BOOTMODE_ENABLED
|
|||
config ZYNQ_SDHCI_MAX_FREQ
|
||||
default 200000000
|
||||
|
||||
config SPL_ZYNQMP_TWO_SDHCI
|
||||
bool "Enable booting from both SDHCIs"
|
||||
depends on SPL
|
||||
help
|
||||
This option reflects that board has two SDHCI controllers which
|
||||
platform can use as boot device. This option ensures that SPL will
|
||||
setup BOOT_DEVICE_MMC2 for SDHCI1 controller and BOOT_DEVICE_MMC1 for
|
||||
SDHCI0 controller. Platforms which have only one SDHCI controller
|
||||
shouldn't enable this option because it for software SDHCI0 or SDHCI1
|
||||
are both covered by BOOT_DEVICE_MMC1.
|
||||
|
||||
config SPL_ZYNQMP_ALT_BOOTMODE
|
||||
hex
|
||||
default 0x0 if JTAG_MODE
|
||||
|
|
|
|||
|
|
@ -66,7 +66,9 @@ struct xfsbl_atf_handoff_params {
|
|||
};
|
||||
|
||||
#ifdef CONFIG_SPL_OS_BOOT
|
||||
void handoff_setup(void)
|
||||
struct bl31_params *bl2_plat_get_bl31_params(uintptr_t bl32_entry,
|
||||
uintptr_t bl33_entry,
|
||||
uintptr_t fdt_addr)
|
||||
{
|
||||
struct xfsbl_atf_handoff_params *atfhandoffparams;
|
||||
|
||||
|
|
@ -76,11 +78,16 @@ void handoff_setup(void)
|
|||
atfhandoffparams->magic[2] = 'N';
|
||||
atfhandoffparams->magic[3] = 'X';
|
||||
|
||||
atfhandoffparams->num_entries = 1;
|
||||
atfhandoffparams->partition[0].entry_point = CONFIG_SYS_TEXT_BASE;
|
||||
atfhandoffparams->partition[0].flags = FSBL_FLAGS_EL2 <<
|
||||
FSBL_FLAGS_EL_SHIFT;
|
||||
atfhandoffparams->num_entries = 0;
|
||||
if (bl33_entry) {
|
||||
atfhandoffparams->partition[0].entry_point = bl33_entry;
|
||||
atfhandoffparams->partition[0].flags = FSBL_FLAGS_EL2 <<
|
||||
FSBL_FLAGS_EL_SHIFT;
|
||||
atfhandoffparams->num_entries++;
|
||||
}
|
||||
|
||||
writel(CONFIG_SPL_TEXT_BASE, &pmu_base->gen_storage6);
|
||||
|
||||
return NULL;
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -7,8 +7,6 @@
|
|||
#ifndef _ASM_ARCH_HARDWARE_H
|
||||
#define _ASM_ARCH_HARDWARE_H
|
||||
|
||||
#define ARASAN_NAND_BASEADDR 0xFF100000
|
||||
|
||||
#define ZYNQMP_TCM_BASE_ADDR 0xFFE00000
|
||||
#define ZYNQMP_TCM_SIZE 0x40000
|
||||
|
||||
|
|
|
|||
|
|
@ -21,5 +21,6 @@ void prog_reg(unsigned long addr, unsigned long mask,
|
|||
unsigned long shift, unsigned long value);
|
||||
|
||||
int psu_init(void);
|
||||
unsigned long psu_post_config_data(void);
|
||||
|
||||
#endif /* _PSU_INIT_GPL_H_ */
|
||||
|
|
|
|||
|
|
@ -46,8 +46,6 @@ struct zynqmp_ipi_msg {
|
|||
int zynq_board_read_rom_ethaddr(unsigned char *ethaddr);
|
||||
unsigned int zynqmp_get_silicon_version(void);
|
||||
|
||||
void handoff_setup(void);
|
||||
|
||||
int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value);
|
||||
int zynqmp_mmio_read(const u32 address, u32 *value);
|
||||
|
||||
|
|
|
|||
123
arch/arm/mach-zynqmp/mkimage_fit_atf.sh
Executable file
123
arch/arm/mach-zynqmp/mkimage_fit_atf.sh
Executable file
|
|
@ -0,0 +1,123 @@
|
|||
#!/bin/sh
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
# script to generate FIT image source for Xilinx ZynqMP boards with
|
||||
# ARM Trusted Firmware and multiple device trees (given on the command line)
|
||||
#
|
||||
# usage: $0 <dt_name> [<dt_name> [<dt_name] ...]
|
||||
|
||||
BL33="u-boot-nodtb.bin"
|
||||
[ -z "$BL31" ] && BL31="bl31.bin"
|
||||
# Can be also done as ${CROSS_COMPILE}readelf -l bl31.elf | awk '/Entry point/ { print $3 }'
|
||||
[ -z "$ATF_LOAD_ADDR" ] && ATF_LOAD_ADDR="0xfffea000"
|
||||
|
||||
if [ -z "$BL33_LOAD_ADDR" ];then
|
||||
BL33_LOAD_ADDR=`awk '/CONFIG_SYS_TEXT_BASE/ { print $3 }' include/generated/autoconf.h`
|
||||
fi
|
||||
|
||||
DTB_LOAD_ADDR=`awk '/CONFIG_XILINX_OF_BOARD_DTB_ADDR/ { print $3 }' include/generated/autoconf.h`
|
||||
if [ ! -z "$DTB_LOAD_ADDR" ]; then
|
||||
DTB_LOAD="load = <$DTB_LOAD_ADDR>;"
|
||||
else
|
||||
DTB_LOAD=""
|
||||
fi
|
||||
|
||||
if [ -z "$*" ]; then
|
||||
DT=arch/arm/dts/${DEVICE_TREE}.dtb
|
||||
else
|
||||
DT=$*
|
||||
fi
|
||||
|
||||
if [ ! -f $BL31 ]; then
|
||||
echo "WARNING: BL31 file $BL31 NOT found, resulting binary is non-functional" >&2
|
||||
BL31=/dev/null
|
||||
# But U-Boot proper could be loaded in EL3 by specifying
|
||||
# firmware = "uboot";
|
||||
# instead of "atf" in config node
|
||||
fi
|
||||
|
||||
cat << __HEADER_EOF
|
||||
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
description = "Configuration to load ATF before U-Boot";
|
||||
|
||||
images {
|
||||
uboot {
|
||||
description = "U-Boot (64-bit)";
|
||||
data = /incbin/("$BL33");
|
||||
type = "firmware";
|
||||
os = "u-boot";
|
||||
arch = "arm64";
|
||||
compression = "none";
|
||||
load = <$BL33_LOAD_ADDR>;
|
||||
entry = <$BL33_LOAD_ADDR>;
|
||||
hash {
|
||||
algo = "md5";
|
||||
};
|
||||
};
|
||||
atf {
|
||||
description = "ARM Trusted Firmware";
|
||||
data = /incbin/("$BL31");
|
||||
type = "firmware";
|
||||
os = "arm-trusted-firmware";
|
||||
arch = "arm64";
|
||||
compression = "none";
|
||||
load = <$ATF_LOAD_ADDR>;
|
||||
entry = <$ATF_LOAD_ADDR>;
|
||||
hash {
|
||||
algo = "md5";
|
||||
};
|
||||
};
|
||||
__HEADER_EOF
|
||||
|
||||
DEFAULT=1
|
||||
cnt=1
|
||||
for dtname in $DT
|
||||
do
|
||||
cat << __FDT_IMAGE_EOF
|
||||
fdt_$cnt {
|
||||
description = "$(basename $dtname .dtb)";
|
||||
data = /incbin/("$dtname");
|
||||
type = "flat_dt";
|
||||
arch = "arm64";
|
||||
compression = "none";
|
||||
$DTB_LOAD
|
||||
hash {
|
||||
algo = "md5";
|
||||
};
|
||||
};
|
||||
__FDT_IMAGE_EOF
|
||||
|
||||
[ "x$(basename $dtname .dtb)" = "x${DEVICE_TREE}" ] && DEFAULT=$cnt
|
||||
|
||||
cnt=$((cnt+1))
|
||||
done
|
||||
|
||||
cat << __CONF_HEADER_EOF
|
||||
};
|
||||
configurations {
|
||||
default = "config_$DEFAULT";
|
||||
|
||||
__CONF_HEADER_EOF
|
||||
|
||||
cnt=1
|
||||
for dtname in $DT
|
||||
do
|
||||
cat << __CONF_SECTION1_EOF
|
||||
config_$cnt {
|
||||
description = "$(basename $dtname .dtb)";
|
||||
firmware = "atf";
|
||||
loadables = "uboot";
|
||||
fdt = "fdt_$cnt";
|
||||
};
|
||||
__CONF_SECTION1_EOF
|
||||
cnt=$((cnt+1))
|
||||
done
|
||||
|
||||
cat << __ITS_EOF
|
||||
};
|
||||
};
|
||||
__ITS_EOF
|
||||
|
|
@ -77,3 +77,12 @@ __weak int psu_init(void)
|
|||
*/
|
||||
return -1;
|
||||
}
|
||||
|
||||
__weak unsigned long psu_post_config_data(void)
|
||||
{
|
||||
/*
|
||||
* This function is overridden by the one in
|
||||
* board/xilinx/zynqmp/(platform)/psu_init_gpl.c, if it exists.
|
||||
*/
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -13,6 +13,7 @@
|
|||
#include <asm/io.h>
|
||||
#include <asm/spl.h>
|
||||
#include <asm/arch/hardware.h>
|
||||
#include <asm/arch/psu_init_gpl.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
|
||||
void board_init_f(ulong dummy)
|
||||
|
|
@ -27,13 +28,6 @@ void board_init_f(ulong dummy)
|
|||
#endif
|
||||
/* Delay is required for clocks to be propagated */
|
||||
udelay(1000000);
|
||||
|
||||
debug("Clearing BSS 0x%p - 0x%p\n", __bss_start, __bss_end);
|
||||
/* Clear the BSS */
|
||||
memset(__bss_start, 0, __bss_end - __bss_start);
|
||||
|
||||
/* No need to call timer init - it is empty for ZynqMP */
|
||||
board_init_r(NULL, 0);
|
||||
}
|
||||
|
||||
static void ps_mode_reset(ulong mode)
|
||||
|
|
@ -60,9 +54,20 @@ void spl_board_init(void)
|
|||
preloader_console_init();
|
||||
ps_mode_reset(MODE_RESET);
|
||||
board_init();
|
||||
psu_post_config_data();
|
||||
}
|
||||
#endif
|
||||
|
||||
void board_boot_order(u32 *spl_boot_list)
|
||||
{
|
||||
spl_boot_list[0] = spl_boot_device();
|
||||
|
||||
if (spl_boot_list[0] == BOOT_DEVICE_MMC1)
|
||||
spl_boot_list[1] = BOOT_DEVICE_MMC2;
|
||||
if (spl_boot_list[0] == BOOT_DEVICE_MMC2)
|
||||
spl_boot_list[1] = BOOT_DEVICE_MMC1;
|
||||
}
|
||||
|
||||
u32 spl_boot_device(void)
|
||||
{
|
||||
u32 reg = 0;
|
||||
|
|
@ -86,11 +91,7 @@ u32 spl_boot_device(void)
|
|||
#ifdef CONFIG_SPL_MMC_SUPPORT
|
||||
case SD_MODE1:
|
||||
case SD1_LSHFT_MODE: /* not working on silicon v1 */
|
||||
/* if both controllers enabled, then these two are the second controller */
|
||||
#ifdef CONFIG_SPL_ZYNQMP_TWO_SDHCI
|
||||
return BOOT_DEVICE_MMC2;
|
||||
/* else, fall through, the one SDHCI controller that is enabled is number 1 */
|
||||
#endif
|
||||
case SD_MODE:
|
||||
case EMMC_MODE:
|
||||
return BOOT_DEVICE_MMC1;
|
||||
|
|
@ -119,8 +120,6 @@ u32 spl_boot_device(void)
|
|||
#ifdef CONFIG_SPL_OS_BOOT
|
||||
int spl_start_uboot(void)
|
||||
{
|
||||
handoff_setup();
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
|
@ -131,6 +130,6 @@ int board_fit_config_name_match(const char *name)
|
|||
/* Just empty function now - can't decide what to choose */
|
||||
debug("%s: %s\n", __func__, name);
|
||||
|
||||
return 0;
|
||||
return -1;
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -220,10 +220,6 @@ unsigned long ps7_peripherals_init_data_3_0[] = {
|
|||
EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U),
|
||||
EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U),
|
||||
EMIT_WRITE(0XF8000004, 0x0000767BU),
|
||||
EMIT_MASKWRITE(0XE0000034, 0x000000FFU, 0x00000006U),
|
||||
EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU, 0x0000007CU),
|
||||
EMIT_MASKWRITE(0XE0000000, 0x000001FFU, 0x00000017U),
|
||||
EMIT_MASKWRITE(0XE0000004, 0x000003FFU, 0x00000020U),
|
||||
EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U),
|
||||
EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U),
|
||||
EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU, 0x00088000U),
|
||||
|
|
|
|||
|
|
@ -173,14 +173,6 @@ static unsigned long ps7_peripherals_init_data_3_0[] = {
|
|||
EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U),
|
||||
EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U),
|
||||
EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
|
||||
EMIT_MASKWRITE(0XE0001034, 0x000000FFU, 0x00000006U),
|
||||
EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU, 0x0000007CU),
|
||||
EMIT_MASKWRITE(0XE0001000, 0x000001FFU, 0x00000017U),
|
||||
EMIT_MASKWRITE(0XE0001004, 0x000003FFU, 0x00000020U),
|
||||
EMIT_MASKWRITE(0XE0000034, 0x000000FFU, 0x00000006U),
|
||||
EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU, 0x0000007CU),
|
||||
EMIT_MASKWRITE(0XE0000000, 0x000001FFU, 0x00000017U),
|
||||
EMIT_MASKWRITE(0XE0000004, 0x000003FFU, 0x00000020U),
|
||||
EMIT_MASKWRITE(0XE000D000, 0x000800FFU, 0x000800C1U),
|
||||
EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U),
|
||||
EMIT_MASKDELAY(0XF8F00200, 1),
|
||||
|
|
|
|||
|
|
@ -173,14 +173,6 @@ static unsigned long ps7_peripherals_init_data_3_0[] = {
|
|||
EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
|
||||
EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
|
||||
EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
|
||||
EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U),
|
||||
EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000007CU),
|
||||
EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U),
|
||||
EMIT_MASKWRITE(0xE0001004, 0x000003FFU, 0x00000020U),
|
||||
EMIT_MASKWRITE(0xE0000034, 0x000000FFU, 0x00000006U),
|
||||
EMIT_MASKWRITE(0xE0000018, 0x0000FFFFU, 0x0000007CU),
|
||||
EMIT_MASKWRITE(0xE0000000, 0x000001FFU, 0x00000017U),
|
||||
EMIT_MASKWRITE(0xE0000004, 0x000003FFU, 0x00000020U),
|
||||
EMIT_MASKWRITE(0xE000D000, 0x000800FFU, 0x000800C1U),
|
||||
EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
|
||||
EMIT_MASKDELAY(0xF8F00200, 1),
|
||||
|
|
|
|||
|
|
@ -171,14 +171,6 @@ static unsigned long ps7_peripherals_init_data_3_0[] = {
|
|||
EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U),
|
||||
EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U),
|
||||
EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
|
||||
EMIT_MASKWRITE(0XE0001034, 0x000000FFU, 0x00000006U),
|
||||
EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU, 0x0000007CU),
|
||||
EMIT_MASKWRITE(0XE0001000, 0x000001FFU, 0x00000017U),
|
||||
EMIT_MASKWRITE(0XE0001004, 0x000003FFU, 0x00000020U),
|
||||
EMIT_MASKWRITE(0XE0000034, 0x000000FFU, 0x00000006U),
|
||||
EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU, 0x0000007CU),
|
||||
EMIT_MASKWRITE(0XE0000000, 0x000001FFU, 0x00000017U),
|
||||
EMIT_MASKWRITE(0XE0000004, 0x000003FFU, 0x00000020U),
|
||||
EMIT_MASKWRITE(0XE000D000, 0x000800FFU, 0x000800C1U),
|
||||
EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U),
|
||||
EMIT_MASKDELAY(0XF8F00200, 1),
|
||||
|
|
|
|||
|
|
@ -44,6 +44,15 @@ config XILINX_OF_BOARD_DTB_ADDR
|
|||
hex
|
||||
default 0x1000 if ARCH_VERSAL
|
||||
default 0x100000 if ARCH_ZYNQ || ARCH_ZYNQMP
|
||||
depends on OF_BOARD
|
||||
depends on OF_BOARD || OF_SEPARATE
|
||||
help
|
||||
Offset in the memory where the board configuration DTB is placed.
|
||||
|
||||
config BOOT_SCRIPT_OFFSET
|
||||
hex "Boot script offset"
|
||||
depends on ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_VERSAL
|
||||
default 0xFC0000 if ARCH_ZYNQ
|
||||
default 0x3E80000 if ARCH_ZYNQMP
|
||||
default 0x7F80000 if ARCH_VERSAL
|
||||
help
|
||||
Specifies distro boot script offset in NAND/NOR flash.
|
||||
|
|
|
|||
|
|
@ -5,6 +5,7 @@
|
|||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/sections.h>
|
||||
#include <dm/uclass.h>
|
||||
#include <i2c.h>
|
||||
|
||||
|
|
@ -37,16 +38,32 @@ int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
|
|||
return ret;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_OF_BOARD)
|
||||
#if defined(CONFIG_OF_BOARD) || defined(CONFIG_OF_SEPARATE)
|
||||
void *board_fdt_blob_setup(void)
|
||||
{
|
||||
static void *fw_dtb = (void *)CONFIG_XILINX_OF_BOARD_DTB_ADDR;
|
||||
static void *fdt_blob = (void *)CONFIG_XILINX_OF_BOARD_DTB_ADDR;
|
||||
|
||||
if (fdt_magic(fw_dtb) != FDT_MAGIC) {
|
||||
printf("DTB is not passed via %p\n", fw_dtb);
|
||||
return NULL;
|
||||
}
|
||||
if (fdt_magic(fdt_blob) == FDT_MAGIC)
|
||||
return fdt_blob;
|
||||
|
||||
return fw_dtb;
|
||||
debug("DTB is not passed via %p\n", fdt_blob);
|
||||
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
/* FDT is at end of BSS unless it is in a different memory region */
|
||||
if (IS_ENABLED(CONFIG_SPL_SEPARATE_BSS))
|
||||
fdt_blob = (ulong *)&_image_binary_end;
|
||||
else
|
||||
fdt_blob = (ulong *)&__bss_end;
|
||||
#else
|
||||
/* FDT is at end of image */
|
||||
fdt_blob = (ulong *)&_end;
|
||||
#endif
|
||||
|
||||
if (fdt_magic(fdt_blob) == FDT_MAGIC)
|
||||
return fdt_blob;
|
||||
|
||||
debug("DTB is also not passed via %p\n", fdt_blob);
|
||||
|
||||
return NULL;
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -130,7 +130,14 @@ int board_late_init(void)
|
|||
break;
|
||||
case EMMC_MODE:
|
||||
puts("EMMC_MODE\n");
|
||||
mode = "mmc0";
|
||||
if (uclass_get_device_by_name(UCLASS_MMC,
|
||||
"sdhci@f1050000", &dev)) {
|
||||
puts("Boot from EMMC but without SD1 enabled!\n");
|
||||
return -1;
|
||||
}
|
||||
debug("mmc1 device found at %p, seq %d\n", dev, dev->seq);
|
||||
mode = "mmc";
|
||||
bootseq = dev->seq;
|
||||
break;
|
||||
case SD_MODE:
|
||||
puts("SD_MODE\n");
|
||||
|
|
@ -196,6 +203,8 @@ int board_late_init(void)
|
|||
initrd_hi = round_down(initrd_hi, SZ_16M);
|
||||
env_set_addr("initrd_high", (void *)initrd_hi);
|
||||
|
||||
env_set_hex("script_offset_f", CONFIG_BOOT_SCRIPT_OFFSET);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -14,7 +14,7 @@ spl/board/xilinx/zynq/ps_init_gpl.o board/xilinx/zynq/ps_init_gpl.o: $(PS_INIT_F
|
|||
endif
|
||||
|
||||
ifeq ($(init-objs),)
|
||||
hw-platform-y :=$(shell echo $(CONFIG_DEFAULT_DEVICE_TREE))
|
||||
hw-platform-y :=$(shell echo $(DEVICE_TREE))
|
||||
init-objs := $(if $(wildcard $(srctree)/$(src)/$(hw-platform-y)/ps7_init_gpl.c),\
|
||||
$(hw-platform-y)/ps7_init_gpl.o)
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -50,7 +50,7 @@ int board_late_init(void)
|
|||
env_set("modeboot", "sdboot");
|
||||
break;
|
||||
case ZYNQ_BM_JTAG:
|
||||
mode = "pxe dhcp";
|
||||
mode = "jtag pxe dhcp";
|
||||
env_set("modeboot", "jtagboot");
|
||||
break;
|
||||
default:
|
||||
|
|
@ -76,6 +76,8 @@ int board_late_init(void)
|
|||
|
||||
env_set("boot_targets", new_targets);
|
||||
|
||||
env_set_hex("script_offset_f", CONFIG_BOOT_SCRIPT_OFFSET);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -227,10 +227,6 @@ static unsigned long ps7_peripherals_init_data_3_0[] = {
|
|||
EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U),
|
||||
EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U),
|
||||
EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
|
||||
EMIT_MASKWRITE(0XE0000034, 0x000000FFU, 0x00000006U),
|
||||
EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU, 0x0000007CU),
|
||||
EMIT_MASKWRITE(0XE0000000, 0x000001FFU, 0x00000017U),
|
||||
EMIT_MASKWRITE(0XE0000004, 0x000003FFU, 0x00000020U),
|
||||
EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U),
|
||||
EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U),
|
||||
EMIT_MASKDELAY(0XF8F00200, 1),
|
||||
|
|
@ -474,10 +470,6 @@ static unsigned long ps7_peripherals_init_data_2_0[] = {
|
|||
EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U),
|
||||
EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U),
|
||||
EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
|
||||
EMIT_MASKWRITE(0XE0000034, 0x000000FFU, 0x00000006U),
|
||||
EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU, 0x0000007CU),
|
||||
EMIT_MASKWRITE(0XE0000000, 0x000001FFU, 0x00000017U),
|
||||
EMIT_MASKWRITE(0XE0000004, 0x00000FFFU, 0x00000020U),
|
||||
EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U),
|
||||
EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U),
|
||||
EMIT_MASKDELAY(0XF8F00200, 1),
|
||||
|
|
@ -714,10 +706,6 @@ static unsigned long ps7_peripherals_init_data_1_0[] = {
|
|||
EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U),
|
||||
EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U),
|
||||
EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
|
||||
EMIT_MASKWRITE(0XE0000034, 0x000000FFU, 0x00000006U),
|
||||
EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU, 0x0000007CU),
|
||||
EMIT_MASKWRITE(0XE0000000, 0x000001FFU, 0x00000017U),
|
||||
EMIT_MASKWRITE(0XE0000004, 0x00000FFFU, 0x00000020U),
|
||||
EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U),
|
||||
EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U),
|
||||
EMIT_MASKDELAY(0XF8F00200, 1),
|
||||
|
|
|
|||
|
|
@ -219,10 +219,6 @@ static unsigned long ps7_peripherals_init_data_3_0[] = {
|
|||
EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
|
||||
EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
|
||||
EMIT_WRITE(0xF8000004, 0x0000767BU),
|
||||
EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U),
|
||||
EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000007CU),
|
||||
EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U),
|
||||
EMIT_MASKWRITE(0xE0001004, 0x000003FFU, 0x00000020U),
|
||||
EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
|
||||
EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
|
||||
EMIT_MASKDELAY(0xF8F00200, 1),
|
||||
|
|
|
|||
|
|
@ -3627,64 +3627,6 @@ unsigned long ps7_peripherals_init_data_3_0[] = {
|
|||
// .. FINISH: LOCK IT BACK
|
||||
// .. START: SRAM/NOR SET OPMODE
|
||||
// .. FINISH: SRAM/NOR SET OPMODE
|
||||
// .. START: UART REGISTERS
|
||||
// .. BDIV = 0x6
|
||||
// .. ==> 0XE0001034[7:0] = 0x00000006U
|
||||
// .. ==> MASK : 0x000000FFU VAL : 0x00000006U
|
||||
// ..
|
||||
EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
|
||||
// .. CD = 0x3e
|
||||
// .. ==> 0XE0001018[15:0] = 0x0000003EU
|
||||
// .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU
|
||||
// ..
|
||||
EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
|
||||
// .. STPBRK = 0x0
|
||||
// .. ==> 0XE0001000[8:8] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000100U VAL : 0x00000000U
|
||||
// .. STTBRK = 0x0
|
||||
// .. ==> 0XE0001000[7:7] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000080U VAL : 0x00000000U
|
||||
// .. RSTTO = 0x0
|
||||
// .. ==> 0XE0001000[6:6] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000040U VAL : 0x00000000U
|
||||
// .. TXDIS = 0x0
|
||||
// .. ==> 0XE0001000[5:5] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000020U VAL : 0x00000000U
|
||||
// .. TXEN = 0x1
|
||||
// .. ==> 0XE0001000[4:4] = 0x00000001U
|
||||
// .. ==> MASK : 0x00000010U VAL : 0x00000010U
|
||||
// .. RXDIS = 0x0
|
||||
// .. ==> 0XE0001000[3:3] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000008U VAL : 0x00000000U
|
||||
// .. RXEN = 0x1
|
||||
// .. ==> 0XE0001000[2:2] = 0x00000001U
|
||||
// .. ==> MASK : 0x00000004U VAL : 0x00000004U
|
||||
// .. TXRES = 0x1
|
||||
// .. ==> 0XE0001000[1:1] = 0x00000001U
|
||||
// .. ==> MASK : 0x00000002U VAL : 0x00000002U
|
||||
// .. RXRES = 0x1
|
||||
// .. ==> 0XE0001000[0:0] = 0x00000001U
|
||||
// .. ==> MASK : 0x00000001U VAL : 0x00000001U
|
||||
// ..
|
||||
EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
|
||||
// .. CHMODE = 0x0
|
||||
// .. ==> 0XE0001004[9:8] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000300U VAL : 0x00000000U
|
||||
// .. NBSTOP = 0x0
|
||||
// .. ==> 0XE0001004[7:6] = 0x00000000U
|
||||
// .. ==> MASK : 0x000000C0U VAL : 0x00000000U
|
||||
// .. PAR = 0x4
|
||||
// .. ==> 0XE0001004[5:3] = 0x00000004U
|
||||
// .. ==> MASK : 0x00000038U VAL : 0x00000020U
|
||||
// .. CHRL = 0x0
|
||||
// .. ==> 0XE0001004[2:1] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000006U VAL : 0x00000000U
|
||||
// .. CLKS = 0x0
|
||||
// .. ==> 0XE0001004[0:0] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
|
||||
// ..
|
||||
EMIT_MASKWRITE(0XE0001004, 0x000003FFU ,0x00000020U),
|
||||
// .. FINISH: UART REGISTERS
|
||||
// .. START: QSPI REGISTERS
|
||||
// .. Holdb_dr = 1
|
||||
// .. ==> 0XE000D000[19:19] = 0x00000001U
|
||||
|
|
@ -7894,70 +7836,6 @@ unsigned long ps7_peripherals_init_data_2_0[] = {
|
|||
// .. FINISH: LOCK IT BACK
|
||||
// .. START: SRAM/NOR SET OPMODE
|
||||
// .. FINISH: SRAM/NOR SET OPMODE
|
||||
// .. START: UART REGISTERS
|
||||
// .. BDIV = 0x6
|
||||
// .. ==> 0XE0001034[7:0] = 0x00000006U
|
||||
// .. ==> MASK : 0x000000FFU VAL : 0x00000006U
|
||||
// ..
|
||||
EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
|
||||
// .. CD = 0x3e
|
||||
// .. ==> 0XE0001018[15:0] = 0x0000003EU
|
||||
// .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU
|
||||
// ..
|
||||
EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
|
||||
// .. STPBRK = 0x0
|
||||
// .. ==> 0XE0001000[8:8] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000100U VAL : 0x00000000U
|
||||
// .. STTBRK = 0x0
|
||||
// .. ==> 0XE0001000[7:7] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000080U VAL : 0x00000000U
|
||||
// .. RSTTO = 0x0
|
||||
// .. ==> 0XE0001000[6:6] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000040U VAL : 0x00000000U
|
||||
// .. TXDIS = 0x0
|
||||
// .. ==> 0XE0001000[5:5] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000020U VAL : 0x00000000U
|
||||
// .. TXEN = 0x1
|
||||
// .. ==> 0XE0001000[4:4] = 0x00000001U
|
||||
// .. ==> MASK : 0x00000010U VAL : 0x00000010U
|
||||
// .. RXDIS = 0x0
|
||||
// .. ==> 0XE0001000[3:3] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000008U VAL : 0x00000000U
|
||||
// .. RXEN = 0x1
|
||||
// .. ==> 0XE0001000[2:2] = 0x00000001U
|
||||
// .. ==> MASK : 0x00000004U VAL : 0x00000004U
|
||||
// .. TXRES = 0x1
|
||||
// .. ==> 0XE0001000[1:1] = 0x00000001U
|
||||
// .. ==> MASK : 0x00000002U VAL : 0x00000002U
|
||||
// .. RXRES = 0x1
|
||||
// .. ==> 0XE0001000[0:0] = 0x00000001U
|
||||
// .. ==> MASK : 0x00000001U VAL : 0x00000001U
|
||||
// ..
|
||||
EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
|
||||
// .. IRMODE = 0x0
|
||||
// .. ==> 0XE0001004[11:11] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000800U VAL : 0x00000000U
|
||||
// .. UCLKEN = 0x0
|
||||
// .. ==> 0XE0001004[10:10] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000400U VAL : 0x00000000U
|
||||
// .. CHMODE = 0x0
|
||||
// .. ==> 0XE0001004[9:8] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000300U VAL : 0x00000000U
|
||||
// .. NBSTOP = 0x0
|
||||
// .. ==> 0XE0001004[7:6] = 0x00000000U
|
||||
// .. ==> MASK : 0x000000C0U VAL : 0x00000000U
|
||||
// .. PAR = 0x4
|
||||
// .. ==> 0XE0001004[5:3] = 0x00000004U
|
||||
// .. ==> MASK : 0x00000038U VAL : 0x00000020U
|
||||
// .. CHRL = 0x0
|
||||
// .. ==> 0XE0001004[2:1] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000006U VAL : 0x00000000U
|
||||
// .. CLKS = 0x0
|
||||
// .. ==> 0XE0001004[0:0] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
|
||||
// ..
|
||||
EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U),
|
||||
// .. FINISH: UART REGISTERS
|
||||
// .. START: QSPI REGISTERS
|
||||
// .. Holdb_dr = 1
|
||||
// .. ==> 0XE000D000[19:19] = 0x00000001U
|
||||
|
|
@ -12094,70 +11972,6 @@ unsigned long ps7_peripherals_init_data_1_0[] = {
|
|||
// .. FINISH: LOCK IT BACK
|
||||
// .. START: SRAM/NOR SET OPMODE
|
||||
// .. FINISH: SRAM/NOR SET OPMODE
|
||||
// .. START: UART REGISTERS
|
||||
// .. BDIV = 0x6
|
||||
// .. ==> 0XE0001034[7:0] = 0x00000006U
|
||||
// .. ==> MASK : 0x000000FFU VAL : 0x00000006U
|
||||
// ..
|
||||
EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
|
||||
// .. CD = 0x3e
|
||||
// .. ==> 0XE0001018[15:0] = 0x0000003EU
|
||||
// .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU
|
||||
// ..
|
||||
EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
|
||||
// .. STPBRK = 0x0
|
||||
// .. ==> 0XE0001000[8:8] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000100U VAL : 0x00000000U
|
||||
// .. STTBRK = 0x0
|
||||
// .. ==> 0XE0001000[7:7] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000080U VAL : 0x00000000U
|
||||
// .. RSTTO = 0x0
|
||||
// .. ==> 0XE0001000[6:6] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000040U VAL : 0x00000000U
|
||||
// .. TXDIS = 0x0
|
||||
// .. ==> 0XE0001000[5:5] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000020U VAL : 0x00000000U
|
||||
// .. TXEN = 0x1
|
||||
// .. ==> 0XE0001000[4:4] = 0x00000001U
|
||||
// .. ==> MASK : 0x00000010U VAL : 0x00000010U
|
||||
// .. RXDIS = 0x0
|
||||
// .. ==> 0XE0001000[3:3] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000008U VAL : 0x00000000U
|
||||
// .. RXEN = 0x1
|
||||
// .. ==> 0XE0001000[2:2] = 0x00000001U
|
||||
// .. ==> MASK : 0x00000004U VAL : 0x00000004U
|
||||
// .. TXRES = 0x1
|
||||
// .. ==> 0XE0001000[1:1] = 0x00000001U
|
||||
// .. ==> MASK : 0x00000002U VAL : 0x00000002U
|
||||
// .. RXRES = 0x1
|
||||
// .. ==> 0XE0001000[0:0] = 0x00000001U
|
||||
// .. ==> MASK : 0x00000001U VAL : 0x00000001U
|
||||
// ..
|
||||
EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
|
||||
// .. IRMODE = 0x0
|
||||
// .. ==> 0XE0001004[11:11] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000800U VAL : 0x00000000U
|
||||
// .. UCLKEN = 0x0
|
||||
// .. ==> 0XE0001004[10:10] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000400U VAL : 0x00000000U
|
||||
// .. CHMODE = 0x0
|
||||
// .. ==> 0XE0001004[9:8] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000300U VAL : 0x00000000U
|
||||
// .. NBSTOP = 0x0
|
||||
// .. ==> 0XE0001004[7:6] = 0x00000000U
|
||||
// .. ==> MASK : 0x000000C0U VAL : 0x00000000U
|
||||
// .. PAR = 0x4
|
||||
// .. ==> 0XE0001004[5:3] = 0x00000004U
|
||||
// .. ==> MASK : 0x00000038U VAL : 0x00000020U
|
||||
// .. CHRL = 0x0
|
||||
// .. ==> 0XE0001004[2:1] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000006U VAL : 0x00000000U
|
||||
// .. CLKS = 0x0
|
||||
// .. ==> 0XE0001004[0:0] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
|
||||
// ..
|
||||
EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U),
|
||||
// .. FINISH: UART REGISTERS
|
||||
// .. START: QSPI REGISTERS
|
||||
// .. Holdb_dr = 1
|
||||
// .. ==> 0XE000D000[19:19] = 0x00000001U
|
||||
|
|
|
|||
|
|
@ -3666,64 +3666,6 @@ unsigned long ps7_peripherals_init_data_3_0[] = {
|
|||
// .. FINISH: LOCK IT BACK
|
||||
// .. START: SRAM/NOR SET OPMODE
|
||||
// .. FINISH: SRAM/NOR SET OPMODE
|
||||
// .. START: UART REGISTERS
|
||||
// .. BDIV = 0x6
|
||||
// .. ==> 0XE0001034[7:0] = 0x00000006U
|
||||
// .. ==> MASK : 0x000000FFU VAL : 0x00000006U
|
||||
// ..
|
||||
EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
|
||||
// .. CD = 0x3e
|
||||
// .. ==> 0XE0001018[15:0] = 0x0000003EU
|
||||
// .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU
|
||||
// ..
|
||||
EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
|
||||
// .. STPBRK = 0x0
|
||||
// .. ==> 0XE0001000[8:8] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000100U VAL : 0x00000000U
|
||||
// .. STTBRK = 0x0
|
||||
// .. ==> 0XE0001000[7:7] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000080U VAL : 0x00000000U
|
||||
// .. RSTTO = 0x0
|
||||
// .. ==> 0XE0001000[6:6] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000040U VAL : 0x00000000U
|
||||
// .. TXDIS = 0x0
|
||||
// .. ==> 0XE0001000[5:5] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000020U VAL : 0x00000000U
|
||||
// .. TXEN = 0x1
|
||||
// .. ==> 0XE0001000[4:4] = 0x00000001U
|
||||
// .. ==> MASK : 0x00000010U VAL : 0x00000010U
|
||||
// .. RXDIS = 0x0
|
||||
// .. ==> 0XE0001000[3:3] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000008U VAL : 0x00000000U
|
||||
// .. RXEN = 0x1
|
||||
// .. ==> 0XE0001000[2:2] = 0x00000001U
|
||||
// .. ==> MASK : 0x00000004U VAL : 0x00000004U
|
||||
// .. TXRES = 0x1
|
||||
// .. ==> 0XE0001000[1:1] = 0x00000001U
|
||||
// .. ==> MASK : 0x00000002U VAL : 0x00000002U
|
||||
// .. RXRES = 0x1
|
||||
// .. ==> 0XE0001000[0:0] = 0x00000001U
|
||||
// .. ==> MASK : 0x00000001U VAL : 0x00000001U
|
||||
// ..
|
||||
EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
|
||||
// .. CHMODE = 0x0
|
||||
// .. ==> 0XE0001004[9:8] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000300U VAL : 0x00000000U
|
||||
// .. NBSTOP = 0x0
|
||||
// .. ==> 0XE0001004[7:6] = 0x00000000U
|
||||
// .. ==> MASK : 0x000000C0U VAL : 0x00000000U
|
||||
// .. PAR = 0x4
|
||||
// .. ==> 0XE0001004[5:3] = 0x00000004U
|
||||
// .. ==> MASK : 0x00000038U VAL : 0x00000020U
|
||||
// .. CHRL = 0x0
|
||||
// .. ==> 0XE0001004[2:1] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000006U VAL : 0x00000000U
|
||||
// .. CLKS = 0x0
|
||||
// .. ==> 0XE0001004[0:0] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
|
||||
// ..
|
||||
EMIT_MASKWRITE(0XE0001004, 0x000003FFU ,0x00000020U),
|
||||
// .. FINISH: UART REGISTERS
|
||||
// .. START: QSPI REGISTERS
|
||||
// .. Holdb_dr = 1
|
||||
// .. ==> 0XE000D000[19:19] = 0x00000001U
|
||||
|
|
@ -8046,70 +7988,6 @@ unsigned long ps7_peripherals_init_data_2_0[] = {
|
|||
// .. FINISH: LOCK IT BACK
|
||||
// .. START: SRAM/NOR SET OPMODE
|
||||
// .. FINISH: SRAM/NOR SET OPMODE
|
||||
// .. START: UART REGISTERS
|
||||
// .. BDIV = 0x6
|
||||
// .. ==> 0XE0001034[7:0] = 0x00000006U
|
||||
// .. ==> MASK : 0x000000FFU VAL : 0x00000006U
|
||||
// ..
|
||||
EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
|
||||
// .. CD = 0x3e
|
||||
// .. ==> 0XE0001018[15:0] = 0x0000003EU
|
||||
// .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU
|
||||
// ..
|
||||
EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
|
||||
// .. STPBRK = 0x0
|
||||
// .. ==> 0XE0001000[8:8] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000100U VAL : 0x00000000U
|
||||
// .. STTBRK = 0x0
|
||||
// .. ==> 0XE0001000[7:7] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000080U VAL : 0x00000000U
|
||||
// .. RSTTO = 0x0
|
||||
// .. ==> 0XE0001000[6:6] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000040U VAL : 0x00000000U
|
||||
// .. TXDIS = 0x0
|
||||
// .. ==> 0XE0001000[5:5] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000020U VAL : 0x00000000U
|
||||
// .. TXEN = 0x1
|
||||
// .. ==> 0XE0001000[4:4] = 0x00000001U
|
||||
// .. ==> MASK : 0x00000010U VAL : 0x00000010U
|
||||
// .. RXDIS = 0x0
|
||||
// .. ==> 0XE0001000[3:3] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000008U VAL : 0x00000000U
|
||||
// .. RXEN = 0x1
|
||||
// .. ==> 0XE0001000[2:2] = 0x00000001U
|
||||
// .. ==> MASK : 0x00000004U VAL : 0x00000004U
|
||||
// .. TXRES = 0x1
|
||||
// .. ==> 0XE0001000[1:1] = 0x00000001U
|
||||
// .. ==> MASK : 0x00000002U VAL : 0x00000002U
|
||||
// .. RXRES = 0x1
|
||||
// .. ==> 0XE0001000[0:0] = 0x00000001U
|
||||
// .. ==> MASK : 0x00000001U VAL : 0x00000001U
|
||||
// ..
|
||||
EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
|
||||
// .. IRMODE = 0x0
|
||||
// .. ==> 0XE0001004[11:11] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000800U VAL : 0x00000000U
|
||||
// .. UCLKEN = 0x0
|
||||
// .. ==> 0XE0001004[10:10] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000400U VAL : 0x00000000U
|
||||
// .. CHMODE = 0x0
|
||||
// .. ==> 0XE0001004[9:8] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000300U VAL : 0x00000000U
|
||||
// .. NBSTOP = 0x0
|
||||
// .. ==> 0XE0001004[7:6] = 0x00000000U
|
||||
// .. ==> MASK : 0x000000C0U VAL : 0x00000000U
|
||||
// .. PAR = 0x4
|
||||
// .. ==> 0XE0001004[5:3] = 0x00000004U
|
||||
// .. ==> MASK : 0x00000038U VAL : 0x00000020U
|
||||
// .. CHRL = 0x0
|
||||
// .. ==> 0XE0001004[2:1] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000006U VAL : 0x00000000U
|
||||
// .. CLKS = 0x0
|
||||
// .. ==> 0XE0001004[0:0] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
|
||||
// ..
|
||||
EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U),
|
||||
// .. FINISH: UART REGISTERS
|
||||
// .. START: QSPI REGISTERS
|
||||
// .. Holdb_dr = 1
|
||||
// .. ==> 0XE000D000[19:19] = 0x00000001U
|
||||
|
|
@ -12359,70 +12237,6 @@ unsigned long ps7_peripherals_init_data_1_0[] = {
|
|||
// .. FINISH: LOCK IT BACK
|
||||
// .. START: SRAM/NOR SET OPMODE
|
||||
// .. FINISH: SRAM/NOR SET OPMODE
|
||||
// .. START: UART REGISTERS
|
||||
// .. BDIV = 0x6
|
||||
// .. ==> 0XE0001034[7:0] = 0x00000006U
|
||||
// .. ==> MASK : 0x000000FFU VAL : 0x00000006U
|
||||
// ..
|
||||
EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
|
||||
// .. CD = 0x3e
|
||||
// .. ==> 0XE0001018[15:0] = 0x0000003EU
|
||||
// .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU
|
||||
// ..
|
||||
EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
|
||||
// .. STPBRK = 0x0
|
||||
// .. ==> 0XE0001000[8:8] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000100U VAL : 0x00000000U
|
||||
// .. STTBRK = 0x0
|
||||
// .. ==> 0XE0001000[7:7] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000080U VAL : 0x00000000U
|
||||
// .. RSTTO = 0x0
|
||||
// .. ==> 0XE0001000[6:6] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000040U VAL : 0x00000000U
|
||||
// .. TXDIS = 0x0
|
||||
// .. ==> 0XE0001000[5:5] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000020U VAL : 0x00000000U
|
||||
// .. TXEN = 0x1
|
||||
// .. ==> 0XE0001000[4:4] = 0x00000001U
|
||||
// .. ==> MASK : 0x00000010U VAL : 0x00000010U
|
||||
// .. RXDIS = 0x0
|
||||
// .. ==> 0XE0001000[3:3] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000008U VAL : 0x00000000U
|
||||
// .. RXEN = 0x1
|
||||
// .. ==> 0XE0001000[2:2] = 0x00000001U
|
||||
// .. ==> MASK : 0x00000004U VAL : 0x00000004U
|
||||
// .. TXRES = 0x1
|
||||
// .. ==> 0XE0001000[1:1] = 0x00000001U
|
||||
// .. ==> MASK : 0x00000002U VAL : 0x00000002U
|
||||
// .. RXRES = 0x1
|
||||
// .. ==> 0XE0001000[0:0] = 0x00000001U
|
||||
// .. ==> MASK : 0x00000001U VAL : 0x00000001U
|
||||
// ..
|
||||
EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
|
||||
// .. IRMODE = 0x0
|
||||
// .. ==> 0XE0001004[11:11] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000800U VAL : 0x00000000U
|
||||
// .. UCLKEN = 0x0
|
||||
// .. ==> 0XE0001004[10:10] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000400U VAL : 0x00000000U
|
||||
// .. CHMODE = 0x0
|
||||
// .. ==> 0XE0001004[9:8] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000300U VAL : 0x00000000U
|
||||
// .. NBSTOP = 0x0
|
||||
// .. ==> 0XE0001004[7:6] = 0x00000000U
|
||||
// .. ==> MASK : 0x000000C0U VAL : 0x00000000U
|
||||
// .. PAR = 0x4
|
||||
// .. ==> 0XE0001004[5:3] = 0x00000004U
|
||||
// .. ==> MASK : 0x00000038U VAL : 0x00000020U
|
||||
// .. CHRL = 0x0
|
||||
// .. ==> 0XE0001004[2:1] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000006U VAL : 0x00000000U
|
||||
// .. CLKS = 0x0
|
||||
// .. ==> 0XE0001004[0:0] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
|
||||
// ..
|
||||
EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U),
|
||||
// .. FINISH: UART REGISTERS
|
||||
// .. START: QSPI REGISTERS
|
||||
// .. Holdb_dr = 1
|
||||
// .. ==> 0XE000D000[19:19] = 0x00000001U
|
||||
|
|
|
|||
|
|
@ -3635,64 +3635,6 @@ unsigned long ps7_peripherals_init_data_3_0[] = {
|
|||
// .. FINISH: LOCK IT BACK
|
||||
// .. START: SRAM/NOR SET OPMODE
|
||||
// .. FINISH: SRAM/NOR SET OPMODE
|
||||
// .. START: UART REGISTERS
|
||||
// .. BDIV = 0x6
|
||||
// .. ==> 0XE0001034[7:0] = 0x00000006U
|
||||
// .. ==> MASK : 0x000000FFU VAL : 0x00000006U
|
||||
// ..
|
||||
EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
|
||||
// .. CD = 0x3e
|
||||
// .. ==> 0XE0001018[15:0] = 0x0000003EU
|
||||
// .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU
|
||||
// ..
|
||||
EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
|
||||
// .. STPBRK = 0x0
|
||||
// .. ==> 0XE0001000[8:8] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000100U VAL : 0x00000000U
|
||||
// .. STTBRK = 0x0
|
||||
// .. ==> 0XE0001000[7:7] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000080U VAL : 0x00000000U
|
||||
// .. RSTTO = 0x0
|
||||
// .. ==> 0XE0001000[6:6] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000040U VAL : 0x00000000U
|
||||
// .. TXDIS = 0x0
|
||||
// .. ==> 0XE0001000[5:5] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000020U VAL : 0x00000000U
|
||||
// .. TXEN = 0x1
|
||||
// .. ==> 0XE0001000[4:4] = 0x00000001U
|
||||
// .. ==> MASK : 0x00000010U VAL : 0x00000010U
|
||||
// .. RXDIS = 0x0
|
||||
// .. ==> 0XE0001000[3:3] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000008U VAL : 0x00000000U
|
||||
// .. RXEN = 0x1
|
||||
// .. ==> 0XE0001000[2:2] = 0x00000001U
|
||||
// .. ==> MASK : 0x00000004U VAL : 0x00000004U
|
||||
// .. TXRES = 0x1
|
||||
// .. ==> 0XE0001000[1:1] = 0x00000001U
|
||||
// .. ==> MASK : 0x00000002U VAL : 0x00000002U
|
||||
// .. RXRES = 0x1
|
||||
// .. ==> 0XE0001000[0:0] = 0x00000001U
|
||||
// .. ==> MASK : 0x00000001U VAL : 0x00000001U
|
||||
// ..
|
||||
EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
|
||||
// .. CHMODE = 0x0
|
||||
// .. ==> 0XE0001004[9:8] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000300U VAL : 0x00000000U
|
||||
// .. NBSTOP = 0x0
|
||||
// .. ==> 0XE0001004[7:6] = 0x00000000U
|
||||
// .. ==> MASK : 0x000000C0U VAL : 0x00000000U
|
||||
// .. PAR = 0x4
|
||||
// .. ==> 0XE0001004[5:3] = 0x00000004U
|
||||
// .. ==> MASK : 0x00000038U VAL : 0x00000020U
|
||||
// .. CHRL = 0x0
|
||||
// .. ==> 0XE0001004[2:1] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000006U VAL : 0x00000000U
|
||||
// .. CLKS = 0x0
|
||||
// .. ==> 0XE0001004[0:0] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
|
||||
// ..
|
||||
EMIT_MASKWRITE(0XE0001004, 0x000003FFU ,0x00000020U),
|
||||
// .. FINISH: UART REGISTERS
|
||||
// .. START: QSPI REGISTERS
|
||||
// .. Holdb_dr = 1
|
||||
// .. ==> 0XE000D000[19:19] = 0x00000001U
|
||||
|
|
@ -7984,70 +7926,6 @@ unsigned long ps7_peripherals_init_data_2_0[] = {
|
|||
// .. FINISH: LOCK IT BACK
|
||||
// .. START: SRAM/NOR SET OPMODE
|
||||
// .. FINISH: SRAM/NOR SET OPMODE
|
||||
// .. START: UART REGISTERS
|
||||
// .. BDIV = 0x6
|
||||
// .. ==> 0XE0001034[7:0] = 0x00000006U
|
||||
// .. ==> MASK : 0x000000FFU VAL : 0x00000006U
|
||||
// ..
|
||||
EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
|
||||
// .. CD = 0x3e
|
||||
// .. ==> 0XE0001018[15:0] = 0x0000003EU
|
||||
// .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU
|
||||
// ..
|
||||
EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
|
||||
// .. STPBRK = 0x0
|
||||
// .. ==> 0XE0001000[8:8] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000100U VAL : 0x00000000U
|
||||
// .. STTBRK = 0x0
|
||||
// .. ==> 0XE0001000[7:7] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000080U VAL : 0x00000000U
|
||||
// .. RSTTO = 0x0
|
||||
// .. ==> 0XE0001000[6:6] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000040U VAL : 0x00000000U
|
||||
// .. TXDIS = 0x0
|
||||
// .. ==> 0XE0001000[5:5] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000020U VAL : 0x00000000U
|
||||
// .. TXEN = 0x1
|
||||
// .. ==> 0XE0001000[4:4] = 0x00000001U
|
||||
// .. ==> MASK : 0x00000010U VAL : 0x00000010U
|
||||
// .. RXDIS = 0x0
|
||||
// .. ==> 0XE0001000[3:3] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000008U VAL : 0x00000000U
|
||||
// .. RXEN = 0x1
|
||||
// .. ==> 0XE0001000[2:2] = 0x00000001U
|
||||
// .. ==> MASK : 0x00000004U VAL : 0x00000004U
|
||||
// .. TXRES = 0x1
|
||||
// .. ==> 0XE0001000[1:1] = 0x00000001U
|
||||
// .. ==> MASK : 0x00000002U VAL : 0x00000002U
|
||||
// .. RXRES = 0x1
|
||||
// .. ==> 0XE0001000[0:0] = 0x00000001U
|
||||
// .. ==> MASK : 0x00000001U VAL : 0x00000001U
|
||||
// ..
|
||||
EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
|
||||
// .. IRMODE = 0x0
|
||||
// .. ==> 0XE0001004[11:11] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000800U VAL : 0x00000000U
|
||||
// .. UCLKEN = 0x0
|
||||
// .. ==> 0XE0001004[10:10] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000400U VAL : 0x00000000U
|
||||
// .. CHMODE = 0x0
|
||||
// .. ==> 0XE0001004[9:8] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000300U VAL : 0x00000000U
|
||||
// .. NBSTOP = 0x0
|
||||
// .. ==> 0XE0001004[7:6] = 0x00000000U
|
||||
// .. ==> MASK : 0x000000C0U VAL : 0x00000000U
|
||||
// .. PAR = 0x4
|
||||
// .. ==> 0XE0001004[5:3] = 0x00000004U
|
||||
// .. ==> MASK : 0x00000038U VAL : 0x00000020U
|
||||
// .. CHRL = 0x0
|
||||
// .. ==> 0XE0001004[2:1] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000006U VAL : 0x00000000U
|
||||
// .. CLKS = 0x0
|
||||
// .. ==> 0XE0001004[0:0] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
|
||||
// ..
|
||||
EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U),
|
||||
// .. FINISH: UART REGISTERS
|
||||
// .. START: QSPI REGISTERS
|
||||
// .. Holdb_dr = 1
|
||||
// .. ==> 0XE000D000[19:19] = 0x00000001U
|
||||
|
|
@ -12266,70 +12144,6 @@ unsigned long ps7_peripherals_init_data_1_0[] = {
|
|||
// .. FINISH: LOCK IT BACK
|
||||
// .. START: SRAM/NOR SET OPMODE
|
||||
// .. FINISH: SRAM/NOR SET OPMODE
|
||||
// .. START: UART REGISTERS
|
||||
// .. BDIV = 0x6
|
||||
// .. ==> 0XE0001034[7:0] = 0x00000006U
|
||||
// .. ==> MASK : 0x000000FFU VAL : 0x00000006U
|
||||
// ..
|
||||
EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
|
||||
// .. CD = 0x3e
|
||||
// .. ==> 0XE0001018[15:0] = 0x0000003EU
|
||||
// .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU
|
||||
// ..
|
||||
EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
|
||||
// .. STPBRK = 0x0
|
||||
// .. ==> 0XE0001000[8:8] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000100U VAL : 0x00000000U
|
||||
// .. STTBRK = 0x0
|
||||
// .. ==> 0XE0001000[7:7] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000080U VAL : 0x00000000U
|
||||
// .. RSTTO = 0x0
|
||||
// .. ==> 0XE0001000[6:6] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000040U VAL : 0x00000000U
|
||||
// .. TXDIS = 0x0
|
||||
// .. ==> 0XE0001000[5:5] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000020U VAL : 0x00000000U
|
||||
// .. TXEN = 0x1
|
||||
// .. ==> 0XE0001000[4:4] = 0x00000001U
|
||||
// .. ==> MASK : 0x00000010U VAL : 0x00000010U
|
||||
// .. RXDIS = 0x0
|
||||
// .. ==> 0XE0001000[3:3] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000008U VAL : 0x00000000U
|
||||
// .. RXEN = 0x1
|
||||
// .. ==> 0XE0001000[2:2] = 0x00000001U
|
||||
// .. ==> MASK : 0x00000004U VAL : 0x00000004U
|
||||
// .. TXRES = 0x1
|
||||
// .. ==> 0XE0001000[1:1] = 0x00000001U
|
||||
// .. ==> MASK : 0x00000002U VAL : 0x00000002U
|
||||
// .. RXRES = 0x1
|
||||
// .. ==> 0XE0001000[0:0] = 0x00000001U
|
||||
// .. ==> MASK : 0x00000001U VAL : 0x00000001U
|
||||
// ..
|
||||
EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
|
||||
// .. IRMODE = 0x0
|
||||
// .. ==> 0XE0001004[11:11] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000800U VAL : 0x00000000U
|
||||
// .. UCLKEN = 0x0
|
||||
// .. ==> 0XE0001004[10:10] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000400U VAL : 0x00000000U
|
||||
// .. CHMODE = 0x0
|
||||
// .. ==> 0XE0001004[9:8] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000300U VAL : 0x00000000U
|
||||
// .. NBSTOP = 0x0
|
||||
// .. ==> 0XE0001004[7:6] = 0x00000000U
|
||||
// .. ==> MASK : 0x000000C0U VAL : 0x00000000U
|
||||
// .. PAR = 0x4
|
||||
// .. ==> 0XE0001004[5:3] = 0x00000004U
|
||||
// .. ==> MASK : 0x00000038U VAL : 0x00000020U
|
||||
// .. CHRL = 0x0
|
||||
// .. ==> 0XE0001004[2:1] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000006U VAL : 0x00000000U
|
||||
// .. CLKS = 0x0
|
||||
// .. ==> 0XE0001004[0:0] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
|
||||
// ..
|
||||
EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U),
|
||||
// .. FINISH: UART REGISTERS
|
||||
// .. START: QSPI REGISTERS
|
||||
// .. Holdb_dr = 1
|
||||
// .. ==> 0XE000D000[19:19] = 0x00000001U
|
||||
|
|
|
|||
|
|
@ -221,10 +221,6 @@ static unsigned long ps7_peripherals_init_data_3_0[] = {
|
|||
EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
|
||||
EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
|
||||
EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
|
||||
EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U),
|
||||
EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000003EU),
|
||||
EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U),
|
||||
EMIT_MASKWRITE(0xE0001004, 0x000003FFU, 0x00000020U),
|
||||
EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
|
||||
EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
|
||||
EMIT_MASKDELAY(0xF8F00200, 1),
|
||||
|
|
@ -461,10 +457,6 @@ static unsigned long ps7_peripherals_init_data_2_0[] = {
|
|||
EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
|
||||
EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
|
||||
EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
|
||||
EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U),
|
||||
EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000003EU),
|
||||
EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U),
|
||||
EMIT_MASKWRITE(0xE0001004, 0x00000FFFU, 0x00000020U),
|
||||
EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
|
||||
EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
|
||||
EMIT_MASKDELAY(0xF8F00200, 1),
|
||||
|
|
@ -699,10 +691,6 @@ static unsigned long ps7_peripherals_init_data_1_0[] = {
|
|||
EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
|
||||
EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
|
||||
EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
|
||||
EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U),
|
||||
EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000003EU),
|
||||
EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U),
|
||||
EMIT_MASKWRITE(0xE0001004, 0x00000FFFU, 0x00000020U),
|
||||
EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
|
||||
EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
|
||||
EMIT_MASKDELAY(0xF8F00200, 1),
|
||||
|
|
|
|||
|
|
@ -212,10 +212,6 @@ static unsigned long ps7_peripherals_init_data_3_0[] = {
|
|||
EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
|
||||
EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
|
||||
EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
|
||||
EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U),
|
||||
EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000003EU),
|
||||
EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U),
|
||||
EMIT_MASKWRITE(0xE0001004, 0x000003FFU, 0x00000020U),
|
||||
EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
|
||||
EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
|
||||
EMIT_MASKWRITE(0xE000E014, 0x00FFFFFFU, 0x00245A55U),
|
||||
|
|
@ -446,10 +442,6 @@ static unsigned long ps7_peripherals_init_data_2_0[] = {
|
|||
EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
|
||||
EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
|
||||
EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
|
||||
EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U),
|
||||
EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000003EU),
|
||||
EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U),
|
||||
EMIT_MASKWRITE(0xE0001004, 0x00000FFFU, 0x00000020U),
|
||||
EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
|
||||
EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
|
||||
EMIT_MASKWRITE(0xE000E014, 0x00FFFFFFU, 0x00245A55U),
|
||||
|
|
@ -678,10 +670,6 @@ static unsigned long ps7_peripherals_init_data_1_0[] = {
|
|||
EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
|
||||
EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
|
||||
EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
|
||||
EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U),
|
||||
EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000003EU),
|
||||
EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U),
|
||||
EMIT_MASKWRITE(0xE0001004, 0x00000FFFU, 0x00000020U),
|
||||
EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
|
||||
EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
|
||||
EMIT_MASKWRITE(0xE000E014, 0x00FFFFFFU, 0x00245A55U),
|
||||
|
|
|
|||
|
|
@ -210,10 +210,6 @@ static unsigned long ps7_peripherals_init_data_3_0[] = {
|
|||
EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
|
||||
EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
|
||||
EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
|
||||
EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U),
|
||||
EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000003EU),
|
||||
EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U),
|
||||
EMIT_MASKWRITE(0xE0001004, 0x000003FFU, 0x00000020U),
|
||||
EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
|
||||
EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
|
||||
EMIT_MASKWRITE(0xE000E014, 0x00FFFFFFU, 0x00245A55U),
|
||||
|
|
@ -442,10 +438,6 @@ static unsigned long ps7_peripherals_init_data_2_0[] = {
|
|||
EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
|
||||
EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
|
||||
EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
|
||||
EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U),
|
||||
EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000003EU),
|
||||
EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U),
|
||||
EMIT_MASKWRITE(0xE0001004, 0x00000FFFU, 0x00000020U),
|
||||
EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
|
||||
EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
|
||||
EMIT_MASKWRITE(0xE000E014, 0x00FFFFFFU, 0x00245A55U),
|
||||
|
|
@ -672,10 +664,6 @@ static unsigned long ps7_peripherals_init_data_1_0[] = {
|
|||
EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
|
||||
EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
|
||||
EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
|
||||
EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U),
|
||||
EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000003EU),
|
||||
EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U),
|
||||
EMIT_MASKWRITE(0xE0001004, 0x00000FFFU, 0x00000020U),
|
||||
EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
|
||||
EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
|
||||
EMIT_MASKWRITE(0xE000E014, 0x00FFFFFFU, 0x00245A55U),
|
||||
|
|
|
|||
|
|
@ -221,10 +221,6 @@ static unsigned long ps7_peripherals_init_data_3_0[] = {
|
|||
EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
|
||||
EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
|
||||
EMIT_MASKWRITE(0xE000E018, 0x00001000U, 0x00001000U),
|
||||
EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U),
|
||||
EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000003EU),
|
||||
EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U),
|
||||
EMIT_MASKWRITE(0xE0001004, 0x000003FFU, 0x00000020U),
|
||||
EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
|
||||
EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
|
||||
EMIT_MASKWRITE(0xE000E014, 0x00FFFFFFU, 0x00049BAAU),
|
||||
|
|
@ -467,10 +463,6 @@ static unsigned long ps7_peripherals_init_data_2_0[] = {
|
|||
EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
|
||||
EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
|
||||
EMIT_MASKWRITE(0xE000E018, 0x00001000U, 0x00001000U),
|
||||
EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U),
|
||||
EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000003EU),
|
||||
EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U),
|
||||
EMIT_MASKWRITE(0xE0001004, 0x00000FFFU, 0x00000020U),
|
||||
EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
|
||||
EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
|
||||
EMIT_MASKWRITE(0xE000E014, 0x00FFFFFFU, 0x00049BAAU),
|
||||
|
|
@ -711,10 +703,6 @@ static unsigned long ps7_peripherals_init_data_1_0[] = {
|
|||
EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
|
||||
EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
|
||||
EMIT_MASKWRITE(0xE000E018, 0x00001000U, 0x00001000U),
|
||||
EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U),
|
||||
EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000003EU),
|
||||
EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U),
|
||||
EMIT_MASKWRITE(0xE0001004, 0x00000FFFU, 0x00000020U),
|
||||
EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
|
||||
EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
|
||||
EMIT_MASKWRITE(0xE000E014, 0x00FFFFFFU, 0x00049BAAU),
|
||||
|
|
|
|||
|
|
@ -210,10 +210,6 @@ static unsigned long ps7_peripherals_init_data_3_0[] = {
|
|||
EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
|
||||
EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
|
||||
EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
|
||||
EMIT_MASKWRITE(0xE0000034, 0x000000FFU, 0x00000006U),
|
||||
EMIT_MASKWRITE(0xE0000018, 0x0000FFFFU, 0x0000003EU),
|
||||
EMIT_MASKWRITE(0xE0000000, 0x000001FFU, 0x00000017U),
|
||||
EMIT_MASKWRITE(0xE0000004, 0x000003FFU, 0x00000020U),
|
||||
EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
|
||||
EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
|
||||
EMIT_MASKDELAY(0xF8F00200, 1),
|
||||
|
|
@ -439,10 +435,6 @@ static unsigned long ps7_peripherals_init_data_2_0[] = {
|
|||
EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
|
||||
EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
|
||||
EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
|
||||
EMIT_MASKWRITE(0xE0000034, 0x000000FFU, 0x00000006U),
|
||||
EMIT_MASKWRITE(0xE0000018, 0x0000FFFFU, 0x0000003EU),
|
||||
EMIT_MASKWRITE(0xE0000000, 0x000001FFU, 0x00000017U),
|
||||
EMIT_MASKWRITE(0xE0000004, 0x00000FFFU, 0x00000020U),
|
||||
EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
|
||||
EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
|
||||
EMIT_MASKDELAY(0xF8F00200, 1),
|
||||
|
|
@ -666,10 +658,6 @@ static unsigned long ps7_peripherals_init_data_1_0[] = {
|
|||
EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
|
||||
EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
|
||||
EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
|
||||
EMIT_MASKWRITE(0xE0000034, 0x000000FFU, 0x00000006U),
|
||||
EMIT_MASKWRITE(0xE0000018, 0x0000FFFFU, 0x0000003EU),
|
||||
EMIT_MASKWRITE(0xE0000000, 0x000001FFU, 0x00000017U),
|
||||
EMIT_MASKWRITE(0xE0000004, 0x00000FFFU, 0x00000020U),
|
||||
EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
|
||||
EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
|
||||
EMIT_MASKDELAY(0xF8F00200, 1),
|
||||
|
|
|
|||
|
|
@ -3627,64 +3627,6 @@ unsigned long ps7_peripherals_init_data_3_0[] = {
|
|||
// .. FINISH: LOCK IT BACK
|
||||
// .. START: SRAM/NOR SET OPMODE
|
||||
// .. FINISH: SRAM/NOR SET OPMODE
|
||||
// .. START: UART REGISTERS
|
||||
// .. BDIV = 0x6
|
||||
// .. ==> 0XE0001034[7:0] = 0x00000006U
|
||||
// .. ==> MASK : 0x000000FFU VAL : 0x00000006U
|
||||
// ..
|
||||
EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
|
||||
// .. CD = 0x3e
|
||||
// .. ==> 0XE0001018[15:0] = 0x0000003EU
|
||||
// .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU
|
||||
// ..
|
||||
EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
|
||||
// .. STPBRK = 0x0
|
||||
// .. ==> 0XE0001000[8:8] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000100U VAL : 0x00000000U
|
||||
// .. STTBRK = 0x0
|
||||
// .. ==> 0XE0001000[7:7] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000080U VAL : 0x00000000U
|
||||
// .. RSTTO = 0x0
|
||||
// .. ==> 0XE0001000[6:6] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000040U VAL : 0x00000000U
|
||||
// .. TXDIS = 0x0
|
||||
// .. ==> 0XE0001000[5:5] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000020U VAL : 0x00000000U
|
||||
// .. TXEN = 0x1
|
||||
// .. ==> 0XE0001000[4:4] = 0x00000001U
|
||||
// .. ==> MASK : 0x00000010U VAL : 0x00000010U
|
||||
// .. RXDIS = 0x0
|
||||
// .. ==> 0XE0001000[3:3] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000008U VAL : 0x00000000U
|
||||
// .. RXEN = 0x1
|
||||
// .. ==> 0XE0001000[2:2] = 0x00000001U
|
||||
// .. ==> MASK : 0x00000004U VAL : 0x00000004U
|
||||
// .. TXRES = 0x1
|
||||
// .. ==> 0XE0001000[1:1] = 0x00000001U
|
||||
// .. ==> MASK : 0x00000002U VAL : 0x00000002U
|
||||
// .. RXRES = 0x1
|
||||
// .. ==> 0XE0001000[0:0] = 0x00000001U
|
||||
// .. ==> MASK : 0x00000001U VAL : 0x00000001U
|
||||
// ..
|
||||
EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
|
||||
// .. CHMODE = 0x0
|
||||
// .. ==> 0XE0001004[9:8] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000300U VAL : 0x00000000U
|
||||
// .. NBSTOP = 0x0
|
||||
// .. ==> 0XE0001004[7:6] = 0x00000000U
|
||||
// .. ==> MASK : 0x000000C0U VAL : 0x00000000U
|
||||
// .. PAR = 0x4
|
||||
// .. ==> 0XE0001004[5:3] = 0x00000004U
|
||||
// .. ==> MASK : 0x00000038U VAL : 0x00000020U
|
||||
// .. CHRL = 0x0
|
||||
// .. ==> 0XE0001004[2:1] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000006U VAL : 0x00000000U
|
||||
// .. CLKS = 0x0
|
||||
// .. ==> 0XE0001004[0:0] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
|
||||
// ..
|
||||
EMIT_MASKWRITE(0XE0001004, 0x000003FFU ,0x00000020U),
|
||||
// .. FINISH: UART REGISTERS
|
||||
// .. START: QSPI REGISTERS
|
||||
// .. Holdb_dr = 1
|
||||
// .. ==> 0XE000D000[19:19] = 0x00000001U
|
||||
|
|
@ -7860,70 +7802,6 @@ unsigned long ps7_peripherals_init_data_2_0[] = {
|
|||
// .. FINISH: LOCK IT BACK
|
||||
// .. START: SRAM/NOR SET OPMODE
|
||||
// .. FINISH: SRAM/NOR SET OPMODE
|
||||
// .. START: UART REGISTERS
|
||||
// .. BDIV = 0x6
|
||||
// .. ==> 0XE0001034[7:0] = 0x00000006U
|
||||
// .. ==> MASK : 0x000000FFU VAL : 0x00000006U
|
||||
// ..
|
||||
EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
|
||||
// .. CD = 0x3e
|
||||
// .. ==> 0XE0001018[15:0] = 0x0000003EU
|
||||
// .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU
|
||||
// ..
|
||||
EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
|
||||
// .. STPBRK = 0x0
|
||||
// .. ==> 0XE0001000[8:8] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000100U VAL : 0x00000000U
|
||||
// .. STTBRK = 0x0
|
||||
// .. ==> 0XE0001000[7:7] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000080U VAL : 0x00000000U
|
||||
// .. RSTTO = 0x0
|
||||
// .. ==> 0XE0001000[6:6] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000040U VAL : 0x00000000U
|
||||
// .. TXDIS = 0x0
|
||||
// .. ==> 0XE0001000[5:5] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000020U VAL : 0x00000000U
|
||||
// .. TXEN = 0x1
|
||||
// .. ==> 0XE0001000[4:4] = 0x00000001U
|
||||
// .. ==> MASK : 0x00000010U VAL : 0x00000010U
|
||||
// .. RXDIS = 0x0
|
||||
// .. ==> 0XE0001000[3:3] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000008U VAL : 0x00000000U
|
||||
// .. RXEN = 0x1
|
||||
// .. ==> 0XE0001000[2:2] = 0x00000001U
|
||||
// .. ==> MASK : 0x00000004U VAL : 0x00000004U
|
||||
// .. TXRES = 0x1
|
||||
// .. ==> 0XE0001000[1:1] = 0x00000001U
|
||||
// .. ==> MASK : 0x00000002U VAL : 0x00000002U
|
||||
// .. RXRES = 0x1
|
||||
// .. ==> 0XE0001000[0:0] = 0x00000001U
|
||||
// .. ==> MASK : 0x00000001U VAL : 0x00000001U
|
||||
// ..
|
||||
EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
|
||||
// .. IRMODE = 0x0
|
||||
// .. ==> 0XE0001004[11:11] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000800U VAL : 0x00000000U
|
||||
// .. UCLKEN = 0x0
|
||||
// .. ==> 0XE0001004[10:10] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000400U VAL : 0x00000000U
|
||||
// .. CHMODE = 0x0
|
||||
// .. ==> 0XE0001004[9:8] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000300U VAL : 0x00000000U
|
||||
// .. NBSTOP = 0x0
|
||||
// .. ==> 0XE0001004[7:6] = 0x00000000U
|
||||
// .. ==> MASK : 0x000000C0U VAL : 0x00000000U
|
||||
// .. PAR = 0x4
|
||||
// .. ==> 0XE0001004[5:3] = 0x00000004U
|
||||
// .. ==> MASK : 0x00000038U VAL : 0x00000020U
|
||||
// .. CHRL = 0x0
|
||||
// .. ==> 0XE0001004[2:1] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000006U VAL : 0x00000000U
|
||||
// .. CLKS = 0x0
|
||||
// .. ==> 0XE0001004[0:0] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
|
||||
// ..
|
||||
EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U),
|
||||
// .. FINISH: UART REGISTERS
|
||||
// .. START: QSPI REGISTERS
|
||||
// .. Holdb_dr = 1
|
||||
// .. ==> 0XE000D000[19:19] = 0x00000001U
|
||||
|
|
@ -12026,70 +11904,6 @@ unsigned long ps7_peripherals_init_data_1_0[] = {
|
|||
// .. FINISH: LOCK IT BACK
|
||||
// .. START: SRAM/NOR SET OPMODE
|
||||
// .. FINISH: SRAM/NOR SET OPMODE
|
||||
// .. START: UART REGISTERS
|
||||
// .. BDIV = 0x6
|
||||
// .. ==> 0XE0001034[7:0] = 0x00000006U
|
||||
// .. ==> MASK : 0x000000FFU VAL : 0x00000006U
|
||||
// ..
|
||||
EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
|
||||
// .. CD = 0x3e
|
||||
// .. ==> 0XE0001018[15:0] = 0x0000003EU
|
||||
// .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU
|
||||
// ..
|
||||
EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
|
||||
// .. STPBRK = 0x0
|
||||
// .. ==> 0XE0001000[8:8] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000100U VAL : 0x00000000U
|
||||
// .. STTBRK = 0x0
|
||||
// .. ==> 0XE0001000[7:7] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000080U VAL : 0x00000000U
|
||||
// .. RSTTO = 0x0
|
||||
// .. ==> 0XE0001000[6:6] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000040U VAL : 0x00000000U
|
||||
// .. TXDIS = 0x0
|
||||
// .. ==> 0XE0001000[5:5] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000020U VAL : 0x00000000U
|
||||
// .. TXEN = 0x1
|
||||
// .. ==> 0XE0001000[4:4] = 0x00000001U
|
||||
// .. ==> MASK : 0x00000010U VAL : 0x00000010U
|
||||
// .. RXDIS = 0x0
|
||||
// .. ==> 0XE0001000[3:3] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000008U VAL : 0x00000000U
|
||||
// .. RXEN = 0x1
|
||||
// .. ==> 0XE0001000[2:2] = 0x00000001U
|
||||
// .. ==> MASK : 0x00000004U VAL : 0x00000004U
|
||||
// .. TXRES = 0x1
|
||||
// .. ==> 0XE0001000[1:1] = 0x00000001U
|
||||
// .. ==> MASK : 0x00000002U VAL : 0x00000002U
|
||||
// .. RXRES = 0x1
|
||||
// .. ==> 0XE0001000[0:0] = 0x00000001U
|
||||
// .. ==> MASK : 0x00000001U VAL : 0x00000001U
|
||||
// ..
|
||||
EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
|
||||
// .. IRMODE = 0x0
|
||||
// .. ==> 0XE0001004[11:11] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000800U VAL : 0x00000000U
|
||||
// .. UCLKEN = 0x0
|
||||
// .. ==> 0XE0001004[10:10] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000400U VAL : 0x00000000U
|
||||
// .. CHMODE = 0x0
|
||||
// .. ==> 0XE0001004[9:8] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000300U VAL : 0x00000000U
|
||||
// .. NBSTOP = 0x0
|
||||
// .. ==> 0XE0001004[7:6] = 0x00000000U
|
||||
// .. ==> MASK : 0x000000C0U VAL : 0x00000000U
|
||||
// .. PAR = 0x4
|
||||
// .. ==> 0XE0001004[5:3] = 0x00000004U
|
||||
// .. ==> MASK : 0x00000038U VAL : 0x00000020U
|
||||
// .. CHRL = 0x0
|
||||
// .. ==> 0XE0001004[2:1] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000006U VAL : 0x00000000U
|
||||
// .. CLKS = 0x0
|
||||
// .. ==> 0XE0001004[0:0] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
|
||||
// ..
|
||||
EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U),
|
||||
// .. FINISH: UART REGISTERS
|
||||
// .. START: QSPI REGISTERS
|
||||
// .. Holdb_dr = 1
|
||||
// .. ==> 0XE000D000[19:19] = 0x00000001U
|
||||
|
|
|
|||
|
|
@ -222,14 +222,6 @@ static unsigned long ps7_peripherals_init_data[] = {
|
|||
EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
|
||||
EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
|
||||
EMIT_WRITE(0xF8000004, 0x0000767BU),
|
||||
EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U),
|
||||
EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000007CU),
|
||||
EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U),
|
||||
EMIT_MASKWRITE(0xE0001004, 0x000003FFU, 0x00000020U),
|
||||
EMIT_MASKWRITE(0xE0000034, 0x000000FFU, 0x00000006U),
|
||||
EMIT_MASKWRITE(0xE0000018, 0x0000FFFFU, 0x0000007CU),
|
||||
EMIT_MASKWRITE(0xE0000000, 0x000001FFU, 0x00000017U),
|
||||
EMIT_MASKWRITE(0xE0000004, 0x000003FFU, 0x00000020U),
|
||||
EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
|
||||
EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
|
||||
EMIT_MASKWRITE(0xE000A244, 0x003FFFFFU, 0x00080000U),
|
||||
|
|
|
|||
|
|
@ -235,10 +235,6 @@ static unsigned long ps7_peripherals_init_data_3_0[] = {
|
|||
EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
|
||||
EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
|
||||
EMIT_WRITE(0xF8000004, 0x0000767BU),
|
||||
EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U),
|
||||
EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000007CU),
|
||||
EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U),
|
||||
EMIT_MASKWRITE(0xE0001004, 0x000003FFU, 0x00000020U),
|
||||
EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
|
||||
EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
|
||||
EMIT_MASKWRITE(0xE000A244, 0x003FFFFFU, 0x00004000U),
|
||||
|
|
|
|||
|
|
@ -3647,64 +3647,6 @@ unsigned long ps7_peripherals_init_data_3_0[] = {
|
|||
/* .. FINISH: LOCK IT BACK */
|
||||
/* .. START: SRAM/NOR SET OPMODE */
|
||||
/* .. FINISH: SRAM/NOR SET OPMODE */
|
||||
/* .. START: UART REGISTERS */
|
||||
/* .. BDIV = 0x6 */
|
||||
/* .. ==> 0XE0001034[7:0] = 0x00000006U */
|
||||
/* .. ==> MASK : 0x000000FFU VAL : 0x00000006U */
|
||||
/* .. */
|
||||
EMIT_MASKWRITE(0XE0001034, 0x000000FFU, 0x00000006U),
|
||||
/* .. CD = 0x7c */
|
||||
/* .. ==> 0XE0001018[15:0] = 0x0000007CU */
|
||||
/* .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU */
|
||||
/* .. */
|
||||
EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU, 0x0000007CU),
|
||||
/* .. STPBRK = 0x0 */
|
||||
/* .. ==> 0XE0001000[8:8] = 0x00000000U */
|
||||
/* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
|
||||
/* .. STTBRK = 0x0 */
|
||||
/* .. ==> 0XE0001000[7:7] = 0x00000000U */
|
||||
/* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
|
||||
/* .. RSTTO = 0x0 */
|
||||
/* .. ==> 0XE0001000[6:6] = 0x00000000U */
|
||||
/* .. ==> MASK : 0x00000040U VAL : 0x00000000U */
|
||||
/* .. TXDIS = 0x0 */
|
||||
/* .. ==> 0XE0001000[5:5] = 0x00000000U */
|
||||
/* .. ==> MASK : 0x00000020U VAL : 0x00000000U */
|
||||
/* .. TXEN = 0x1 */
|
||||
/* .. ==> 0XE0001000[4:4] = 0x00000001U */
|
||||
/* .. ==> MASK : 0x00000010U VAL : 0x00000010U */
|
||||
/* .. RXDIS = 0x0 */
|
||||
/* .. ==> 0XE0001000[3:3] = 0x00000000U */
|
||||
/* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
|
||||
/* .. RXEN = 0x1 */
|
||||
/* .. ==> 0XE0001000[2:2] = 0x00000001U */
|
||||
/* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
|
||||
/* .. TXRES = 0x1 */
|
||||
/* .. ==> 0XE0001000[1:1] = 0x00000001U */
|
||||
/* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
|
||||
/* .. RXRES = 0x1 */
|
||||
/* .. ==> 0XE0001000[0:0] = 0x00000001U */
|
||||
/* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
|
||||
/* .. */
|
||||
EMIT_MASKWRITE(0XE0001000, 0x000001FFU, 0x00000017U),
|
||||
/* .. CHMODE = 0x0 */
|
||||
/* .. ==> 0XE0001004[9:8] = 0x00000000U */
|
||||
/* .. ==> MASK : 0x00000300U VAL : 0x00000000U */
|
||||
/* .. NBSTOP = 0x0 */
|
||||
/* .. ==> 0XE0001004[7:6] = 0x00000000U */
|
||||
/* .. ==> MASK : 0x000000C0U VAL : 0x00000000U */
|
||||
/* .. PAR = 0x4 */
|
||||
/* .. ==> 0XE0001004[5:3] = 0x00000004U */
|
||||
/* .. ==> MASK : 0x00000038U VAL : 0x00000020U */
|
||||
/* .. CHRL = 0x0 */
|
||||
/* .. ==> 0XE0001004[2:1] = 0x00000000U */
|
||||
/* .. ==> MASK : 0x00000006U VAL : 0x00000000U */
|
||||
/* .. CLKS = 0x0 */
|
||||
/* .. ==> 0XE0001004[0:0] = 0x00000000U */
|
||||
/* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
|
||||
/* .. */
|
||||
EMIT_MASKWRITE(0XE0001004, 0x000003FFU, 0x00000020U),
|
||||
/* .. FINISH: UART REGISTERS */
|
||||
/* .. START: QSPI REGISTERS */
|
||||
/* .. Holdb_dr = 1 */
|
||||
/* .. ==> 0XE000D000[19:19] = 0x00000001U */
|
||||
|
|
@ -7944,70 +7886,6 @@ unsigned long ps7_peripherals_init_data_2_0[] = {
|
|||
/* .. FINISH: LOCK IT BACK */
|
||||
/* .. START: SRAM/NOR SET OPMODE */
|
||||
/* .. FINISH: SRAM/NOR SET OPMODE */
|
||||
/* .. START: UART REGISTERS */
|
||||
/* .. BDIV = 0x6 */
|
||||
/* .. ==> 0XE0001034[7:0] = 0x00000006U */
|
||||
/* .. ==> MASK : 0x000000FFU VAL : 0x00000006U */
|
||||
/* .. */
|
||||
EMIT_MASKWRITE(0XE0001034, 0x000000FFU, 0x00000006U),
|
||||
/* .. CD = 0x7c */
|
||||
/* .. ==> 0XE0001018[15:0] = 0x0000007CU */
|
||||
/* .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU */
|
||||
/* .. */
|
||||
EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU, 0x0000007CU),
|
||||
/* .. STPBRK = 0x0 */
|
||||
/* .. ==> 0XE0001000[8:8] = 0x00000000U */
|
||||
/* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
|
||||
/* .. STTBRK = 0x0 */
|
||||
/* .. ==> 0XE0001000[7:7] = 0x00000000U */
|
||||
/* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
|
||||
/* .. RSTTO = 0x0 */
|
||||
/* .. ==> 0XE0001000[6:6] = 0x00000000U */
|
||||
/* .. ==> MASK : 0x00000040U VAL : 0x00000000U */
|
||||
/* .. TXDIS = 0x0 */
|
||||
/* .. ==> 0XE0001000[5:5] = 0x00000000U */
|
||||
/* .. ==> MASK : 0x00000020U VAL : 0x00000000U */
|
||||
/* .. TXEN = 0x1 */
|
||||
/* .. ==> 0XE0001000[4:4] = 0x00000001U */
|
||||
/* .. ==> MASK : 0x00000010U VAL : 0x00000010U */
|
||||
/* .. RXDIS = 0x0 */
|
||||
/* .. ==> 0XE0001000[3:3] = 0x00000000U */
|
||||
/* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
|
||||
/* .. RXEN = 0x1 */
|
||||
/* .. ==> 0XE0001000[2:2] = 0x00000001U */
|
||||
/* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
|
||||
/* .. TXRES = 0x1 */
|
||||
/* .. ==> 0XE0001000[1:1] = 0x00000001U */
|
||||
/* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
|
||||
/* .. RXRES = 0x1 */
|
||||
/* .. ==> 0XE0001000[0:0] = 0x00000001U */
|
||||
/* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
|
||||
/* .. */
|
||||
EMIT_MASKWRITE(0XE0001000, 0x000001FFU, 0x00000017U),
|
||||
/* .. IRMODE = 0x0 */
|
||||
/* .. ==> 0XE0001004[11:11] = 0x00000000U */
|
||||
/* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
|
||||
/* .. UCLKEN = 0x0 */
|
||||
/* .. ==> 0XE0001004[10:10] = 0x00000000U */
|
||||
/* .. ==> MASK : 0x00000400U VAL : 0x00000000U */
|
||||
/* .. CHMODE = 0x0 */
|
||||
/* .. ==> 0XE0001004[9:8] = 0x00000000U */
|
||||
/* .. ==> MASK : 0x00000300U VAL : 0x00000000U */
|
||||
/* .. NBSTOP = 0x0 */
|
||||
/* .. ==> 0XE0001004[7:6] = 0x00000000U */
|
||||
/* .. ==> MASK : 0x000000C0U VAL : 0x00000000U */
|
||||
/* .. PAR = 0x4 */
|
||||
/* .. ==> 0XE0001004[5:3] = 0x00000004U */
|
||||
/* .. ==> MASK : 0x00000038U VAL : 0x00000020U */
|
||||
/* .. CHRL = 0x0 */
|
||||
/* .. ==> 0XE0001004[2:1] = 0x00000000U */
|
||||
/* .. ==> MASK : 0x00000006U VAL : 0x00000000U */
|
||||
/* .. CLKS = 0x0 */
|
||||
/* .. ==> 0XE0001004[0:0] = 0x00000000U */
|
||||
/* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
|
||||
/* .. */
|
||||
EMIT_MASKWRITE(0XE0001004, 0x00000FFFU, 0x00000020U),
|
||||
/* .. FINISH: UART REGISTERS */
|
||||
/* .. START: QSPI REGISTERS */
|
||||
/* .. Holdb_dr = 1 */
|
||||
/* .. ==> 0XE000D000[19:19] = 0x00000001U */
|
||||
|
|
@ -12172,70 +12050,6 @@ unsigned long ps7_peripherals_init_data_1_0[] = {
|
|||
/* .. FINISH: LOCK IT BACK */
|
||||
/* .. START: SRAM/NOR SET OPMODE */
|
||||
/* .. FINISH: SRAM/NOR SET OPMODE */
|
||||
/* .. START: UART REGISTERS */
|
||||
/* .. BDIV = 0x6 */
|
||||
/* .. ==> 0XE0001034[7:0] = 0x00000006U */
|
||||
/* .. ==> MASK : 0x000000FFU VAL : 0x00000006U */
|
||||
/* .. */
|
||||
EMIT_MASKWRITE(0XE0001034, 0x000000FFU, 0x00000006U),
|
||||
/* .. CD = 0x7c */
|
||||
/* .. ==> 0XE0001018[15:0] = 0x0000007CU */
|
||||
/* .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU */
|
||||
/* .. */
|
||||
EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU, 0x0000007CU),
|
||||
/* .. STPBRK = 0x0 */
|
||||
/* .. ==> 0XE0001000[8:8] = 0x00000000U */
|
||||
/* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
|
||||
/* .. STTBRK = 0x0 */
|
||||
/* .. ==> 0XE0001000[7:7] = 0x00000000U */
|
||||
/* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
|
||||
/* .. RSTTO = 0x0 */
|
||||
/* .. ==> 0XE0001000[6:6] = 0x00000000U */
|
||||
/* .. ==> MASK : 0x00000040U VAL : 0x00000000U */
|
||||
/* .. TXDIS = 0x0 */
|
||||
/* .. ==> 0XE0001000[5:5] = 0x00000000U */
|
||||
/* .. ==> MASK : 0x00000020U VAL : 0x00000000U */
|
||||
/* .. TXEN = 0x1 */
|
||||
/* .. ==> 0XE0001000[4:4] = 0x00000001U */
|
||||
/* .. ==> MASK : 0x00000010U VAL : 0x00000010U */
|
||||
/* .. RXDIS = 0x0 */
|
||||
/* .. ==> 0XE0001000[3:3] = 0x00000000U */
|
||||
/* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
|
||||
/* .. RXEN = 0x1 */
|
||||
/* .. ==> 0XE0001000[2:2] = 0x00000001U */
|
||||
/* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
|
||||
/* .. TXRES = 0x1 */
|
||||
/* .. ==> 0XE0001000[1:1] = 0x00000001U */
|
||||
/* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
|
||||
/* .. RXRES = 0x1 */
|
||||
/* .. ==> 0XE0001000[0:0] = 0x00000001U */
|
||||
/* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
|
||||
/* .. */
|
||||
EMIT_MASKWRITE(0XE0001000, 0x000001FFU, 0x00000017U),
|
||||
/* .. IRMODE = 0x0 */
|
||||
/* .. ==> 0XE0001004[11:11] = 0x00000000U */
|
||||
/* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
|
||||
/* .. UCLKEN = 0x0 */
|
||||
/* .. ==> 0XE0001004[10:10] = 0x00000000U */
|
||||
/* .. ==> MASK : 0x00000400U VAL : 0x00000000U */
|
||||
/* .. CHMODE = 0x0 */
|
||||
/* .. ==> 0XE0001004[9:8] = 0x00000000U */
|
||||
/* .. ==> MASK : 0x00000300U VAL : 0x00000000U */
|
||||
/* .. NBSTOP = 0x0 */
|
||||
/* .. ==> 0XE0001004[7:6] = 0x00000000U */
|
||||
/* .. ==> MASK : 0x000000C0U VAL : 0x00000000U */
|
||||
/* .. PAR = 0x4 */
|
||||
/* .. ==> 0XE0001004[5:3] = 0x00000004U */
|
||||
/* .. ==> MASK : 0x00000038U VAL : 0x00000020U */
|
||||
/* .. CHRL = 0x0 */
|
||||
/* .. ==> 0XE0001004[2:1] = 0x00000000U */
|
||||
/* .. ==> MASK : 0x00000006U VAL : 0x00000000U */
|
||||
/* .. CLKS = 0x0 */
|
||||
/* .. ==> 0XE0001004[0:0] = 0x00000000U */
|
||||
/* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
|
||||
/* .. */
|
||||
EMIT_MASKWRITE(0XE0001004, 0x00000FFFU, 0x00000020U),
|
||||
/* .. FINISH: UART REGISTERS */
|
||||
/* .. START: QSPI REGISTERS */
|
||||
/* .. Holdb_dr = 1 */
|
||||
/* .. ==> 0XE000D000[19:19] = 0x00000001U */
|
||||
|
|
|
|||
|
|
@ -14,7 +14,7 @@ spl/board/xilinx/zynqmp/ps_init_gpl.o board/xilinx/zynqmp/ps_init_gpl.o: $(PS_IN
|
|||
endif
|
||||
|
||||
ifeq ($(init-objs),)
|
||||
hw-platform-y :=$(shell echo $(CONFIG_DEFAULT_DEVICE_TREE))
|
||||
hw-platform-y :=$(shell echo $(DEVICE_TREE))
|
||||
init-objs := $(if $(wildcard $(srctree)/$(src)/$(hw-platform-y)/psu_init_gpl.c),\
|
||||
$(hw-platform-y)/psu_init_gpl.o)
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -506,14 +506,6 @@ static unsigned long psu_peripherals_init_data(void)
|
|||
psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U);
|
||||
psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U);
|
||||
psu_mask_write(0xFF5E0238, 0x00000006U, 0x00000000U);
|
||||
psu_mask_write(0xFF000034, 0x000000FFU, 0x00000005U);
|
||||
psu_mask_write(0xFF000018, 0x0000FFFFU, 0x0000008FU);
|
||||
psu_mask_write(0xFF000000, 0x000001FFU, 0x00000017U);
|
||||
psu_mask_write(0xFF000004, 0x000003FFU, 0x00000020U);
|
||||
psu_mask_write(0xFF010034, 0x000000FFU, 0x00000005U);
|
||||
psu_mask_write(0xFF010018, 0x0000FFFFU, 0x0000008FU);
|
||||
psu_mask_write(0xFF010000, 0x000001FFU, 0x00000017U);
|
||||
psu_mask_write(0xFF010004, 0x000003FFU, 0x00000020U);
|
||||
psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U);
|
||||
psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
|
||||
psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
|
||||
|
|
|
|||
|
|
@ -479,14 +479,6 @@ static unsigned long psu_peripherals_init_data(void)
|
|||
psu_mask_write(0xFF180324, 0x03C00000U, 0x00000000U);
|
||||
psu_mask_write(0xFF5E0238, 0x00000600U, 0x00000000U);
|
||||
psu_mask_write(0xFF5E0238, 0x00000006U, 0x00000000U);
|
||||
psu_mask_write(0xFF000034, 0x000000FFU, 0x00000005U);
|
||||
psu_mask_write(0xFF000018, 0x0000FFFFU, 0x0000008FU);
|
||||
psu_mask_write(0xFF000000, 0x000001FFU, 0x00000017U);
|
||||
psu_mask_write(0xFF000004, 0x000003FFU, 0x00000020U);
|
||||
psu_mask_write(0xFF010034, 0x000000FFU, 0x00000005U);
|
||||
psu_mask_write(0xFF010018, 0x0000FFFFU, 0x0000008FU);
|
||||
psu_mask_write(0xFF010000, 0x000001FFU, 0x00000017U);
|
||||
psu_mask_write(0xFF010004, 0x000003FFU, 0x00000020U);
|
||||
psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U);
|
||||
psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
|
||||
psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
|
||||
|
|
|
|||
1
board/xilinx/zynqmp/zynqmp-m-a2197-03-revA
Symbolic link
1
board/xilinx/zynqmp/zynqmp-m-a2197-03-revA
Symbolic link
|
|
@ -0,0 +1 @@
|
|||
zynqmp-a2197-revA
|
||||
1
board/xilinx/zynqmp/zynqmp-p-a2197-00-revA
Symbolic link
1
board/xilinx/zynqmp/zynqmp-p-a2197-00-revA
Symbolic link
|
|
@ -0,0 +1 @@
|
|||
zynqmp-a2197-revA
|
||||
|
|
@ -388,10 +388,6 @@ static unsigned long psu_peripherals_init_data(void)
|
|||
psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U);
|
||||
psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U);
|
||||
psu_mask_write(0xFF5E0238, 0x00000002U, 0x00000000U);
|
||||
psu_mask_write(0xFF000034, 0x000000FFU, 0x00000005U);
|
||||
psu_mask_write(0xFF000018, 0x0000FFFFU, 0x0000008FU);
|
||||
psu_mask_write(0xFF000000, 0x000001FFU, 0x00000017U);
|
||||
psu_mask_write(0xFF000004, 0x000003FFU, 0x00000020U);
|
||||
psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U);
|
||||
psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
|
||||
psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
|
||||
|
|
|
|||
|
|
@ -378,10 +378,6 @@ static unsigned long psu_peripherals_init_data(void)
|
|||
psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000000U);
|
||||
psu_mask_write(0xFF180390, 0x00000004U, 0x00000000U);
|
||||
psu_mask_write(0xFF5E0238, 0x00000002U, 0x00000000U);
|
||||
psu_mask_write(0xFF000034, 0x000000FFU, 0x00000005U);
|
||||
psu_mask_write(0xFF000018, 0x0000FFFFU, 0x0000008FU);
|
||||
psu_mask_write(0xFF000000, 0x000001FFU, 0x00000017U);
|
||||
psu_mask_write(0xFF000004, 0x000003FFU, 0x00000020U);
|
||||
psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U);
|
||||
psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
|
||||
psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
|
||||
|
|
|
|||
|
|
@ -427,10 +427,6 @@ static unsigned long psu_peripherals_init_data(void)
|
|||
psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U);
|
||||
psu_mask_write(0xFF5E0238, 0x00000800U, 0x00000000U);
|
||||
psu_mask_write(0xFF5E0238, 0x00000002U, 0x00000000U);
|
||||
psu_mask_write(0xFF000034, 0x000000FFU, 0x00000005U);
|
||||
psu_mask_write(0xFF000018, 0x0000FFFFU, 0x0000008FU);
|
||||
psu_mask_write(0xFF000000, 0x000001FFU, 0x00000017U);
|
||||
psu_mask_write(0xFF000004, 0x000003FFU, 0x00000020U);
|
||||
psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U);
|
||||
psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
|
||||
psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
|
||||
|
|
|
|||
|
|
@ -475,10 +475,6 @@ static unsigned long psu_peripherals_init_data(void)
|
|||
psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U);
|
||||
psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U);
|
||||
psu_mask_write(0xFF5E0238, 0x00000002U, 0x00000000U);
|
||||
psu_mask_write(0xFF000034, 0x000000FFU, 0x00000005U);
|
||||
psu_mask_write(0xFF000018, 0x0000FFFFU, 0x0000008FU);
|
||||
psu_mask_write(0xFF000000, 0x000001FFU, 0x00000017U);
|
||||
psu_mask_write(0xFF000004, 0x000003FFU, 0x00000020U);
|
||||
psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U);
|
||||
psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
|
||||
psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
|
||||
|
|
|
|||
|
|
@ -477,14 +477,6 @@ static unsigned long psu_peripherals_init_data(void)
|
|||
psu_mask_write(0xFF5E0238, 0x00000018U, 0x00000000U);
|
||||
psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U);
|
||||
psu_mask_write(0xFF5E0238, 0x00000006U, 0x00000000U);
|
||||
psu_mask_write(0xFF000034, 0x000000FFU, 0x00000005U);
|
||||
psu_mask_write(0xFF000018, 0x0000FFFFU, 0x0000008FU);
|
||||
psu_mask_write(0xFF000000, 0x000001FFU, 0x00000017U);
|
||||
psu_mask_write(0xFF000004, 0x000003FFU, 0x00000020U);
|
||||
psu_mask_write(0xFF010034, 0x000000FFU, 0x00000005U);
|
||||
psu_mask_write(0xFF010018, 0x0000FFFFU, 0x0000008FU);
|
||||
psu_mask_write(0xFF010000, 0x000001FFU, 0x00000017U);
|
||||
psu_mask_write(0xFF010004, 0x000003FFU, 0x00000020U);
|
||||
psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U);
|
||||
psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
|
||||
psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
|
||||
|
|
|
|||
|
|
@ -477,14 +477,6 @@ static unsigned long psu_peripherals_init_data(void)
|
|||
psu_mask_write(0xFF5E0238, 0x00000018U, 0x00000000U);
|
||||
psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U);
|
||||
psu_mask_write(0xFF5E0238, 0x00000006U, 0x00000000U);
|
||||
psu_mask_write(0xFF000034, 0x000000FFU, 0x00000005U);
|
||||
psu_mask_write(0xFF000018, 0x0000FFFFU, 0x0000008FU);
|
||||
psu_mask_write(0xFF000000, 0x000001FFU, 0x00000017U);
|
||||
psu_mask_write(0xFF000004, 0x000003FFU, 0x00000020U);
|
||||
psu_mask_write(0xFF010034, 0x000000FFU, 0x00000005U);
|
||||
psu_mask_write(0xFF010018, 0x0000FFFFU, 0x0000008FU);
|
||||
psu_mask_write(0xFF010000, 0x000001FFU, 0x00000017U);
|
||||
psu_mask_write(0xFF010004, 0x000003FFU, 0x00000020U);
|
||||
psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U);
|
||||
psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
|
||||
psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
|
||||
|
|
|
|||
|
|
@ -477,14 +477,6 @@ static unsigned long psu_peripherals_init_data(void)
|
|||
psu_mask_write(0xFF5E0238, 0x00000018U, 0x00000000U);
|
||||
psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U);
|
||||
psu_mask_write(0xFF5E0238, 0x00000006U, 0x00000000U);
|
||||
psu_mask_write(0xFF000034, 0x000000FFU, 0x00000005U);
|
||||
psu_mask_write(0xFF000018, 0x0000FFFFU, 0x0000008FU);
|
||||
psu_mask_write(0xFF000000, 0x000001FFU, 0x00000017U);
|
||||
psu_mask_write(0xFF000004, 0x000003FFU, 0x00000020U);
|
||||
psu_mask_write(0xFF010034, 0x000000FFU, 0x00000005U);
|
||||
psu_mask_write(0xFF010018, 0x0000FFFFU, 0x0000008FU);
|
||||
psu_mask_write(0xFF010000, 0x000001FFU, 0x00000017U);
|
||||
psu_mask_write(0xFF010004, 0x000003FFU, 0x00000020U);
|
||||
psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U);
|
||||
psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
|
||||
psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
|
||||
|
|
|
|||
|
|
@ -471,14 +471,6 @@ static unsigned long psu_peripherals_init_data(void)
|
|||
psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U);
|
||||
psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U);
|
||||
psu_mask_write(0xFF5E0238, 0x00000006U, 0x00000000U);
|
||||
psu_mask_write(0xFF000034, 0x000000FFU, 0x00000005U);
|
||||
psu_mask_write(0xFF000018, 0x0000FFFFU, 0x0000008FU);
|
||||
psu_mask_write(0xFF000000, 0x000001FFU, 0x00000017U);
|
||||
psu_mask_write(0xFF000004, 0x000003FFU, 0x00000020U);
|
||||
psu_mask_write(0xFF010034, 0x000000FFU, 0x00000005U);
|
||||
psu_mask_write(0xFF010018, 0x0000FFFFU, 0x0000008FU);
|
||||
psu_mask_write(0xFF010000, 0x000001FFU, 0x00000017U);
|
||||
psu_mask_write(0xFF010004, 0x000003FFU, 0x00000020U);
|
||||
psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U);
|
||||
psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
|
||||
psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
|
||||
|
|
|
|||
|
|
@ -409,7 +409,6 @@ static unsigned long psu_mio_init_data(void)
|
|||
psu_mask_write(0xFF18007C, 0x000000FEU, 0x00000000U);
|
||||
psu_mask_write(0xFF180080, 0x000000FEU, 0x00000008U);
|
||||
psu_mask_write(0xFF180084, 0x000000FEU, 0x00000008U);
|
||||
psu_mask_write(0xFF180088, 0x000000FEU, 0x00000008U);
|
||||
psu_mask_write(0xFF18008C, 0x000000FEU, 0x00000000U);
|
||||
psu_mask_write(0xFF180090, 0x000000FEU, 0x00000000U);
|
||||
psu_mask_write(0xFF180094, 0x000000FEU, 0x00000000U);
|
||||
|
|
@ -499,14 +498,6 @@ static unsigned long psu_peripherals_init_data(void)
|
|||
psu_mask_write(0xFF5E0238, 0x00000800U, 0x00000000U);
|
||||
psu_mask_write(0xFF5E0238, 0x00000006U, 0x00000000U);
|
||||
psu_mask_write(0xFD4AB120, 0x00000007U, 0x00000007U);
|
||||
psu_mask_write(0xFF000034, 0x000000FFU, 0x00000005U);
|
||||
psu_mask_write(0xFF000018, 0x0000FFFFU, 0x0000008FU);
|
||||
psu_mask_write(0xFF000000, 0x000001FFU, 0x00000017U);
|
||||
psu_mask_write(0xFF000004, 0x000003FFU, 0x00000020U);
|
||||
psu_mask_write(0xFF010034, 0x000000FFU, 0x00000005U);
|
||||
psu_mask_write(0xFF010018, 0x0000FFFFU, 0x0000008FU);
|
||||
psu_mask_write(0xFF010000, 0x000001FFU, 0x00000017U);
|
||||
psu_mask_write(0xFF010004, 0x000003FFU, 0x00000020U);
|
||||
psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U);
|
||||
psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
|
||||
psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
|
||||
|
|
@ -990,3 +981,9 @@ int psu_init(void)
|
|||
return 1;
|
||||
return 0;
|
||||
}
|
||||
|
||||
unsigned long psu_post_config_data(void)
|
||||
{
|
||||
psu_mask_write(0xFF180088, 0x000000FEU, 0x00000008U);
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -479,14 +479,6 @@ static unsigned long psu_peripherals_init_data(void)
|
|||
psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U);
|
||||
psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U);
|
||||
psu_mask_write(0xFF5E0238, 0x00000006U, 0x00000000U);
|
||||
psu_mask_write(0xFF000034, 0x000000FFU, 0x00000005U);
|
||||
psu_mask_write(0xFF000018, 0x0000FFFFU, 0x0000008FU);
|
||||
psu_mask_write(0xFF000000, 0x000001FFU, 0x00000017U);
|
||||
psu_mask_write(0xFF000004, 0x000003FFU, 0x00000020U);
|
||||
psu_mask_write(0xFF010034, 0x000000FFU, 0x00000005U);
|
||||
psu_mask_write(0xFF010018, 0x0000FFFFU, 0x0000008FU);
|
||||
psu_mask_write(0xFF010000, 0x000001FFU, 0x00000017U);
|
||||
psu_mask_write(0xFF010004, 0x000003FFU, 0x00000020U);
|
||||
psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U);
|
||||
psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
|
||||
psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
|
||||
|
|
|
|||
|
|
@ -486,14 +486,6 @@ static unsigned long psu_peripherals_init_data(void)
|
|||
psu_mask_write(0xFE980FB0, 0xFFFFFFFFU, 0xC5ACCE55U);
|
||||
psu_mask_write(0xFE980004, 0x80000000U, 0x80000000U);
|
||||
psu_mask_write(0xFE980FB0, 0xFFFFFFFFU, 0x00000000U);
|
||||
psu_mask_write(0xFF000034, 0x000000FFU, 0x00000005U);
|
||||
psu_mask_write(0xFF000018, 0x0000FFFFU, 0x0000008FU);
|
||||
psu_mask_write(0xFF000000, 0x000001FFU, 0x00000017U);
|
||||
psu_mask_write(0xFF000004, 0x000003FFU, 0x00000020U);
|
||||
psu_mask_write(0xFF010034, 0x000000FFU, 0x00000005U);
|
||||
psu_mask_write(0xFF010018, 0x0000FFFFU, 0x0000008FU);
|
||||
psu_mask_write(0xFF010000, 0x000001FFU, 0x00000017U);
|
||||
psu_mask_write(0xFF010004, 0x000003FFU, 0x00000020U);
|
||||
psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
|
||||
psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
|
||||
psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U);
|
||||
|
|
|
|||
|
|
@ -455,14 +455,6 @@ static unsigned long psu_peripherals_init_data(void)
|
|||
psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U);
|
||||
psu_mask_write(0xFF5E0238, 0x00000006U, 0x00000000U);
|
||||
psu_mask_write(0xFD4AB120, 0x00000007U, 0x00000007U);
|
||||
psu_mask_write(0xFF000034, 0x000000FFU, 0x00000005U);
|
||||
psu_mask_write(0xFF000018, 0x0000FFFFU, 0x0000008FU);
|
||||
psu_mask_write(0xFF000000, 0x000001FFU, 0x00000017U);
|
||||
psu_mask_write(0xFF000004, 0x000003FFU, 0x00000020U);
|
||||
psu_mask_write(0xFF010034, 0x000000FFU, 0x00000005U);
|
||||
psu_mask_write(0xFF010018, 0x0000FFFFU, 0x0000008FU);
|
||||
psu_mask_write(0xFF010000, 0x000001FFU, 0x00000017U);
|
||||
psu_mask_write(0xFF010004, 0x000003FFU, 0x00000020U);
|
||||
psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U);
|
||||
psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
|
||||
psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
|
||||
|
|
|
|||
|
|
@ -463,14 +463,6 @@ static unsigned long psu_peripherals_init_data(void)
|
|||
psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U);
|
||||
psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U);
|
||||
psu_mask_write(0xFF5E0238, 0x00000006U, 0x00000000U);
|
||||
psu_mask_write(0xFF000034, 0x000000FFU, 0x00000005U);
|
||||
psu_mask_write(0xFF000018, 0x0000FFFFU, 0x0000008FU);
|
||||
psu_mask_write(0xFF000000, 0x000001FFU, 0x00000017U);
|
||||
psu_mask_write(0xFF000004, 0x000003FFU, 0x00000020U);
|
||||
psu_mask_write(0xFF010034, 0x000000FFU, 0x00000005U);
|
||||
psu_mask_write(0xFF010018, 0x0000FFFFU, 0x0000008FU);
|
||||
psu_mask_write(0xFF010000, 0x000001FFU, 0x00000017U);
|
||||
psu_mask_write(0xFF010004, 0x000003FFU, 0x00000020U);
|
||||
psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
|
||||
psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
|
||||
psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U);
|
||||
|
|
|
|||
|
|
@ -580,8 +580,17 @@ int board_late_init(void)
|
|||
break;
|
||||
case EMMC_MODE:
|
||||
puts("EMMC_MODE\n");
|
||||
mode = "mmc0";
|
||||
env_set("modeboot", "emmcboot");
|
||||
if (uclass_get_device_by_name(UCLASS_MMC,
|
||||
"mmc@ff160000", &dev) &&
|
||||
uclass_get_device_by_name(UCLASS_MMC,
|
||||
"sdhci@ff160000", &dev)) {
|
||||
puts("Boot from EMMC but without SD0 enabled!\n");
|
||||
return -1;
|
||||
}
|
||||
debug("mmc0 device found at %p, seq %d\n", dev, dev->seq);
|
||||
|
||||
mode = "mmc";
|
||||
bootseq = dev->seq;
|
||||
break;
|
||||
case SD_MODE:
|
||||
puts("SD_MODE\n");
|
||||
|
|
@ -658,6 +667,8 @@ int board_late_init(void)
|
|||
initrd_hi = round_down(initrd_hi, SZ_16M);
|
||||
env_set_addr("initrd_high", (void *)initrd_hi);
|
||||
|
||||
env_set_hex("script_offset_f", CONFIG_BOOT_SCRIPT_OFFSET);
|
||||
|
||||
reset_reason();
|
||||
|
||||
return 0;
|
||||
|
|
|
|||
|
|
@ -18,20 +18,7 @@
|
|||
static struct bl2_to_bl31_params_mem bl31_params_mem;
|
||||
static struct bl31_params *bl2_to_bl31_params;
|
||||
|
||||
/**
|
||||
* bl2_plat_get_bl31_params() - prepare params for bl31.
|
||||
*
|
||||
* This function assigns a pointer to the memory that the platform has kept
|
||||
* aside to pass platform specific and trusted firmware related information
|
||||
* to BL31. This memory is allocated by allocating memory to
|
||||
* bl2_to_bl31_params_mem structure which is a superset of all the
|
||||
* structure whose information is passed to BL31
|
||||
* NOTE: This function should be called only once and should be done
|
||||
* before generating params to BL31
|
||||
*
|
||||
* @return bl31 params structure pointer
|
||||
*/
|
||||
static struct bl31_params *bl2_plat_get_bl31_params(uintptr_t bl32_entry,
|
||||
__weak struct bl31_params *bl2_plat_get_bl31_params(uintptr_t bl32_entry,
|
||||
uintptr_t bl33_entry,
|
||||
uintptr_t fdt_addr)
|
||||
{
|
||||
|
|
@ -112,7 +99,7 @@ static void bl31_entry(uintptr_t bl31_entry, uintptr_t bl32_entry,
|
|||
|
||||
static int spl_fit_images_find(void *blob, int os)
|
||||
{
|
||||
int parent, node, ndepth;
|
||||
int parent, node, ndepth = 0;
|
||||
const void *data;
|
||||
|
||||
if (!blob)
|
||||
|
|
|
|||
|
|
@ -1,90 +0,0 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_ZYNQMP=y
|
||||
CONFIG_SYS_TEXT_BASE=0x8000000
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x8000
|
||||
CONFIG_SPL=y
|
||||
CONFIG_DEBUG_UART_BASE=0xff010000
|
||||
CONFIG_DEBUG_UART_CLOCK=100000000
|
||||
CONFIG_ZYNQ_SDHCI_MAX_FREQ=15000000
|
||||
CONFIG_ZYNQMP_USB=y
|
||||
CONFIG_DEBUG_UART=y
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_SPL_LOAD_FIT=y
|
||||
# CONFIG_DISPLAY_CPUINFO is not set
|
||||
CONFIG_SPL_OS_BOOT=y
|
||||
CONFIG_SPL_RAM_SUPPORT=y
|
||||
CONFIG_SPL_RAM_DEVICE=y
|
||||
CONFIG_SPL_ATF=y
|
||||
CONFIG_CMD_BOOTMENU=y
|
||||
CONFIG_CMD_MEMTEST=y
|
||||
CONFIG_CMD_BIND=y
|
||||
CONFIG_CMD_CLK=y
|
||||
CONFIG_CMD_DFU=y
|
||||
CONFIG_CMD_FPGA_LOADBP=y
|
||||
CONFIG_CMD_FPGA_LOADP=y
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_POWEROFF=y
|
||||
CONFIG_CMD_SPI=y
|
||||
CONFIG_CMD_USB=y
|
||||
CONFIG_CMD_USB_MASS_STORAGE=y
|
||||
CONFIG_CMD_TFTPPUT=y
|
||||
CONFIG_CMD_TIME=y
|
||||
CONFIG_CMD_TIMER=y
|
||||
CONFIG_CMD_EXT4_WRITE=y
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="avnet-ultra96-rev1"
|
||||
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_SPL_DM=y
|
||||
CONFIG_SPL_DM_SEQ_ALIAS=y
|
||||
CONFIG_CLK_ZYNQMP=y
|
||||
CONFIG_DFU_RAM=y
|
||||
CONFIG_FPGA_XILINX=y
|
||||
CONFIG_FPGA_ZYNQMPPL=y
|
||||
CONFIG_DM_GPIO=y
|
||||
CONFIG_XILINX_GPIO=y
|
||||
CONFIG_DM_I2C=y
|
||||
CONFIG_SYS_I2C_CADENCE=y
|
||||
CONFIG_I2C_MUX=y
|
||||
CONFIG_I2C_MUX_PCA954x=y
|
||||
CONFIG_LED=y
|
||||
CONFIG_LED_GPIO=y
|
||||
CONFIG_MISC=y
|
||||
CONFIG_SUPPORT_EMMC_BOOT=y
|
||||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_ZYNQ=y
|
||||
CONFIG_SPI_FLASH_BAR=y
|
||||
CONFIG_SPI_FLASH_ISSI=y
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
|
||||
# CONFIG_NETDEVICES is not set
|
||||
CONFIG_DEBUG_UART_ZYNQ=y
|
||||
CONFIG_DEBUG_UART_ANNOUNCE=y
|
||||
CONFIG_ZYNQ_SERIAL=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_ZYNQ_SPI=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_XHCI_DWC3=y
|
||||
CONFIG_USB_DWC3=y
|
||||
CONFIG_USB_DWC3_GENERIC=y
|
||||
CONFIG_USB_ULPI_VIEWPORT=y
|
||||
CONFIG_USB_ULPI=y
|
||||
CONFIG_USB_GADGET=y
|
||||
CONFIG_USB_GADGET_DOWNLOAD=y
|
||||
CONFIG_USB_ETHER=y
|
||||
CONFIG_USB_ETH_CDC=y
|
||||
CONFIG_USB_HOST_ETHER=y
|
||||
CONFIG_USB_ETHER_ASIX=y
|
||||
CONFIG_WDT=y
|
||||
CONFIG_WDT_CDNS=y
|
||||
CONFIG_SPL_GZIP=y
|
||||
CONFIG_OF_LIBFDT_OVERLAY=y
|
||||
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
|
||||
|
|
@ -7,7 +7,6 @@ CONFIG_DEBUG_UART_BASE=0xff000000
|
|||
CONFIG_DEBUG_UART_CLOCK=100000000
|
||||
CONFIG_SPL_SPI_FLASH_SUPPORT=y
|
||||
CONFIG_SPL_SPI_SUPPORT=y
|
||||
CONFIG_SPL_ZYNQMP_TWO_SDHCI=y
|
||||
CONFIG_DEBUG_UART=y
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_FIT=y
|
||||
|
|
@ -57,5 +56,6 @@ CONFIG_DEBUG_UART_ANNOUNCE=y
|
|||
CONFIG_ZYNQ_SERIAL=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_ZYNQMP_GQSPI=y
|
||||
CONFIG_PANIC_HANG=y
|
||||
CONFIG_OF_LIBFDT_OVERLAY=y
|
||||
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
|
||||
|
|
|
|||
|
|
@ -9,7 +9,6 @@ CONFIG_FIT_VERBOSE=y
|
|||
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
|
||||
CONFIG_BOOTDELAY=5
|
||||
CONFIG_SUPPORT_RAW_INITRD=y
|
||||
# CONFIG_BOARD_LATE_INIT is not set
|
||||
# CONFIG_DISPLAY_CPUINFO is not set
|
||||
CONFIG_BOARD_EARLY_INIT_R=y
|
||||
CONFIG_HUSH_PARSER=y
|
||||
|
|
|
|||
|
|
@ -1,113 +0,0 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_ZYNQMP=y
|
||||
CONFIG_SYS_TEXT_BASE=0x8000000
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x8000
|
||||
CONFIG_SPL=y
|
||||
CONFIG_DEBUG_UART_BASE=0xff000000
|
||||
CONFIG_DEBUG_UART_CLOCK=100000000
|
||||
CONFIG_IDENT_STRING=" Xilinx ZynqMP SC for Versal"
|
||||
CONFIG_SPL_SPI_FLASH_SUPPORT=y
|
||||
CONFIG_SPL_SPI_SUPPORT=y
|
||||
CONFIG_ZYNQMP_USB=y
|
||||
CONFIG_DEBUG_UART=y
|
||||
CONFIG_AHCI=y
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_SPL_LOAD_FIT=y
|
||||
# CONFIG_DISPLAY_CPUINFO is not set
|
||||
CONFIG_BOARD_EARLY_INIT_R=y
|
||||
CONFIG_SPL_OS_BOOT=y
|
||||
CONFIG_SPL_RAM_SUPPORT=y
|
||||
CONFIG_SPL_RAM_DEVICE=y
|
||||
CONFIG_SPL_ATF=y
|
||||
CONFIG_CMD_THOR_DOWNLOAD=y
|
||||
CONFIG_CMD_MEMTEST=y
|
||||
CONFIG_SYS_ALT_MEMTEST=y
|
||||
CONFIG_CMD_CLK=y
|
||||
CONFIG_CMD_DFU=y
|
||||
CONFIG_CMD_FPGA_LOADBP=y
|
||||
CONFIG_CMD_FPGA_LOADP=y
|
||||
CONFIG_CMD_FPGA_LOAD_SECURE=y
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_GPT=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_SDRAM=y
|
||||
CONFIG_CMD_USB=y
|
||||
CONFIG_CMD_TFTPPUT=y
|
||||
CONFIG_CMD_TIME=y
|
||||
CONFIG_CMD_TIMER=y
|
||||
CONFIG_CMD_EXT4_WRITE=y
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-a2197-revA"
|
||||
CONFIG_OF_LIST="zynqmp-a2197-revA zynqmp-g-a2197-00-revA zynqmp-p-a2197-00-revA zynqmp-m-a2197-01-revA zynqmp-m-a2197-02-revA zynqmp-m-a2197-03-revA"
|
||||
CONFIG_ENV_IS_IN_FAT=y
|
||||
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_SPL_DM=y
|
||||
CONFIG_SPL_DM_SEQ_ALIAS=y
|
||||
CONFIG_SCSI_AHCI=y
|
||||
CONFIG_SATA_CEVA=y
|
||||
CONFIG_CLK_ZYNQMP=y
|
||||
CONFIG_DFU_RAM=y
|
||||
CONFIG_USB_FUNCTION_FASTBOOT=y
|
||||
CONFIG_FASTBOOT_FLASH=y
|
||||
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
|
||||
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
|
||||
CONFIG_FPGA_XILINX=y
|
||||
CONFIG_FPGA_ZYNQMPPL=y
|
||||
CONFIG_DM_GPIO=y
|
||||
CONFIG_XILINX_GPIO=y
|
||||
CONFIG_DM_PCA953X=y
|
||||
CONFIG_DM_I2C=y
|
||||
CONFIG_SYS_I2C_CADENCE=y
|
||||
CONFIG_I2C_MUX=y
|
||||
CONFIG_I2C_MUX_PCA954x=y
|
||||
CONFIG_LED=y
|
||||
CONFIG_LED_GPIO=y
|
||||
CONFIG_MISC=y
|
||||
CONFIG_I2C_EEPROM=y
|
||||
CONFIG_SYS_I2C_EEPROM_ADDR=0x0
|
||||
CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0
|
||||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_ZYNQ=y
|
||||
CONFIG_SPI_FLASH_BAR=y
|
||||
CONFIG_SF_DUAL_FLASH=y
|
||||
CONFIG_SPI_FLASH_ISSI=y
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
|
||||
CONFIG_PHY_MARVELL=y
|
||||
CONFIG_PHY_NATSEMI=y
|
||||
CONFIG_PHY_REALTEK=y
|
||||
CONFIG_PHY_TI=y
|
||||
CONFIG_PHY_VITESSE=y
|
||||
CONFIG_PHY_FIXED=y
|
||||
CONFIG_PHY_GIGE=y
|
||||
CONFIG_MII=y
|
||||
CONFIG_ZYNQ_GEM=y
|
||||
CONFIG_SCSI=y
|
||||
CONFIG_DM_SCSI=y
|
||||
CONFIG_DEBUG_UART_ZYNQ=y
|
||||
CONFIG_DEBUG_UART_ANNOUNCE=y
|
||||
CONFIG_ZYNQ_SERIAL=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_ZYNQMP_GQSPI=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_XHCI_DWC3=y
|
||||
CONFIG_USB_DWC3=y
|
||||
CONFIG_USB_DWC3_GENERIC=y
|
||||
CONFIG_USB_ULPI_VIEWPORT=y
|
||||
CONFIG_USB_ULPI=y
|
||||
CONFIG_USB_GADGET=y
|
||||
CONFIG_USB_GADGET_MANUFACTURER="Xilinx"
|
||||
CONFIG_USB_GADGET_VENDOR_NUM=0x03FD
|
||||
CONFIG_USB_GADGET_PRODUCT_NUM=0x0300
|
||||
CONFIG_USB_FUNCTION_THOR=y
|
||||
CONFIG_SPL_GZIP=y
|
||||
CONFIG_OF_LIBFDT_OVERLAY=y
|
||||
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
|
||||
|
|
@ -1,111 +0,0 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_ZYNQMP=y
|
||||
CONFIG_SYS_TEXT_BASE=0x8000000
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x8000
|
||||
CONFIG_SPL=y
|
||||
CONFIG_DEBUG_UART_BASE=0xff000000
|
||||
CONFIG_DEBUG_UART_CLOCK=100000000
|
||||
CONFIG_IDENT_STRING=" Xilinx ZynqMP SC for Versal"
|
||||
CONFIG_SPL_SPI_FLASH_SUPPORT=y
|
||||
CONFIG_SPL_SPI_SUPPORT=y
|
||||
CONFIG_ZYNQMP_USB=y
|
||||
CONFIG_DEBUG_UART=y
|
||||
CONFIG_AHCI=y
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_SPL_LOAD_FIT=y
|
||||
# CONFIG_DISPLAY_CPUINFO is not set
|
||||
CONFIG_BOARD_EARLY_INIT_R=y
|
||||
CONFIG_SPL_OS_BOOT=y
|
||||
CONFIG_SPL_RAM_SUPPORT=y
|
||||
CONFIG_SPL_RAM_DEVICE=y
|
||||
CONFIG_SPL_ATF=y
|
||||
CONFIG_CMD_THOR_DOWNLOAD=y
|
||||
CONFIG_CMD_MEMTEST=y
|
||||
CONFIG_SYS_ALT_MEMTEST=y
|
||||
CONFIG_CMD_CLK=y
|
||||
CONFIG_CMD_DFU=y
|
||||
CONFIG_CMD_FPGA_LOADBP=y
|
||||
CONFIG_CMD_FPGA_LOADP=y
|
||||
CONFIG_CMD_FPGA_LOAD_SECURE=y
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_GPT=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_SDRAM=y
|
||||
CONFIG_CMD_USB=y
|
||||
CONFIG_CMD_TFTPPUT=y
|
||||
CONFIG_CMD_TIME=y
|
||||
CONFIG_CMD_TIMER=y
|
||||
CONFIG_CMD_EXT4_WRITE=y
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-e-a2197-00-revA"
|
||||
CONFIG_ENV_IS_IN_FAT=y
|
||||
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_SPL_DM=y
|
||||
CONFIG_SPL_DM_SEQ_ALIAS=y
|
||||
CONFIG_SCSI_AHCI=y
|
||||
CONFIG_SATA_CEVA=y
|
||||
CONFIG_CLK_ZYNQMP=y
|
||||
CONFIG_DFU_RAM=y
|
||||
CONFIG_USB_FUNCTION_FASTBOOT=y
|
||||
CONFIG_FASTBOOT_FLASH=y
|
||||
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
|
||||
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
|
||||
CONFIG_FPGA_XILINX=y
|
||||
CONFIG_FPGA_ZYNQMPPL=y
|
||||
CONFIG_DM_GPIO=y
|
||||
CONFIG_XILINX_GPIO=y
|
||||
CONFIG_DM_PCA953X=y
|
||||
CONFIG_DM_I2C=y
|
||||
CONFIG_SYS_I2C_CADENCE=y
|
||||
CONFIG_I2C_MUX=y
|
||||
CONFIG_I2C_MUX_PCA954x=y
|
||||
CONFIG_LED=y
|
||||
CONFIG_LED_GPIO=y
|
||||
CONFIG_MISC=y
|
||||
CONFIG_I2C_EEPROM=y
|
||||
CONFIG_SYS_I2C_EEPROM_ADDR=0x0
|
||||
CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0
|
||||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_ZYNQ=y
|
||||
CONFIG_SPI_FLASH_BAR=y
|
||||
CONFIG_SF_DUAL_FLASH=y
|
||||
CONFIG_SPI_FLASH_ISSI=y
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
|
||||
CONFIG_PHY_MARVELL=y
|
||||
CONFIG_PHY_NATSEMI=y
|
||||
CONFIG_PHY_REALTEK=y
|
||||
CONFIG_PHY_TI=y
|
||||
CONFIG_PHY_VITESSE=y
|
||||
CONFIG_PHY_FIXED=y
|
||||
CONFIG_PHY_GIGE=y
|
||||
CONFIG_MII=y
|
||||
CONFIG_ZYNQ_GEM=y
|
||||
CONFIG_SCSI=y
|
||||
CONFIG_DM_SCSI=y
|
||||
CONFIG_DEBUG_UART_ZYNQ=y
|
||||
CONFIG_DEBUG_UART_ANNOUNCE=y
|
||||
CONFIG_ZYNQ_SERIAL=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_ZYNQMP_GQSPI=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_XHCI_DWC3=y
|
||||
CONFIG_USB_DWC3=y
|
||||
CONFIG_USB_DWC3_GENERIC=y
|
||||
CONFIG_USB_ULPI_VIEWPORT=y
|
||||
CONFIG_USB_ULPI=y
|
||||
CONFIG_USB_GADGET=y
|
||||
CONFIG_USB_GADGET_MANUFACTURER="Xilinx"
|
||||
CONFIG_USB_GADGET_VENDOR_NUM=0x03FD
|
||||
CONFIG_USB_GADGET_PRODUCT_NUM=0x0300
|
||||
CONFIG_USB_FUNCTION_THOR=y
|
||||
CONFIG_SPL_GZIP=y
|
||||
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
|
||||
|
|
@ -1,111 +0,0 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_ZYNQMP=y
|
||||
CONFIG_SYS_TEXT_BASE=0x8000000
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x8000
|
||||
CONFIG_SPL=y
|
||||
CONFIG_DEBUG_UART_BASE=0xff000000
|
||||
CONFIG_DEBUG_UART_CLOCK=100000000
|
||||
CONFIG_IDENT_STRING=" Xilinx ZynqMP SC for Versal"
|
||||
CONFIG_SPL_SPI_FLASH_SUPPORT=y
|
||||
CONFIG_SPL_SPI_SUPPORT=y
|
||||
CONFIG_ZYNQMP_USB=y
|
||||
CONFIG_DEBUG_UART=y
|
||||
CONFIG_AHCI=y
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_SPL_LOAD_FIT=y
|
||||
# CONFIG_DISPLAY_CPUINFO is not set
|
||||
CONFIG_BOARD_EARLY_INIT_R=y
|
||||
CONFIG_SPL_OS_BOOT=y
|
||||
CONFIG_SPL_RAM_SUPPORT=y
|
||||
CONFIG_SPL_RAM_DEVICE=y
|
||||
CONFIG_SPL_ATF=y
|
||||
CONFIG_CMD_THOR_DOWNLOAD=y
|
||||
CONFIG_CMD_MEMTEST=y
|
||||
CONFIG_SYS_ALT_MEMTEST=y
|
||||
CONFIG_CMD_CLK=y
|
||||
CONFIG_CMD_DFU=y
|
||||
CONFIG_CMD_FPGA_LOADBP=y
|
||||
CONFIG_CMD_FPGA_LOADP=y
|
||||
CONFIG_CMD_FPGA_LOAD_SECURE=y
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_GPT=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_SDRAM=y
|
||||
CONFIG_CMD_USB=y
|
||||
CONFIG_CMD_TFTPPUT=y
|
||||
CONFIG_CMD_TIME=y
|
||||
CONFIG_CMD_TIMER=y
|
||||
CONFIG_CMD_EXT4_WRITE=y
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-g-a2197-00-revA"
|
||||
CONFIG_ENV_IS_IN_FAT=y
|
||||
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_SPL_DM=y
|
||||
CONFIG_SPL_DM_SEQ_ALIAS=y
|
||||
CONFIG_SCSI_AHCI=y
|
||||
CONFIG_SATA_CEVA=y
|
||||
CONFIG_CLK_ZYNQMP=y
|
||||
CONFIG_DFU_RAM=y
|
||||
CONFIG_USB_FUNCTION_FASTBOOT=y
|
||||
CONFIG_FASTBOOT_FLASH=y
|
||||
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
|
||||
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
|
||||
CONFIG_FPGA_XILINX=y
|
||||
CONFIG_FPGA_ZYNQMPPL=y
|
||||
CONFIG_DM_GPIO=y
|
||||
CONFIG_XILINX_GPIO=y
|
||||
CONFIG_DM_PCA953X=y
|
||||
CONFIG_DM_I2C=y
|
||||
CONFIG_SYS_I2C_CADENCE=y
|
||||
CONFIG_I2C_MUX=y
|
||||
CONFIG_I2C_MUX_PCA954x=y
|
||||
CONFIG_LED=y
|
||||
CONFIG_LED_GPIO=y
|
||||
CONFIG_MISC=y
|
||||
CONFIG_I2C_EEPROM=y
|
||||
CONFIG_SYS_I2C_EEPROM_ADDR=0x0
|
||||
CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0
|
||||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_ZYNQ=y
|
||||
CONFIG_SPI_FLASH_BAR=y
|
||||
CONFIG_SF_DUAL_FLASH=y
|
||||
CONFIG_SPI_FLASH_ISSI=y
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
|
||||
CONFIG_PHY_MARVELL=y
|
||||
CONFIG_PHY_NATSEMI=y
|
||||
CONFIG_PHY_REALTEK=y
|
||||
CONFIG_PHY_TI=y
|
||||
CONFIG_PHY_VITESSE=y
|
||||
CONFIG_PHY_FIXED=y
|
||||
CONFIG_PHY_GIGE=y
|
||||
CONFIG_MII=y
|
||||
CONFIG_ZYNQ_GEM=y
|
||||
CONFIG_SCSI=y
|
||||
CONFIG_DM_SCSI=y
|
||||
CONFIG_DEBUG_UART_ZYNQ=y
|
||||
CONFIG_DEBUG_UART_ANNOUNCE=y
|
||||
CONFIG_ZYNQ_SERIAL=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_ZYNQMP_GQSPI=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_XHCI_DWC3=y
|
||||
CONFIG_USB_DWC3=y
|
||||
CONFIG_USB_DWC3_GENERIC=y
|
||||
CONFIG_USB_ULPI_VIEWPORT=y
|
||||
CONFIG_USB_ULPI=y
|
||||
CONFIG_USB_GADGET=y
|
||||
CONFIG_USB_GADGET_MANUFACTURER="Xilinx"
|
||||
CONFIG_USB_GADGET_VENDOR_NUM=0x03FD
|
||||
CONFIG_USB_GADGET_PRODUCT_NUM=0x0300
|
||||
CONFIG_USB_FUNCTION_THOR=y
|
||||
CONFIG_SPL_GZIP=y
|
||||
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
|
||||
|
|
@ -1,111 +0,0 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_ZYNQMP=y
|
||||
CONFIG_SYS_TEXT_BASE=0x8000000
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x8000
|
||||
CONFIG_SPL=y
|
||||
CONFIG_DEBUG_UART_BASE=0xff000000
|
||||
CONFIG_DEBUG_UART_CLOCK=100000000
|
||||
CONFIG_IDENT_STRING=" Xilinx ZynqMP SC for Versal"
|
||||
CONFIG_SPL_SPI_FLASH_SUPPORT=y
|
||||
CONFIG_SPL_SPI_SUPPORT=y
|
||||
CONFIG_ZYNQMP_USB=y
|
||||
CONFIG_DEBUG_UART=y
|
||||
CONFIG_AHCI=y
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_SPL_LOAD_FIT=y
|
||||
# CONFIG_DISPLAY_CPUINFO is not set
|
||||
CONFIG_BOARD_EARLY_INIT_R=y
|
||||
CONFIG_SPL_OS_BOOT=y
|
||||
CONFIG_SPL_RAM_SUPPORT=y
|
||||
CONFIG_SPL_RAM_DEVICE=y
|
||||
CONFIG_SPL_ATF=y
|
||||
CONFIG_CMD_THOR_DOWNLOAD=y
|
||||
CONFIG_CMD_MEMTEST=y
|
||||
CONFIG_SYS_ALT_MEMTEST=y
|
||||
CONFIG_CMD_CLK=y
|
||||
CONFIG_CMD_DFU=y
|
||||
CONFIG_CMD_FPGA_LOADBP=y
|
||||
CONFIG_CMD_FPGA_LOADP=y
|
||||
CONFIG_CMD_FPGA_LOAD_SECURE=y
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_GPT=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_SDRAM=y
|
||||
CONFIG_CMD_USB=y
|
||||
CONFIG_CMD_TFTPPUT=y
|
||||
CONFIG_CMD_TIME=y
|
||||
CONFIG_CMD_TIMER=y
|
||||
CONFIG_CMD_EXT4_WRITE=y
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-m-a2197-01-revA"
|
||||
CONFIG_ENV_IS_IN_FAT=y
|
||||
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_SPL_DM=y
|
||||
CONFIG_SPL_DM_SEQ_ALIAS=y
|
||||
CONFIG_SCSI_AHCI=y
|
||||
CONFIG_SATA_CEVA=y
|
||||
CONFIG_CLK_ZYNQMP=y
|
||||
CONFIG_DFU_RAM=y
|
||||
CONFIG_USB_FUNCTION_FASTBOOT=y
|
||||
CONFIG_FASTBOOT_FLASH=y
|
||||
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
|
||||
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
|
||||
CONFIG_FPGA_XILINX=y
|
||||
CONFIG_FPGA_ZYNQMPPL=y
|
||||
CONFIG_DM_GPIO=y
|
||||
CONFIG_XILINX_GPIO=y
|
||||
CONFIG_DM_PCA953X=y
|
||||
CONFIG_DM_I2C=y
|
||||
CONFIG_SYS_I2C_CADENCE=y
|
||||
CONFIG_I2C_MUX=y
|
||||
CONFIG_I2C_MUX_PCA954x=y
|
||||
CONFIG_LED=y
|
||||
CONFIG_LED_GPIO=y
|
||||
CONFIG_MISC=y
|
||||
CONFIG_I2C_EEPROM=y
|
||||
CONFIG_SYS_I2C_EEPROM_ADDR=0x0
|
||||
CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0
|
||||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_ZYNQ=y
|
||||
CONFIG_SPI_FLASH_BAR=y
|
||||
CONFIG_SF_DUAL_FLASH=y
|
||||
CONFIG_SPI_FLASH_ISSI=y
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
|
||||
CONFIG_PHY_MARVELL=y
|
||||
CONFIG_PHY_NATSEMI=y
|
||||
CONFIG_PHY_REALTEK=y
|
||||
CONFIG_PHY_TI=y
|
||||
CONFIG_PHY_VITESSE=y
|
||||
CONFIG_PHY_FIXED=y
|
||||
CONFIG_PHY_GIGE=y
|
||||
CONFIG_MII=y
|
||||
CONFIG_ZYNQ_GEM=y
|
||||
CONFIG_SCSI=y
|
||||
CONFIG_DM_SCSI=y
|
||||
CONFIG_DEBUG_UART_ZYNQ=y
|
||||
CONFIG_DEBUG_UART_ANNOUNCE=y
|
||||
CONFIG_ZYNQ_SERIAL=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_ZYNQMP_GQSPI=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_XHCI_DWC3=y
|
||||
CONFIG_USB_DWC3=y
|
||||
CONFIG_USB_DWC3_GENERIC=y
|
||||
CONFIG_USB_ULPI_VIEWPORT=y
|
||||
CONFIG_USB_ULPI=y
|
||||
CONFIG_USB_GADGET=y
|
||||
CONFIG_USB_GADGET_MANUFACTURER="Xilinx"
|
||||
CONFIG_USB_GADGET_VENDOR_NUM=0x03FD
|
||||
CONFIG_USB_GADGET_PRODUCT_NUM=0x0300
|
||||
CONFIG_USB_FUNCTION_THOR=y
|
||||
CONFIG_SPL_GZIP=y
|
||||
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
|
||||
|
|
@ -1,111 +0,0 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_ZYNQMP=y
|
||||
CONFIG_SYS_TEXT_BASE=0x8000000
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x8000
|
||||
CONFIG_SPL=y
|
||||
CONFIG_DEBUG_UART_BASE=0xff000000
|
||||
CONFIG_DEBUG_UART_CLOCK=100000000
|
||||
CONFIG_IDENT_STRING=" Xilinx ZynqMP SC for Versal"
|
||||
CONFIG_SPL_SPI_FLASH_SUPPORT=y
|
||||
CONFIG_SPL_SPI_SUPPORT=y
|
||||
CONFIG_ZYNQMP_USB=y
|
||||
CONFIG_DEBUG_UART=y
|
||||
CONFIG_AHCI=y
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_SPL_LOAD_FIT=y
|
||||
# CONFIG_DISPLAY_CPUINFO is not set
|
||||
CONFIG_BOARD_EARLY_INIT_R=y
|
||||
CONFIG_SPL_OS_BOOT=y
|
||||
CONFIG_SPL_RAM_SUPPORT=y
|
||||
CONFIG_SPL_RAM_DEVICE=y
|
||||
CONFIG_SPL_ATF=y
|
||||
CONFIG_CMD_THOR_DOWNLOAD=y
|
||||
CONFIG_CMD_MEMTEST=y
|
||||
CONFIG_SYS_ALT_MEMTEST=y
|
||||
CONFIG_CMD_CLK=y
|
||||
CONFIG_CMD_DFU=y
|
||||
CONFIG_CMD_FPGA_LOADBP=y
|
||||
CONFIG_CMD_FPGA_LOADP=y
|
||||
CONFIG_CMD_FPGA_LOAD_SECURE=y
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_GPT=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_SDRAM=y
|
||||
CONFIG_CMD_USB=y
|
||||
CONFIG_CMD_TFTPPUT=y
|
||||
CONFIG_CMD_TIME=y
|
||||
CONFIG_CMD_TIMER=y
|
||||
CONFIG_CMD_EXT4_WRITE=y
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-m-a2197-02-revA"
|
||||
CONFIG_ENV_IS_IN_FAT=y
|
||||
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_SPL_DM=y
|
||||
CONFIG_SPL_DM_SEQ_ALIAS=y
|
||||
CONFIG_SCSI_AHCI=y
|
||||
CONFIG_SATA_CEVA=y
|
||||
CONFIG_CLK_ZYNQMP=y
|
||||
CONFIG_DFU_RAM=y
|
||||
CONFIG_USB_FUNCTION_FASTBOOT=y
|
||||
CONFIG_FASTBOOT_FLASH=y
|
||||
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
|
||||
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
|
||||
CONFIG_FPGA_XILINX=y
|
||||
CONFIG_FPGA_ZYNQMPPL=y
|
||||
CONFIG_DM_GPIO=y
|
||||
CONFIG_XILINX_GPIO=y
|
||||
CONFIG_DM_PCA953X=y
|
||||
CONFIG_DM_I2C=y
|
||||
CONFIG_SYS_I2C_CADENCE=y
|
||||
CONFIG_I2C_MUX=y
|
||||
CONFIG_I2C_MUX_PCA954x=y
|
||||
CONFIG_LED=y
|
||||
CONFIG_LED_GPIO=y
|
||||
CONFIG_MISC=y
|
||||
CONFIG_I2C_EEPROM=y
|
||||
CONFIG_SYS_I2C_EEPROM_ADDR=0x0
|
||||
CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0
|
||||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_ZYNQ=y
|
||||
CONFIG_SPI_FLASH_BAR=y
|
||||
CONFIG_SF_DUAL_FLASH=y
|
||||
CONFIG_SPI_FLASH_ISSI=y
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
|
||||
CONFIG_PHY_MARVELL=y
|
||||
CONFIG_PHY_NATSEMI=y
|
||||
CONFIG_PHY_REALTEK=y
|
||||
CONFIG_PHY_TI=y
|
||||
CONFIG_PHY_VITESSE=y
|
||||
CONFIG_PHY_FIXED=y
|
||||
CONFIG_PHY_GIGE=y
|
||||
CONFIG_MII=y
|
||||
CONFIG_ZYNQ_GEM=y
|
||||
CONFIG_SCSI=y
|
||||
CONFIG_DM_SCSI=y
|
||||
CONFIG_DEBUG_UART_ZYNQ=y
|
||||
CONFIG_DEBUG_UART_ANNOUNCE=y
|
||||
CONFIG_ZYNQ_SERIAL=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_ZYNQMP_GQSPI=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_XHCI_DWC3=y
|
||||
CONFIG_USB_DWC3=y
|
||||
CONFIG_USB_DWC3_GENERIC=y
|
||||
CONFIG_USB_ULPI_VIEWPORT=y
|
||||
CONFIG_USB_ULPI=y
|
||||
CONFIG_USB_GADGET=y
|
||||
CONFIG_USB_GADGET_MANUFACTURER="Xilinx"
|
||||
CONFIG_USB_GADGET_VENDOR_NUM=0x03FD
|
||||
CONFIG_USB_GADGET_PRODUCT_NUM=0x0300
|
||||
CONFIG_USB_FUNCTION_THOR=y
|
||||
CONFIG_SPL_GZIP=y
|
||||
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
|
||||
|
|
@ -1,111 +0,0 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_ZYNQMP=y
|
||||
CONFIG_SYS_TEXT_BASE=0x8000000
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x8000
|
||||
CONFIG_SPL=y
|
||||
CONFIG_DEBUG_UART_BASE=0xff000000
|
||||
CONFIG_DEBUG_UART_CLOCK=100000000
|
||||
CONFIG_IDENT_STRING=" Xilinx ZynqMP SC for Versal"
|
||||
CONFIG_SPL_SPI_FLASH_SUPPORT=y
|
||||
CONFIG_SPL_SPI_SUPPORT=y
|
||||
CONFIG_ZYNQMP_USB=y
|
||||
CONFIG_DEBUG_UART=y
|
||||
CONFIG_AHCI=y
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_SPL_LOAD_FIT=y
|
||||
# CONFIG_DISPLAY_CPUINFO is not set
|
||||
CONFIG_BOARD_EARLY_INIT_R=y
|
||||
CONFIG_SPL_OS_BOOT=y
|
||||
CONFIG_SPL_RAM_SUPPORT=y
|
||||
CONFIG_SPL_RAM_DEVICE=y
|
||||
CONFIG_SPL_ATF=y
|
||||
CONFIG_CMD_THOR_DOWNLOAD=y
|
||||
CONFIG_CMD_MEMTEST=y
|
||||
CONFIG_SYS_ALT_MEMTEST=y
|
||||
CONFIG_CMD_CLK=y
|
||||
CONFIG_CMD_DFU=y
|
||||
CONFIG_CMD_FPGA_LOADBP=y
|
||||
CONFIG_CMD_FPGA_LOADP=y
|
||||
CONFIG_CMD_FPGA_LOAD_SECURE=y
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_GPT=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_SDRAM=y
|
||||
CONFIG_CMD_USB=y
|
||||
CONFIG_CMD_TFTPPUT=y
|
||||
CONFIG_CMD_TIME=y
|
||||
CONFIG_CMD_TIMER=y
|
||||
CONFIG_CMD_EXT4_WRITE=y
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-m-a2197-03-revA"
|
||||
CONFIG_ENV_IS_IN_FAT=y
|
||||
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_SPL_DM=y
|
||||
CONFIG_SPL_DM_SEQ_ALIAS=y
|
||||
CONFIG_SCSI_AHCI=y
|
||||
CONFIG_SATA_CEVA=y
|
||||
CONFIG_CLK_ZYNQMP=y
|
||||
CONFIG_DFU_RAM=y
|
||||
CONFIG_USB_FUNCTION_FASTBOOT=y
|
||||
CONFIG_FASTBOOT_FLASH=y
|
||||
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
|
||||
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
|
||||
CONFIG_FPGA_XILINX=y
|
||||
CONFIG_FPGA_ZYNQMPPL=y
|
||||
CONFIG_DM_GPIO=y
|
||||
CONFIG_XILINX_GPIO=y
|
||||
CONFIG_DM_PCA953X=y
|
||||
CONFIG_DM_I2C=y
|
||||
CONFIG_SYS_I2C_CADENCE=y
|
||||
CONFIG_I2C_MUX=y
|
||||
CONFIG_I2C_MUX_PCA954x=y
|
||||
CONFIG_LED=y
|
||||
CONFIG_LED_GPIO=y
|
||||
CONFIG_MISC=y
|
||||
CONFIG_I2C_EEPROM=y
|
||||
CONFIG_SYS_I2C_EEPROM_ADDR=0x0
|
||||
CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0
|
||||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_ZYNQ=y
|
||||
CONFIG_SPI_FLASH_BAR=y
|
||||
CONFIG_SF_DUAL_FLASH=y
|
||||
CONFIG_SPI_FLASH_ISSI=y
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
|
||||
CONFIG_PHY_MARVELL=y
|
||||
CONFIG_PHY_NATSEMI=y
|
||||
CONFIG_PHY_REALTEK=y
|
||||
CONFIG_PHY_TI=y
|
||||
CONFIG_PHY_VITESSE=y
|
||||
CONFIG_PHY_FIXED=y
|
||||
CONFIG_PHY_GIGE=y
|
||||
CONFIG_MII=y
|
||||
CONFIG_ZYNQ_GEM=y
|
||||
CONFIG_SCSI=y
|
||||
CONFIG_DM_SCSI=y
|
||||
CONFIG_DEBUG_UART_ZYNQ=y
|
||||
CONFIG_DEBUG_UART_ANNOUNCE=y
|
||||
CONFIG_ZYNQ_SERIAL=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_ZYNQMP_GQSPI=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_XHCI_DWC3=y
|
||||
CONFIG_USB_DWC3=y
|
||||
CONFIG_USB_DWC3_GENERIC=y
|
||||
CONFIG_USB_ULPI_VIEWPORT=y
|
||||
CONFIG_USB_ULPI=y
|
||||
CONFIG_USB_GADGET=y
|
||||
CONFIG_USB_GADGET_MANUFACTURER="Xilinx"
|
||||
CONFIG_USB_GADGET_VENDOR_NUM=0x03FD
|
||||
CONFIG_USB_GADGET_PRODUCT_NUM=0x0300
|
||||
CONFIG_USB_FUNCTION_THOR=y
|
||||
CONFIG_SPL_GZIP=y
|
||||
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
|
||||
|
|
@ -49,4 +49,5 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
|||
# CONFIG_DM_WARN is not set
|
||||
# CONFIG_DM_DEVICE_REMOVE is not set
|
||||
# CONFIG_MMC is not set
|
||||
CONFIG_PANIC_HANG=y
|
||||
# CONFIG_EFI_LOADER is not set
|
||||
|
|
|
|||
|
|
@ -55,4 +55,5 @@ CONFIG_SPL_DM_SEQ_ALIAS=y
|
|||
CONFIG_SUPPORT_EMMC_BOOT=y
|
||||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_ZYNQ=y
|
||||
CONFIG_PANIC_HANG=y
|
||||
# CONFIG_EFI_LOADER is not set
|
||||
|
|
|
|||
|
|
@ -55,4 +55,5 @@ CONFIG_SPL_DM_SEQ_ALIAS=y
|
|||
CONFIG_SUPPORT_EMMC_BOOT=y
|
||||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_ZYNQ=y
|
||||
CONFIG_PANIC_HANG=y
|
||||
# CONFIG_EFI_LOADER is not set
|
||||
|
|
|
|||
|
|
@ -51,4 +51,5 @@ CONFIG_MTD=y
|
|||
CONFIG_MTD_RAW_NAND=y
|
||||
CONFIG_NAND_ARASAN=y
|
||||
CONFIG_SYS_NAND_MAX_CHIPS=2
|
||||
CONFIG_PANIC_HANG=y
|
||||
# CONFIG_EFI_LOADER is not set
|
||||
|
|
|
|||
|
|
@ -50,4 +50,5 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
|||
CONFIG_MTD=y
|
||||
CONFIG_MTD_RAW_NAND=y
|
||||
CONFIG_NAND_ARASAN=y
|
||||
CONFIG_PANIC_HANG=y
|
||||
# CONFIG_EFI_LOADER is not set
|
||||
|
|
|
|||
|
|
@ -62,4 +62,5 @@ CONFIG_SPI_FLASH_WINBOND=y
|
|||
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
|
||||
CONFIG_SPI=y
|
||||
CONFIG_ZYNQMP_GQSPI=y
|
||||
CONFIG_PANIC_HANG=y
|
||||
# CONFIG_EFI_LOADER is not set
|
||||
|
|
|
|||
|
|
@ -1,112 +0,0 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_ZYNQMP=y
|
||||
CONFIG_SYS_TEXT_BASE=0x8000000
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x8000
|
||||
CONFIG_SPL=y
|
||||
CONFIG_DEBUG_UART_BASE=0xff000000
|
||||
CONFIG_DEBUG_UART_CLOCK=100000000
|
||||
CONFIG_IDENT_STRING=" Xilinx ZynqMP SC for Versal"
|
||||
CONFIG_SPL_SPI_FLASH_SUPPORT=y
|
||||
CONFIG_SPL_SPI_SUPPORT=y
|
||||
CONFIG_ZYNQMP_USB=y
|
||||
CONFIG_SPL_ZYNQMP_TWO_SDHCI=y
|
||||
CONFIG_DEBUG_UART=y
|
||||
CONFIG_AHCI=y
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_SPL_LOAD_FIT=y
|
||||
# CONFIG_DISPLAY_CPUINFO is not set
|
||||
CONFIG_BOARD_EARLY_INIT_R=y
|
||||
CONFIG_SPL_OS_BOOT=y
|
||||
CONFIG_SPL_RAM_SUPPORT=y
|
||||
CONFIG_SPL_RAM_DEVICE=y
|
||||
CONFIG_SPL_ATF=y
|
||||
CONFIG_CMD_THOR_DOWNLOAD=y
|
||||
CONFIG_CMD_MEMTEST=y
|
||||
CONFIG_SYS_ALT_MEMTEST=y
|
||||
CONFIG_CMD_CLK=y
|
||||
CONFIG_CMD_DFU=y
|
||||
CONFIG_CMD_FPGA_LOADBP=y
|
||||
CONFIG_CMD_FPGA_LOADP=y
|
||||
CONFIG_CMD_FPGA_LOAD_SECURE=y
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_GPT=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_SDRAM=y
|
||||
CONFIG_CMD_USB=y
|
||||
CONFIG_CMD_TFTPPUT=y
|
||||
CONFIG_CMD_TIME=y
|
||||
CONFIG_CMD_TIMER=y
|
||||
CONFIG_CMD_EXT4_WRITE=y
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-p-a2197-00-revA"
|
||||
CONFIG_ENV_IS_IN_FAT=y
|
||||
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_SPL_DM=y
|
||||
CONFIG_SPL_DM_SEQ_ALIAS=y
|
||||
CONFIG_SCSI_AHCI=y
|
||||
CONFIG_SATA_CEVA=y
|
||||
CONFIG_CLK_ZYNQMP=y
|
||||
CONFIG_DFU_RAM=y
|
||||
CONFIG_USB_FUNCTION_FASTBOOT=y
|
||||
CONFIG_FASTBOOT_FLASH=y
|
||||
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
|
||||
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
|
||||
CONFIG_FPGA_XILINX=y
|
||||
CONFIG_FPGA_ZYNQMPPL=y
|
||||
CONFIG_DM_GPIO=y
|
||||
CONFIG_XILINX_GPIO=y
|
||||
CONFIG_DM_PCA953X=y
|
||||
CONFIG_DM_I2C=y
|
||||
CONFIG_SYS_I2C_CADENCE=y
|
||||
CONFIG_I2C_MUX=y
|
||||
CONFIG_I2C_MUX_PCA954x=y
|
||||
CONFIG_LED=y
|
||||
CONFIG_LED_GPIO=y
|
||||
CONFIG_MISC=y
|
||||
CONFIG_I2C_EEPROM=y
|
||||
CONFIG_SYS_I2C_EEPROM_ADDR=0x0
|
||||
CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0
|
||||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_ZYNQ=y
|
||||
CONFIG_SPI_FLASH_BAR=y
|
||||
CONFIG_SF_DUAL_FLASH=y
|
||||
CONFIG_SPI_FLASH_ISSI=y
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
|
||||
CONFIG_PHY_MARVELL=y
|
||||
CONFIG_PHY_NATSEMI=y
|
||||
CONFIG_PHY_REALTEK=y
|
||||
CONFIG_PHY_TI=y
|
||||
CONFIG_PHY_VITESSE=y
|
||||
CONFIG_PHY_FIXED=y
|
||||
CONFIG_PHY_GIGE=y
|
||||
CONFIG_MII=y
|
||||
CONFIG_ZYNQ_GEM=y
|
||||
CONFIG_SCSI=y
|
||||
CONFIG_DM_SCSI=y
|
||||
CONFIG_DEBUG_UART_ZYNQ=y
|
||||
CONFIG_DEBUG_UART_ANNOUNCE=y
|
||||
CONFIG_ZYNQ_SERIAL=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_ZYNQMP_GQSPI=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_XHCI_DWC3=y
|
||||
CONFIG_USB_DWC3=y
|
||||
CONFIG_USB_DWC3_GENERIC=y
|
||||
CONFIG_USB_ULPI_VIEWPORT=y
|
||||
CONFIG_USB_ULPI=y
|
||||
CONFIG_USB_GADGET=y
|
||||
CONFIG_USB_GADGET_MANUFACTURER="Xilinx"
|
||||
CONFIG_USB_GADGET_VENDOR_NUM=0x03FD
|
||||
CONFIG_USB_GADGET_PRODUCT_NUM=0x0300
|
||||
CONFIG_USB_FUNCTION_THOR=y
|
||||
CONFIG_SPL_GZIP=y
|
||||
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
|
||||
|
|
@ -1,4 +1,5 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_POSITION_INDEPENDENT=y
|
||||
CONFIG_ARCH_ZYNQMP=y
|
||||
CONFIG_SYS_TEXT_BASE=0x8000000
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x8000
|
||||
|
|
@ -16,10 +17,14 @@ CONFIG_BOARD_EARLY_INIT_R=y
|
|||
CONFIG_SPL_OS_BOOT=y
|
||||
CONFIG_SPL_RAM_SUPPORT=y
|
||||
CONFIG_SPL_RAM_DEVICE=y
|
||||
CONFIG_SPL_SPI_LOAD=y
|
||||
CONFIG_SPL_ATF=y
|
||||
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
|
||||
CONFIG_CMD_BOOTMENU=y
|
||||
CONFIG_CMD_THOR_DOWNLOAD=y
|
||||
CONFIG_CMD_MEMTEST=y
|
||||
CONFIG_SYS_ALT_MEMTEST=y
|
||||
CONFIG_CMD_BIND=y
|
||||
CONFIG_CMD_CLK=y
|
||||
CONFIG_CMD_DFU=y
|
||||
CONFIG_CMD_FPGA_LOADBP=y
|
||||
|
|
@ -29,15 +34,19 @@ CONFIG_CMD_GPIO=y
|
|||
CONFIG_CMD_GPT=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_NAND_LOCK_UNLOCK=y
|
||||
CONFIG_CMD_POWEROFF=y
|
||||
CONFIG_CMD_SDRAM=y
|
||||
CONFIG_CMD_SPI=y
|
||||
CONFIG_CMD_USB=y
|
||||
CONFIG_CMD_USB_MASS_STORAGE=y
|
||||
CONFIG_CMD_TFTPPUT=y
|
||||
CONFIG_CMD_TIME=y
|
||||
CONFIG_CMD_TIMER=y
|
||||
CONFIG_CMD_EXT4_WRITE=y
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
CONFIG_OF_BOARD=y
|
||||
CONFIG_ENV_IS_IN_FAT=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu100-revC"
|
||||
CONFIG_OF_LIST="avnet-ultra96-rev1 zynqmp-a2197-revA zynqmp-e-a2197-00-revA zynqmp-g-a2197-00-revA zynqmp-m-a2197-01-revA zynqmp-m-a2197-02-revA zynqmp-m-a2197-03-revA zynqmp-p-a2197-00-revA zynqmp-zc1232-revA zynqmp-zc1254-revA zynqmp-zc1751-xm015-dc1 zynqmp-zc1751-xm016-dc2 zynqmp-zc1751-xm017-dc3 zynqmp-zc1751-xm018-dc4 zynqmp-zc1751-xm019-dc5 zynqmp-zcu100-revC zynqmp-zcu102-rev1.0 zynqmp-zcu102-revA zynqmp-zcu102-revB zynqmp-zcu104-revA zynqmp-zcu104-revC zynqmp-zcu106-revA zynqmp-zcu111-revA zynqmp-zcu1275-revA zynqmp-zcu1275-revB zynqmp-zcu1285-revA zynqmp-zcu208-revA zynqmp-zcu216-revA"
|
||||
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_SPL_DM=y
|
||||
|
|
@ -53,7 +62,9 @@ CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
|
|||
CONFIG_FPGA_XILINX=y
|
||||
CONFIG_FPGA_ZYNQMPPL=y
|
||||
CONFIG_DM_GPIO=y
|
||||
CONFIG_GPIO_HOG=y
|
||||
CONFIG_XILINX_GPIO=y
|
||||
CONFIG_DM_PCA953X=y
|
||||
CONFIG_DM_I2C=y
|
||||
CONFIG_SYS_I2C_CADENCE=y
|
||||
CONFIG_I2C_MUX=y
|
||||
|
|
@ -65,29 +76,41 @@ CONFIG_I2C_EEPROM=y
|
|||
CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0x20
|
||||
CONFIG_SYS_I2C_EEPROM_ADDR=0x0
|
||||
CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0
|
||||
CONFIG_SUPPORT_EMMC_BOOT=y
|
||||
CONFIG_MMC_IO_VOLTAGE=y
|
||||
CONFIG_MMC_UHS_SUPPORT=y
|
||||
CONFIG_MMC_HS200_SUPPORT=y
|
||||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_ZYNQ=y
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_RAW_NAND=y
|
||||
CONFIG_NAND_ARASAN=y
|
||||
CONFIG_SYS_NAND_MAX_CHIPS=2
|
||||
CONFIG_SPI_FLASH_BAR=y
|
||||
CONFIG_SF_DUAL_FLASH=y
|
||||
CONFIG_SPI_FLASH_ISSI=y
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
CONFIG_SPI_FLASH_SST=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
|
||||
CONFIG_PHY_MARVELL=y
|
||||
CONFIG_PHY_MICREL=y
|
||||
CONFIG_PHY_MICREL_KSZ90X1=y
|
||||
CONFIG_PHY_NATSEMI=y
|
||||
CONFIG_PHY_REALTEK=y
|
||||
CONFIG_PHY_TI=y
|
||||
CONFIG_PHY_VITESSE=y
|
||||
CONFIG_PHY_XILINX_GMII2RGMII=y
|
||||
CONFIG_PHY_FIXED=y
|
||||
CONFIG_PHY_GIGE=y
|
||||
CONFIG_MII=y
|
||||
CONFIG_ZYNQ_GEM=y
|
||||
CONFIG_SCSI=y
|
||||
CONFIG_DM_SCSI=y
|
||||
CONFIG_ZYNQ_SERIAL=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_ZYNQ_SPI=y
|
||||
CONFIG_ZYNQMP_GQSPI=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_XHCI_HCD=y
|
||||
|
|
@ -101,4 +124,13 @@ CONFIG_USB_GADGET_MANUFACTURER="Xilinx"
|
|||
CONFIG_USB_GADGET_VENDOR_NUM=0x03FD
|
||||
CONFIG_USB_GADGET_PRODUCT_NUM=0x0300
|
||||
CONFIG_USB_FUNCTION_THOR=y
|
||||
CONFIG_USB_ETHER=y
|
||||
CONFIG_USB_ETH_CDC=y
|
||||
CONFIG_USB_HOST_ETHER=y
|
||||
CONFIG_USB_ETHER_ASIX=y
|
||||
CONFIG_WDT=y
|
||||
CONFIG_WDT_CDNS=y
|
||||
CONFIG_PANIC_HANG=y
|
||||
CONFIG_SPL_GZIP=y
|
||||
CONFIG_OF_LIBFDT_OVERLAY=y
|
||||
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
|
||||
|
|
|
|||
|
|
@ -1,49 +0,0 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_ZYNQMP=y
|
||||
CONFIG_SYS_TEXT_BASE=0x8000000
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x8000
|
||||
CONFIG_SPL=y
|
||||
CONFIG_DEBUG_UART_BASE=0xff000000
|
||||
CONFIG_DEBUG_UART_CLOCK=100000000
|
||||
# CONFIG_SPL_FS_FAT is not set
|
||||
# CONFIG_SPL_LIBDISK_SUPPORT is not set
|
||||
CONFIG_DEBUG_UART=y
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_SPL_LOAD_FIT=y
|
||||
# CONFIG_DISPLAY_CPUINFO is not set
|
||||
CONFIG_SPL_OS_BOOT=y
|
||||
CONFIG_SPL_RAM_SUPPORT=y
|
||||
CONFIG_SPL_RAM_DEVICE=y
|
||||
CONFIG_SPL_ATF=y
|
||||
CONFIG_CMD_MEMTEST=y
|
||||
CONFIG_CMD_CLK=y
|
||||
CONFIG_CMD_FPGA_LOADBP=y
|
||||
CONFIG_CMD_FPGA_LOADP=y
|
||||
CONFIG_CMD_FPGA_LOAD_SECURE=y
|
||||
# CONFIG_CMD_NET is not set
|
||||
CONFIG_CMD_TIME=y
|
||||
CONFIG_CMD_TIMER=y
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1232-revA"
|
||||
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
CONFIG_SPL_DM=y
|
||||
CONFIG_CLK_ZYNQMP=y
|
||||
CONFIG_FPGA_XILINX=y
|
||||
CONFIG_FPGA_ZYNQMPPL=y
|
||||
CONFIG_MISC=y
|
||||
# CONFIG_MMC is not set
|
||||
CONFIG_SPI_FLASH_BAR=y
|
||||
CONFIG_SPI_FLASH_ISSI=y
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
|
||||
CONFIG_DEBUG_UART_ZYNQ=y
|
||||
CONFIG_DEBUG_UART_ANNOUNCE=y
|
||||
CONFIG_ZYNQ_SERIAL=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_ZYNQMP_GQSPI=y
|
||||
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
|
||||
|
|
@ -1,49 +0,0 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_ZYNQMP=y
|
||||
CONFIG_SYS_TEXT_BASE=0x8000000
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x8000
|
||||
CONFIG_SPL=y
|
||||
CONFIG_DEBUG_UART_BASE=0xff000000
|
||||
CONFIG_DEBUG_UART_CLOCK=100000000
|
||||
# CONFIG_SPL_FS_FAT is not set
|
||||
# CONFIG_SPL_LIBDISK_SUPPORT is not set
|
||||
CONFIG_DEBUG_UART=y
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_SPL_LOAD_FIT=y
|
||||
# CONFIG_DISPLAY_CPUINFO is not set
|
||||
CONFIG_SPL_OS_BOOT=y
|
||||
CONFIG_SPL_RAM_SUPPORT=y
|
||||
CONFIG_SPL_RAM_DEVICE=y
|
||||
CONFIG_SPL_ATF=y
|
||||
CONFIG_CMD_MEMTEST=y
|
||||
CONFIG_CMD_CLK=y
|
||||
CONFIG_CMD_FPGA_LOADBP=y
|
||||
CONFIG_CMD_FPGA_LOADP=y
|
||||
CONFIG_CMD_FPGA_LOAD_SECURE=y
|
||||
# CONFIG_CMD_NET is not set
|
||||
CONFIG_CMD_TIME=y
|
||||
CONFIG_CMD_TIMER=y
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1254-revA"
|
||||
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
CONFIG_SPL_DM=y
|
||||
CONFIG_CLK_ZYNQMP=y
|
||||
CONFIG_FPGA_XILINX=y
|
||||
CONFIG_FPGA_ZYNQMPPL=y
|
||||
CONFIG_MISC=y
|
||||
# CONFIG_MMC is not set
|
||||
CONFIG_SPI_FLASH_BAR=y
|
||||
CONFIG_SPI_FLASH_ISSI=y
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
|
||||
CONFIG_DEBUG_UART_ZYNQ=y
|
||||
CONFIG_DEBUG_UART_ANNOUNCE=y
|
||||
CONFIG_ZYNQ_SERIAL=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_ZYNQMP_GQSPI=y
|
||||
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
|
||||
|
|
@ -1,95 +0,0 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_ZYNQMP=y
|
||||
CONFIG_SYS_TEXT_BASE=0x8000000
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x8000
|
||||
CONFIG_SPL=y
|
||||
CONFIG_DEBUG_UART_BASE=0xff000000
|
||||
CONFIG_DEBUG_UART_CLOCK=100000000
|
||||
CONFIG_ZYNQMP_USB=y
|
||||
CONFIG_SPL_ZYNQMP_TWO_SDHCI=y
|
||||
CONFIG_DEBUG_UART=y
|
||||
CONFIG_AHCI=y
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_SPL_LOAD_FIT=y
|
||||
# CONFIG_DISPLAY_CPUINFO is not set
|
||||
CONFIG_BOARD_EARLY_INIT_R=y
|
||||
CONFIG_SPL_OS_BOOT=y
|
||||
CONFIG_SPL_RAM_SUPPORT=y
|
||||
CONFIG_SPL_RAM_DEVICE=y
|
||||
CONFIG_SPL_ATF=y
|
||||
CONFIG_CMD_THOR_DOWNLOAD=y
|
||||
CONFIG_CMD_MEMTEST=y
|
||||
CONFIG_SYS_ALT_MEMTEST=y
|
||||
CONFIG_CMD_CLK=y
|
||||
CONFIG_CMD_DFU=y
|
||||
CONFIG_CMD_FPGA_LOADBP=y
|
||||
CONFIG_CMD_FPGA_LOADP=y
|
||||
CONFIG_CMD_FPGA_LOAD_SECURE=y
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_GPT=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_USB=y
|
||||
CONFIG_CMD_TFTPPUT=y
|
||||
CONFIG_CMD_TIME=y
|
||||
CONFIG_CMD_TIMER=y
|
||||
CONFIG_CMD_EXT4_WRITE=y
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm015-dc1"
|
||||
CONFIG_ENV_IS_IN_FAT=y
|
||||
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_SPL_DM=y
|
||||
CONFIG_SPL_DM_SEQ_ALIAS=y
|
||||
CONFIG_CLK_ZYNQMP=y
|
||||
CONFIG_DFU_RAM=y
|
||||
CONFIG_USB_FUNCTION_FASTBOOT=y
|
||||
CONFIG_FASTBOOT_FLASH=y
|
||||
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
|
||||
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
|
||||
CONFIG_FPGA_XILINX=y
|
||||
CONFIG_FPGA_ZYNQMPPL=y
|
||||
CONFIG_DM_GPIO=y
|
||||
CONFIG_DM_I2C=y
|
||||
CONFIG_SYS_I2C_CADENCE=y
|
||||
CONFIG_MISC=y
|
||||
CONFIG_SUPPORT_EMMC_BOOT=y
|
||||
CONFIG_MMC_HS200_SUPPORT=y
|
||||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_ZYNQ=y
|
||||
CONFIG_SPI_FLASH_BAR=y
|
||||
CONFIG_SPI_FLASH_ISSI=y
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
|
||||
CONFIG_PHY_MARVELL=y
|
||||
CONFIG_PHY_NATSEMI=y
|
||||
CONFIG_PHY_REALTEK=y
|
||||
CONFIG_PHY_TI=y
|
||||
CONFIG_PHY_VITESSE=y
|
||||
CONFIG_PHY_FIXED=y
|
||||
CONFIG_PHY_GIGE=y
|
||||
CONFIG_MII=y
|
||||
CONFIG_ZYNQ_GEM=y
|
||||
CONFIG_DEBUG_UART_ZYNQ=y
|
||||
CONFIG_DEBUG_UART_ANNOUNCE=y
|
||||
CONFIG_ZYNQ_SERIAL=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_ZYNQMP_GQSPI=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_XHCI_DWC3=y
|
||||
CONFIG_USB_DWC3=y
|
||||
CONFIG_USB_DWC3_GENERIC=y
|
||||
CONFIG_USB_ULPI_VIEWPORT=y
|
||||
CONFIG_USB_ULPI=y
|
||||
CONFIG_USB_GADGET=y
|
||||
CONFIG_USB_GADGET_MANUFACTURER="Xilinx"
|
||||
CONFIG_USB_GADGET_VENDOR_NUM=0x03FD
|
||||
CONFIG_USB_GADGET_PRODUCT_NUM=0x0300
|
||||
CONFIG_USB_FUNCTION_THOR=y
|
||||
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
|
||||
|
|
@ -1,87 +0,0 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_ZYNQMP=y
|
||||
CONFIG_SYS_TEXT_BASE=0x8000000
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x8000
|
||||
CONFIG_SPL=y
|
||||
CONFIG_DEBUG_UART_BASE=0xff000000
|
||||
CONFIG_DEBUG_UART_CLOCK=100000000
|
||||
# CONFIG_SPL_FS_FAT is not set
|
||||
# CONFIG_SPL_LIBDISK_SUPPORT is not set
|
||||
CONFIG_ZYNQMP_USB=y
|
||||
CONFIG_DEBUG_UART=y
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_SPL_LOAD_FIT=y
|
||||
# CONFIG_DISPLAY_CPUINFO is not set
|
||||
CONFIG_BOARD_EARLY_INIT_R=y
|
||||
CONFIG_SPL_OS_BOOT=y
|
||||
CONFIG_SPL_RAM_SUPPORT=y
|
||||
CONFIG_SPL_RAM_DEVICE=y
|
||||
CONFIG_SPL_ATF=y
|
||||
CONFIG_CMD_THOR_DOWNLOAD=y
|
||||
CONFIG_CMD_MEMTEST=y
|
||||
CONFIG_SYS_ALT_MEMTEST=y
|
||||
CONFIG_CMD_CLK=y
|
||||
CONFIG_CMD_DFU=y
|
||||
# CONFIG_CMD_FLASH is not set
|
||||
CONFIG_CMD_FPGA_LOADBP=y
|
||||
CONFIG_CMD_FPGA_LOADP=y
|
||||
CONFIG_CMD_FPGA_LOAD_SECURE=y
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_GPT=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_NAND_LOCK_UNLOCK=y
|
||||
CONFIG_CMD_USB=y
|
||||
CONFIG_CMD_TFTPPUT=y
|
||||
CONFIG_CMD_TIME=y
|
||||
CONFIG_CMD_TIMER=y
|
||||
CONFIG_CMD_EXT4_WRITE=y
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm016-dc2"
|
||||
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_SPL_DM=y
|
||||
CONFIG_SPL_DM_SEQ_ALIAS=y
|
||||
CONFIG_CLK_ZYNQMP=y
|
||||
CONFIG_DFU_RAM=y
|
||||
CONFIG_USB_FUNCTION_FASTBOOT=y
|
||||
CONFIG_FPGA_XILINX=y
|
||||
CONFIG_FPGA_ZYNQMPPL=y
|
||||
CONFIG_DM_GPIO=y
|
||||
CONFIG_DM_I2C=y
|
||||
CONFIG_SYS_I2C_CADENCE=y
|
||||
CONFIG_MISC=y
|
||||
# CONFIG_MMC is not set
|
||||
CONFIG_DM_MMC=y
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_RAW_NAND=y
|
||||
CONFIG_NAND_ARASAN=y
|
||||
CONFIG_SYS_NAND_MAX_CHIPS=2
|
||||
CONFIG_SPI_FLASH_SST=y
|
||||
CONFIG_PHY_MARVELL=y
|
||||
CONFIG_PHY_NATSEMI=y
|
||||
CONFIG_PHY_REALTEK=y
|
||||
CONFIG_PHY_TI=y
|
||||
CONFIG_PHY_VITESSE=y
|
||||
CONFIG_PHY_FIXED=y
|
||||
CONFIG_PHY_GIGE=y
|
||||
CONFIG_MII=y
|
||||
CONFIG_ZYNQ_GEM=y
|
||||
CONFIG_DEBUG_UART_ZYNQ=y
|
||||
CONFIG_DEBUG_UART_ANNOUNCE=y
|
||||
CONFIG_ZYNQ_SERIAL=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_XHCI_DWC3=y
|
||||
CONFIG_USB_DWC3=y
|
||||
CONFIG_USB_DWC3_GENERIC=y
|
||||
CONFIG_USB_ULPI_VIEWPORT=y
|
||||
CONFIG_USB_ULPI=y
|
||||
CONFIG_USB_GADGET=y
|
||||
CONFIG_USB_GADGET_MANUFACTURER="Xilinx"
|
||||
CONFIG_USB_GADGET_VENDOR_NUM=0x03FD
|
||||
CONFIG_USB_GADGET_PRODUCT_NUM=0x0300
|
||||
CONFIG_USB_FUNCTION_THOR=y
|
||||
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
|
||||
|
|
@ -1,82 +0,0 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_ZYNQMP=y
|
||||
CONFIG_SYS_TEXT_BASE=0x8000000
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x8000
|
||||
CONFIG_SPL=y
|
||||
CONFIG_DEBUG_UART_BASE=0xff010000
|
||||
CONFIG_DEBUG_UART_CLOCK=100000000
|
||||
CONFIG_ZYNQMP_USB=y
|
||||
CONFIG_DEBUG_UART=y
|
||||
CONFIG_AHCI=y
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_SPL_LOAD_FIT=y
|
||||
# CONFIG_DISPLAY_CPUINFO is not set
|
||||
CONFIG_SPL_OS_BOOT=y
|
||||
CONFIG_SPL_RAM_SUPPORT=y
|
||||
CONFIG_SPL_RAM_DEVICE=y
|
||||
CONFIG_SPL_ATF=y
|
||||
CONFIG_CMD_MEMTEST=y
|
||||
CONFIG_CMD_CLK=y
|
||||
CONFIG_CMD_DFU=y
|
||||
# CONFIG_CMD_FLASH is not set
|
||||
CONFIG_CMD_FPGA_LOADBP=y
|
||||
CONFIG_CMD_FPGA_LOADP=y
|
||||
CONFIG_CMD_FPGA_LOAD_SECURE=y
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_GPT=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_USB=y
|
||||
CONFIG_CMD_TFTPPUT=y
|
||||
CONFIG_CMD_TIME=y
|
||||
CONFIG_CMD_TIMER=y
|
||||
CONFIG_CMD_EXT4_WRITE=y
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm017-dc3"
|
||||
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_SPL_DM=y
|
||||
CONFIG_SPL_DM_SEQ_ALIAS=y
|
||||
CONFIG_SCSI_AHCI=y
|
||||
CONFIG_SATA_CEVA=y
|
||||
CONFIG_CLK_ZYNQMP=y
|
||||
CONFIG_DFU_RAM=y
|
||||
CONFIG_FPGA_XILINX=y
|
||||
CONFIG_FPGA_ZYNQMPPL=y
|
||||
CONFIG_DM_GPIO=y
|
||||
CONFIG_DM_I2C=y
|
||||
CONFIG_SYS_I2C_CADENCE=y
|
||||
CONFIG_MISC=y
|
||||
CONFIG_SUPPORT_EMMC_BOOT=y
|
||||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_ZYNQ=y
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_RAW_NAND=y
|
||||
CONFIG_NAND_ARASAN=y
|
||||
CONFIG_PHY_MARVELL=y
|
||||
CONFIG_PHY_NATSEMI=y
|
||||
CONFIG_PHY_REALTEK=y
|
||||
CONFIG_PHY_TI=y
|
||||
CONFIG_PHY_VITESSE=y
|
||||
CONFIG_PHY_FIXED=y
|
||||
CONFIG_PHY_GIGE=y
|
||||
CONFIG_MII=y
|
||||
CONFIG_ZYNQ_GEM=y
|
||||
CONFIG_SCSI=y
|
||||
CONFIG_DM_SCSI=y
|
||||
CONFIG_DEBUG_UART_ZYNQ=y
|
||||
CONFIG_DEBUG_UART_ANNOUNCE=y
|
||||
CONFIG_ZYNQ_SERIAL=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_XHCI_DWC3=y
|
||||
CONFIG_USB_DWC3=y
|
||||
CONFIG_USB_DWC3_GENERIC=y
|
||||
CONFIG_USB_ULPI_VIEWPORT=y
|
||||
CONFIG_USB_ULPI=y
|
||||
CONFIG_USB_GADGET=y
|
||||
CONFIG_USB_GADGET_DOWNLOAD=y
|
||||
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
|
||||
|
|
@ -1,67 +0,0 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_ZYNQMP=y
|
||||
CONFIG_SYS_TEXT_BASE=0x8000000
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x8000
|
||||
CONFIG_SPL=y
|
||||
CONFIG_DEBUG_UART_BASE=0xff000000
|
||||
CONFIG_DEBUG_UART_CLOCK=100000000
|
||||
CONFIG_DEBUG_UART=y
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_SPL_LOAD_FIT=y
|
||||
# CONFIG_DISPLAY_CPUINFO is not set
|
||||
CONFIG_BOARD_EARLY_INIT_R=y
|
||||
CONFIG_SPL_OS_BOOT=y
|
||||
CONFIG_SPL_RAM_SUPPORT=y
|
||||
CONFIG_SPL_RAM_DEVICE=y
|
||||
CONFIG_SPL_ATF=y
|
||||
CONFIG_CMD_MEMTEST=y
|
||||
CONFIG_SYS_ALT_MEMTEST=y
|
||||
CONFIG_CMD_CLK=y
|
||||
CONFIG_CMD_FPGA_LOADBP=y
|
||||
CONFIG_CMD_FPGA_LOADP=y
|
||||
CONFIG_CMD_FPGA_LOAD_SECURE=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_TFTPPUT=y
|
||||
CONFIG_CMD_TIME=y
|
||||
CONFIG_CMD_TIMER=y
|
||||
CONFIG_CMD_EXT4_WRITE=y
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm018-dc4"
|
||||
CONFIG_ENV_IS_IN_FAT=y
|
||||
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_SPL_DM=y
|
||||
CONFIG_SPL_DM_SEQ_ALIAS=y
|
||||
CONFIG_CLK_ZYNQMP=y
|
||||
CONFIG_FPGA_XILINX=y
|
||||
CONFIG_FPGA_ZYNQMPPL=y
|
||||
CONFIG_DM_GPIO=y
|
||||
CONFIG_DM_I2C=y
|
||||
CONFIG_SYS_I2C_CADENCE=y
|
||||
CONFIG_MISC=y
|
||||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_ZYNQ=y
|
||||
CONFIG_SPI_FLASH_BAR=y
|
||||
CONFIG_SPI_FLASH_ISSI=y
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
|
||||
CONFIG_PHY_MARVELL=y
|
||||
CONFIG_PHY_NATSEMI=y
|
||||
CONFIG_PHY_REALTEK=y
|
||||
CONFIG_PHY_TI=y
|
||||
CONFIG_PHY_VITESSE=y
|
||||
CONFIG_PHY_FIXED=y
|
||||
CONFIG_PHY_GIGE=y
|
||||
CONFIG_MII=y
|
||||
CONFIG_ZYNQ_GEM=y
|
||||
CONFIG_DEBUG_UART_ZYNQ=y
|
||||
CONFIG_DEBUG_UART_ANNOUNCE=y
|
||||
CONFIG_ZYNQ_SERIAL=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_ZYNQMP_GQSPI=y
|
||||
|
|
@ -1,60 +0,0 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_ZYNQMP=y
|
||||
CONFIG_SYS_TEXT_BASE=0x8000000
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x8000
|
||||
CONFIG_SPL=y
|
||||
CONFIG_DEBUG_UART_BASE=0xff000000
|
||||
CONFIG_DEBUG_UART_CLOCK=100000000
|
||||
CONFIG_DEBUG_UART=y
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_SPL_LOAD_FIT=y
|
||||
# CONFIG_DISPLAY_CPUINFO is not set
|
||||
CONFIG_BOARD_EARLY_INIT_R=y
|
||||
CONFIG_SPL_OS_BOOT=y
|
||||
CONFIG_SPL_RAM_SUPPORT=y
|
||||
CONFIG_SPL_RAM_DEVICE=y
|
||||
CONFIG_SPL_ATF=y
|
||||
CONFIG_CMD_MEMTEST=y
|
||||
CONFIG_SYS_ALT_MEMTEST=y
|
||||
CONFIG_CMD_CLK=y
|
||||
CONFIG_CMD_FPGA_LOADBP=y
|
||||
CONFIG_CMD_FPGA_LOADP=y
|
||||
CONFIG_CMD_FPGA_LOAD_SECURE=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_TFTPPUT=y
|
||||
CONFIG_CMD_TIME=y
|
||||
CONFIG_CMD_TIMER=y
|
||||
CONFIG_CMD_EXT4_WRITE=y
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm019-dc5"
|
||||
CONFIG_ENV_IS_IN_FAT=y
|
||||
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_SPL_DM=y
|
||||
CONFIG_SPL_DM_SEQ_ALIAS=y
|
||||
CONFIG_CLK_ZYNQMP=y
|
||||
CONFIG_FPGA_XILINX=y
|
||||
CONFIG_FPGA_ZYNQMPPL=y
|
||||
CONFIG_DM_GPIO=y
|
||||
CONFIG_DM_I2C=y
|
||||
CONFIG_SYS_I2C_CADENCE=y
|
||||
CONFIG_MISC=y
|
||||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_ZYNQ=y
|
||||
CONFIG_PHY_MARVELL=y
|
||||
CONFIG_PHY_NATSEMI=y
|
||||
CONFIG_PHY_REALTEK=y
|
||||
CONFIG_PHY_TI=y
|
||||
CONFIG_PHY_VITESSE=y
|
||||
CONFIG_PHY_FIXED=y
|
||||
CONFIG_PHY_GIGE=y
|
||||
CONFIG_MII=y
|
||||
CONFIG_ZYNQ_GEM=y
|
||||
CONFIG_DEBUG_UART_ZYNQ=y
|
||||
CONFIG_DEBUG_UART_ANNOUNCE=y
|
||||
CONFIG_ZYNQ_SERIAL=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
|
||||
|
|
@ -1,87 +0,0 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_ZYNQMP=y
|
||||
CONFIG_SYS_TEXT_BASE=0x8000000
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x8000
|
||||
CONFIG_SPL=y
|
||||
CONFIG_DEBUG_UART_BASE=0xff010000
|
||||
CONFIG_DEBUG_UART_CLOCK=100000000
|
||||
CONFIG_ZYNQ_SDHCI_MAX_FREQ=15000000
|
||||
CONFIG_ZYNQMP_USB=y
|
||||
CONFIG_DEBUG_UART=y
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_SPL_LOAD_FIT=y
|
||||
# CONFIG_DISPLAY_CPUINFO is not set
|
||||
CONFIG_SPL_OS_BOOT=y
|
||||
CONFIG_SPL_RAM_SUPPORT=y
|
||||
CONFIG_SPL_RAM_DEVICE=y
|
||||
CONFIG_SPL_ATF=y
|
||||
CONFIG_CMD_BOOTMENU=y
|
||||
CONFIG_CMD_MEMTEST=y
|
||||
CONFIG_CMD_BIND=y
|
||||
CONFIG_CMD_CLK=y
|
||||
CONFIG_CMD_DFU=y
|
||||
CONFIG_CMD_FPGA_LOADBP=y
|
||||
CONFIG_CMD_FPGA_LOADP=y
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_POWEROFF=y
|
||||
CONFIG_CMD_SPI=y
|
||||
CONFIG_CMD_USB=y
|
||||
CONFIG_CMD_USB_MASS_STORAGE=y
|
||||
CONFIG_CMD_TFTPPUT=y
|
||||
CONFIG_CMD_TIME=y
|
||||
CONFIG_CMD_TIMER=y
|
||||
CONFIG_CMD_EXT4_WRITE=y
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu100-revC"
|
||||
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_SPL_DM=y
|
||||
CONFIG_SPL_DM_SEQ_ALIAS=y
|
||||
CONFIG_CLK_ZYNQMP=y
|
||||
CONFIG_DFU_RAM=y
|
||||
CONFIG_FPGA_XILINX=y
|
||||
CONFIG_FPGA_ZYNQMPPL=y
|
||||
CONFIG_DM_GPIO=y
|
||||
CONFIG_XILINX_GPIO=y
|
||||
CONFIG_DM_I2C=y
|
||||
CONFIG_SYS_I2C_CADENCE=y
|
||||
CONFIG_I2C_MUX=y
|
||||
CONFIG_I2C_MUX_PCA954x=y
|
||||
CONFIG_LED=y
|
||||
CONFIG_LED_GPIO=y
|
||||
CONFIG_MISC=y
|
||||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_ZYNQ=y
|
||||
CONFIG_SPI_FLASH_BAR=y
|
||||
CONFIG_SPI_FLASH_ISSI=y
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
|
||||
# CONFIG_NETDEVICES is not set
|
||||
CONFIG_DEBUG_UART_ZYNQ=y
|
||||
CONFIG_DEBUG_UART_ANNOUNCE=y
|
||||
CONFIG_ZYNQ_SERIAL=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_ZYNQ_SPI=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_XHCI_DWC3=y
|
||||
CONFIG_USB_DWC3=y
|
||||
CONFIG_USB_DWC3_GENERIC=y
|
||||
CONFIG_USB_ULPI_VIEWPORT=y
|
||||
CONFIG_USB_ULPI=y
|
||||
CONFIG_USB_GADGET=y
|
||||
CONFIG_USB_GADGET_DOWNLOAD=y
|
||||
CONFIG_USB_ETHER=y
|
||||
CONFIG_USB_ETH_CDC=y
|
||||
CONFIG_USB_HOST_ETHER=y
|
||||
CONFIG_USB_ETHER_ASIX=y
|
||||
CONFIG_SPL_GZIP=y
|
||||
CONFIG_OF_LIBFDT_OVERLAY=y
|
||||
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
|
||||
|
|
@ -1,111 +0,0 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_ZYNQMP=y
|
||||
CONFIG_SYS_TEXT_BASE=0x8000000
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x8000
|
||||
CONFIG_SPL=y
|
||||
CONFIG_DEBUG_UART_BASE=0xff000000
|
||||
CONFIG_DEBUG_UART_CLOCK=100000000
|
||||
CONFIG_SPL_SPI_FLASH_SUPPORT=y
|
||||
CONFIG_SPL_SPI_SUPPORT=y
|
||||
CONFIG_ZYNQMP_USB=y
|
||||
CONFIG_DEBUG_UART=y
|
||||
CONFIG_AHCI=y
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_SPL_LOAD_FIT=y
|
||||
# CONFIG_DISPLAY_CPUINFO is not set
|
||||
CONFIG_BOARD_EARLY_INIT_R=y
|
||||
CONFIG_SPL_OS_BOOT=y
|
||||
CONFIG_SPL_RAM_SUPPORT=y
|
||||
CONFIG_SPL_RAM_DEVICE=y
|
||||
CONFIG_SPL_ATF=y
|
||||
CONFIG_CMD_THOR_DOWNLOAD=y
|
||||
CONFIG_CMD_MEMTEST=y
|
||||
CONFIG_SYS_ALT_MEMTEST=y
|
||||
CONFIG_CMD_CLK=y
|
||||
CONFIG_CMD_DFU=y
|
||||
CONFIG_CMD_FPGA_LOADBP=y
|
||||
CONFIG_CMD_FPGA_LOADP=y
|
||||
CONFIG_CMD_FPGA_LOAD_SECURE=y
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_GPT=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_SDRAM=y
|
||||
CONFIG_CMD_USB=y
|
||||
CONFIG_CMD_TFTPPUT=y
|
||||
CONFIG_CMD_TIME=y
|
||||
CONFIG_CMD_TIMER=y
|
||||
CONFIG_CMD_EXT4_WRITE=y
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu102-rev1.0"
|
||||
CONFIG_ENV_IS_IN_FAT=y
|
||||
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_SPL_DM=y
|
||||
CONFIG_SPL_DM_SEQ_ALIAS=y
|
||||
CONFIG_SCSI_AHCI=y
|
||||
CONFIG_SATA_CEVA=y
|
||||
CONFIG_CLK_ZYNQMP=y
|
||||
CONFIG_DFU_RAM=y
|
||||
CONFIG_USB_FUNCTION_FASTBOOT=y
|
||||
CONFIG_FASTBOOT_FLASH=y
|
||||
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
|
||||
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
|
||||
CONFIG_FPGA_XILINX=y
|
||||
CONFIG_FPGA_ZYNQMPPL=y
|
||||
CONFIG_DM_GPIO=y
|
||||
CONFIG_GPIO_HOG=y
|
||||
CONFIG_XILINX_GPIO=y
|
||||
CONFIG_DM_I2C=y
|
||||
CONFIG_SYS_I2C_CADENCE=y
|
||||
CONFIG_I2C_MUX=y
|
||||
CONFIG_I2C_MUX_PCA954x=y
|
||||
CONFIG_LED=y
|
||||
CONFIG_LED_GPIO=y
|
||||
CONFIG_MISC=y
|
||||
CONFIG_I2C_EEPROM=y
|
||||
CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0x20
|
||||
CONFIG_SYS_I2C_EEPROM_ADDR=0x0
|
||||
CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0
|
||||
CONFIG_MMC_IO_VOLTAGE=y
|
||||
CONFIG_MMC_UHS_SUPPORT=y
|
||||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_ZYNQ=y
|
||||
CONFIG_SPI_FLASH_BAR=y
|
||||
CONFIG_SPI_FLASH_ISSI=y
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
|
||||
CONFIG_PHY_MARVELL=y
|
||||
CONFIG_PHY_NATSEMI=y
|
||||
CONFIG_PHY_REALTEK=y
|
||||
CONFIG_PHY_TI=y
|
||||
CONFIG_PHY_VITESSE=y
|
||||
CONFIG_PHY_FIXED=y
|
||||
CONFIG_PHY_GIGE=y
|
||||
CONFIG_MII=y
|
||||
CONFIG_ZYNQ_GEM=y
|
||||
CONFIG_SCSI=y
|
||||
CONFIG_DM_SCSI=y
|
||||
CONFIG_DEBUG_UART_ZYNQ=y
|
||||
CONFIG_DEBUG_UART_ANNOUNCE=y
|
||||
CONFIG_ZYNQ_SERIAL=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_ZYNQMP_GQSPI=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_XHCI_DWC3=y
|
||||
CONFIG_USB_DWC3=y
|
||||
CONFIG_USB_DWC3_GENERIC=y
|
||||
CONFIG_USB_ULPI_VIEWPORT=y
|
||||
CONFIG_USB_ULPI=y
|
||||
CONFIG_USB_GADGET=y
|
||||
CONFIG_USB_GADGET_MANUFACTURER="Xilinx"
|
||||
CONFIG_USB_GADGET_VENDOR_NUM=0x03FD
|
||||
CONFIG_USB_GADGET_PRODUCT_NUM=0x0300
|
||||
CONFIG_USB_FUNCTION_THOR=y
|
||||
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
|
||||
|
|
@ -1,111 +0,0 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_ZYNQMP=y
|
||||
CONFIG_SYS_TEXT_BASE=0x8000000
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x8000
|
||||
CONFIG_SPL=y
|
||||
CONFIG_DEBUG_UART_BASE=0xff000000
|
||||
CONFIG_DEBUG_UART_CLOCK=100000000
|
||||
CONFIG_SPL_SPI_FLASH_SUPPORT=y
|
||||
CONFIG_SPL_SPI_SUPPORT=y
|
||||
CONFIG_ZYNQMP_USB=y
|
||||
CONFIG_DEBUG_UART=y
|
||||
CONFIG_AHCI=y
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_SPL_LOAD_FIT=y
|
||||
# CONFIG_DISPLAY_CPUINFO is not set
|
||||
CONFIG_BOARD_EARLY_INIT_R=y
|
||||
CONFIG_SPL_OS_BOOT=y
|
||||
CONFIG_SPL_RAM_SUPPORT=y
|
||||
CONFIG_SPL_RAM_DEVICE=y
|
||||
CONFIG_SPL_ATF=y
|
||||
CONFIG_CMD_THOR_DOWNLOAD=y
|
||||
CONFIG_CMD_MEMTEST=y
|
||||
CONFIG_SYS_ALT_MEMTEST=y
|
||||
CONFIG_CMD_CLK=y
|
||||
CONFIG_CMD_DFU=y
|
||||
CONFIG_CMD_FPGA_LOADBP=y
|
||||
CONFIG_CMD_FPGA_LOADP=y
|
||||
CONFIG_CMD_FPGA_LOAD_SECURE=y
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_GPT=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_SDRAM=y
|
||||
CONFIG_CMD_USB=y
|
||||
CONFIG_CMD_TFTPPUT=y
|
||||
CONFIG_CMD_TIME=y
|
||||
CONFIG_CMD_TIMER=y
|
||||
CONFIG_CMD_EXT4_WRITE=y
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu102-revA"
|
||||
CONFIG_ENV_IS_IN_FAT=y
|
||||
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_SPL_DM=y
|
||||
CONFIG_SPL_DM_SEQ_ALIAS=y
|
||||
CONFIG_SCSI_AHCI=y
|
||||
CONFIG_SATA_CEVA=y
|
||||
CONFIG_CLK_ZYNQMP=y
|
||||
CONFIG_DFU_RAM=y
|
||||
CONFIG_USB_FUNCTION_FASTBOOT=y
|
||||
CONFIG_FASTBOOT_FLASH=y
|
||||
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
|
||||
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
|
||||
CONFIG_FPGA_XILINX=y
|
||||
CONFIG_FPGA_ZYNQMPPL=y
|
||||
CONFIG_DM_GPIO=y
|
||||
CONFIG_GPIO_HOG=y
|
||||
CONFIG_XILINX_GPIO=y
|
||||
CONFIG_DM_PCA953X=y
|
||||
CONFIG_DM_I2C=y
|
||||
CONFIG_SYS_I2C_CADENCE=y
|
||||
CONFIG_I2C_MUX=y
|
||||
CONFIG_I2C_MUX_PCA954x=y
|
||||
CONFIG_LED=y
|
||||
CONFIG_LED_GPIO=y
|
||||
CONFIG_MISC=y
|
||||
CONFIG_I2C_EEPROM=y
|
||||
CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0x20
|
||||
CONFIG_SYS_I2C_EEPROM_ADDR=0x0
|
||||
CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0
|
||||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_ZYNQ=y
|
||||
CONFIG_SPI_FLASH_BAR=y
|
||||
CONFIG_SPI_FLASH_ISSI=y
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
|
||||
CONFIG_PHY_MARVELL=y
|
||||
CONFIG_PHY_NATSEMI=y
|
||||
CONFIG_PHY_REALTEK=y
|
||||
CONFIG_PHY_TI=y
|
||||
CONFIG_PHY_VITESSE=y
|
||||
CONFIG_PHY_FIXED=y
|
||||
CONFIG_PHY_GIGE=y
|
||||
CONFIG_MII=y
|
||||
CONFIG_ZYNQ_GEM=y
|
||||
CONFIG_SCSI=y
|
||||
CONFIG_DM_SCSI=y
|
||||
CONFIG_DEBUG_UART_ZYNQ=y
|
||||
CONFIG_DEBUG_UART_ANNOUNCE=y
|
||||
CONFIG_ZYNQ_SERIAL=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_ZYNQMP_GQSPI=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_XHCI_DWC3=y
|
||||
CONFIG_USB_DWC3=y
|
||||
CONFIG_USB_DWC3_GENERIC=y
|
||||
CONFIG_USB_ULPI_VIEWPORT=y
|
||||
CONFIG_USB_ULPI=y
|
||||
CONFIG_USB_GADGET=y
|
||||
CONFIG_USB_GADGET_MANUFACTURER="Xilinx"
|
||||
CONFIG_USB_GADGET_VENDOR_NUM=0x03FD
|
||||
CONFIG_USB_GADGET_PRODUCT_NUM=0x0300
|
||||
CONFIG_USB_FUNCTION_THOR=y
|
||||
CONFIG_SPL_GZIP=y
|
||||
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
|
||||
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Add table
Reference in a new issue