From a1337e3581b74b62397767b5a8d8ff148ccb97c1 Mon Sep 17 00:00:00 2001 From: Parthiban Nallathambi Date: Fri, 23 Oct 2020 16:23:49 +0200 Subject: [PATCH 01/10] ARM: am335x: Add phyBOARD REGOR support phyBOARD-REGOR is based on phyCORE AM335x R2 SoM (PCL060). CPU : AM335X-GP rev 2.1 Model: Phytec AM335x phyBOARD-REGOR DRAM: 512 MiB NAND: 512 MiB MMC: OMAP SD/MMC: 0 eth0: ethernet@4a100000 Working: - Eth0 - i2C - MMC/SD - NAND - UART - USB (host) Device trees were taken from Linux mainline: commit c4d6fe731176 ("Linux 5.9.0") Signed-off-by: Parthiban Nallathambi Reviewed-by: Tom Rini --- arch/arm/dts/Makefile | 3 +- arch/arm/dts/am335x-regor-rdk-u-boot.dtsi | 31 ++++ arch/arm/dts/am335x-regor-rdk.dts | 24 +++ arch/arm/dts/am335x-regor.dtsi | 202 +++++++++++++++++++++ board/phytec/phycore_am335x_r2/MAINTAINERS | 6 +- configs/phycore-am335x-r2-regor_defconfig | 88 +++++++++ 6 files changed, 352 insertions(+), 2 deletions(-) create mode 100644 arch/arm/dts/am335x-regor-rdk-u-boot.dtsi create mode 100644 arch/arm/dts/am335x-regor-rdk.dts create mode 100644 arch/arm/dts/am335x-regor.dtsi create mode 100644 configs/phycore-am335x-r2-regor_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 5308713df7..43192073bf 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -350,7 +350,8 @@ dtb-$(CONFIG_AM33XX) += \ am335x-sl50.dtb \ am335x-base0033.dtb \ am335x-guardian.dtb \ - am335x-wega-rdk.dtb + am335x-wega-rdk.dtb \ + am335x-regor-rdk.dtb dtb-$(CONFIG_AM43XX) += am437x-gp-evm.dtb am437x-sk-evm.dtb \ am43x-epos-evm.dtb \ am437x-idk-evm.dtb \ diff --git a/arch/arm/dts/am335x-regor-rdk-u-boot.dtsi b/arch/arm/dts/am335x-regor-rdk-u-boot.dtsi new file mode 100644 index 0000000000..1ddd715875 --- /dev/null +++ b/arch/arm/dts/am335x-regor-rdk-u-boot.dtsi @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2020 Linumiz + */ + +/ { + chosen { + #address-cells = <1>; + #size-cells = <1>; + + bootargs = "console=ttyO0,115200 earlyprintk"; + stdout-path = &uart0; + }; + + ocp { + u-boot,dm-pre-reloc; + }; +}; + +&i2c0 { + u-boot,dm-pre-reloc; +}; + +&uart0 { + u-boot,dm-pre-reloc; +}; + +&mmc1 { + u-boot,dm-pre-reloc; + cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; +}; diff --git a/arch/arm/dts/am335x-regor-rdk.dts b/arch/arm/dts/am335x-regor-rdk.dts new file mode 100644 index 0000000000..66a1360b83 --- /dev/null +++ b/arch/arm/dts/am335x-regor-rdk.dts @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 Phytec Messtechnik GmbH + * Author: Teresa Remmet + * + */ + +/dts-v1/; + +#include "am335x-phycore-som.dtsi" +#include "am335x-regor.dtsi" + +/* SoM */ +&gpmc { + status = "okay"; +}; + +&i2c_eeprom { + status = "okay"; +}; + +&serial_flash { + status = "okay"; +}; diff --git a/arch/arm/dts/am335x-regor.dtsi b/arch/arm/dts/am335x-regor.dtsi new file mode 100644 index 0000000000..86b3f07429 --- /dev/null +++ b/arch/arm/dts/am335x-regor.dtsi @@ -0,0 +1,202 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 Phytec Messtechnik GmbH + * Author: Teresa Remmet + * + */ + +/ { + model = "Phytec AM335x phyBOARD-REGOR"; + compatible = "phytec,am335x-regor", "phytec,am335x-phycore-som", "ti,am33xx"; + + vcc3v3: fixedregulator@1 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + }; + + /* User IO */ + user_leds: user_leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&user_leds_pins>; + + run_stop-led { + gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "gpio"; + default-state = "off"; + }; + + error-led { + gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "gpio"; + default-state = "off"; + }; + }; +}; + +/* User Leds */ +&am33xx_pinmux { + user_leds_pins: pinmux_user_leds { + pinctrl-single,pins = < + AM33XX_IOPAD(0x8E0, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* lcd_hsync.gpio2_22 */ + AM33XX_IOPAD(0x994, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* mcasp0_fsx.gpio3_15 */ + >; + }; +}; + +/* CAN Busses */ +&am33xx_pinmux { + dcan1_pins: pinmux_dcan1 { + pinctrl-single,pins = < + AM33XX_IOPAD(0x968, PIN_OUTPUT_PULLUP | MUX_MODE2) /* uart0_ctsn.d_can1_tx */ + AM33XX_IOPAD(0x96C, PIN_INPUT_PULLUP | MUX_MODE2) /* uart0_rtsn.d_can1_rx */ + >; + }; +}; + +&dcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&dcan1_pins>; + status = "okay"; +}; + +/* Ethernet */ +&am33xx_pinmux { + ethernet1_pins: pinmux_ethernet1 { + pinctrl-single,pins = < + AM33XX_IOPAD(0x840, PIN_OUTPUT | MUX_MODE1) /* gpmc_a0.mii2_txen */ + AM33XX_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a1.mii2_rxdv */ + AM33XX_IOPAD(0x848, PIN_OUTPUT | MUX_MODE1) /* gpmc_a2.mii2_txd3 */ + AM33XX_IOPAD(0x84C, PIN_OUTPUT | MUX_MODE1) /* gpmc_a3.mii2_txd2 */ + AM33XX_IOPAD(0x850, PIN_OUTPUT | MUX_MODE1) /* gpmc_a4.mii2_txd1 */ + AM33XX_IOPAD(0x854, PIN_OUTPUT | MUX_MODE1) /* gpmc_a5.mii2_txd0 */ + AM33XX_IOPAD(0x858, PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a6.mii2_txclk */ + AM33XX_IOPAD(0x85C, PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a7.mii2_rxclk */ + AM33XX_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a8.mii2_rxd3 */ + AM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a9.mii2_rxd2 */ + AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a10.mii2_rxd1 */ + AM33XX_IOPAD(0x86C, PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a11.mii2_rxd0 */ + AM33XX_IOPAD(0x874, PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_wpn.mii2_rxerr */ + AM33XX_IOPAD(0x878, PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_ben1.mii2_col */ + >; + }; +}; + +&cpsw_emac1 { + phy-handle = <&phy1>; + phy-mode = "mii"; + dual_emac_res_vlan = <2>; +}; + +&davinci_mdio { + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; + +&mac { + slaves = <2>; + pinctrl-names = "default"; + pinctrl-0 = <ðernet0_pins ðernet1_pins>; + dual_emac = <1>; +}; + +/* GPIOs */ +&am33xx_pinmux { + pinctrl-names = "default"; + pinctrl-0 = <&user_gpios_pins>; + + user_gpios_pins: pinmux_user_gpios { + pinctrl-single,pins = < + /* DIGIN 1-4 */ + AM33XX_IOPAD(0x82C, PIN_INPUT | MUX_MODE7) /* gpmc_ad11.gpio0_27 */ + AM33XX_IOPAD(0x828, PIN_INPUT | MUX_MODE7) /* gpmc_ad10.gpio0_26 */ + AM33XX_IOPAD(0x824, PIN_INPUT | MUX_MODE7) /* gpmc_ad9.gpio0_23 */ + AM33XX_IOPAD(0x820, PIN_INPUT | MUX_MODE7) /* gpmc_ad8.gpio0_22 */ + /* DIGOUT 1-4 */ + AM33XX_IOPAD(0x83C, PIN_OUTPUT | MUX_MODE7) /* gpmc_ad15.gpio1_15 */ + AM33XX_IOPAD(0x838, PIN_OUTPUT | MUX_MODE7) /* gpmc_ad14.gpio1_14 */ + AM33XX_IOPAD(0x834, PIN_OUTPUT | MUX_MODE7) /* gpmc_ad13.gpio1_13 */ + AM33XX_IOPAD(0x830, PIN_OUTPUT | MUX_MODE7) /* gpmc_ad12.gpio1_12 */ + >; + }; +}; + +/* MMC */ +&am33xx_pinmux { + mmc1_pins: pinmux_mmc1 { + pinctrl-single,pins = < + AM33XX_IOPAD(0x8F0, PIN_INPUT_PULLUP | MUX_MODE0) + AM33XX_IOPAD(0x8F4, PIN_INPUT_PULLUP | MUX_MODE0) + AM33XX_IOPAD(0x8F8, PIN_INPUT_PULLUP | MUX_MODE0) + AM33XX_IOPAD(0x8FC, PIN_INPUT_PULLUP | MUX_MODE0) + AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0) + AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0) + AM33XX_IOPAD(0x960, PIN_INPUT_PULLUP | MUX_MODE7) /* spi0_cs1.mmc0_sdcd */ + >; + }; +}; + +&mmc1 { + vmmc-supply = <&vcc3v3>; + bus-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +/* RTC */ +&i2c_rtc { + status = "okay"; +}; + +/* UARTs */ +&am33xx_pinmux { + uart0_pins: pinmux_uart0 { + pinctrl-single,pins = < + AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) + AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) + >; + }; + + uart2_pins: pinmux_uart2 { + pinctrl-single,pins = < + AM33XX_IOPAD(0x92C, PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_tx_clk.uart2_rxd */ + AM33XX_IOPAD(0x930, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_rx_clk.uart2_txd */ + >; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; + status = "okay"; +}; + +/* RS485 - UART1 */ +&am33xx_pinmux { + uart1_rs485_pins: pinmux_uart1_rs485_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x980, PIN_INPUT_PULLUP | MUX_MODE0) + AM33XX_IOPAD(0x984, PIN_OUTPUT_PULLDOWN | MUX_MODE0) + AM33XX_IOPAD(0x97C, PIN_OUTPUT_PULLUP | MUX_MODE0) + >; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_rs485_pins>; + status = "okay"; + linux,rs485-enabled-at-boot-time; +}; diff --git a/board/phytec/phycore_am335x_r2/MAINTAINERS b/board/phytec/phycore_am335x_r2/MAINTAINERS index e56f30fdc0..8d02b0e198 100644 --- a/board/phytec/phycore_am335x_r2/MAINTAINERS +++ b/board/phytec/phycore_am335x_r2/MAINTAINERS @@ -1,7 +1,11 @@ phyCORE AM335x R2 WEGA BOARD M: Niel Fourie -M: Parthiban Nallathambi +M: Parthiban Nallathambi S: Maintained +F: arch/arm/dts/am335x-regor.dtsi +F: arch/arm/dts/am335x-regor-rdk.dts +F: arch/arm/dts/am335x-regor-rdk-u-boot.dtsi F: board/phytec/phycore_am335x_r2 F: include/configs/phycore_am335x_r2.h +F: configs/phycore-am335x-r2-regor_defconfig F: configs/phycore-am335x-r2-wega_defconfig diff --git a/configs/phycore-am335x-r2-regor_defconfig b/configs/phycore-am335x-r2-regor_defconfig new file mode 100644 index 0000000000..6d40497537 --- /dev/null +++ b/configs/phycore-am335x-r2-regor_defconfig @@ -0,0 +1,88 @@ +CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y +CONFIG_ARCH_OMAP2PLUS=y +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_ENV_OFFSET=0xA0000 +CONFIG_AM33XX=y +CONFIG_SYS_MPUCLK=1000 +CONFIG_TARGET_PHYCORE_AM335X_R2=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL=y +CONFIG_SPL_FS_FAT=y +CONFIG_SPL_LIBDISK_SUPPORT=y +CONFIG_SPL_PAYLOAD="u-boot.img" +CONFIG_DEFAULT_DEVICE_TREE="am335x-regor-rdk" +# CONFIG_FIT is not set +CONFIG_OF_BOARD_SETUP=y +CONFIG_DEFAULT_FDT_FILE="am335x-regor-rdk.dtb" +CONFIG_SYS_CONSOLE_INFO_QUIET=y +CONFIG_ARCH_MISC_INIT=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_NAND_DRIVERS=y +CONFIG_SPL_NAND_ECC=y +CONFIG_SPL_NAND_BASE=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_SPL=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y +CONFIG_CMD_NAND=y +CONFIG_CMD_PART=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_BOOTP_DNS2=y +CONFIG_CMD_PING=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_MTDPARTS=y +CONFIG_MTDIDS_DEFAULT="nand0=nand.0" +CONFIG_MTDPARTS_DEFAULT="mtdparts=nand.0:128k(NAND.SPL),1m(NAND.u-boot),-(NAND.UBI)" +CONFIG_CMD_UBI=y +CONFIG_DOS_PARTITION=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_FAT=y +CONFIG_ENV_IS_IN_NAND=y +CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_VERSION_VARIABLE=y +CONFIG_BOOTP_SEND_HOSTNAME=y +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_DM_I2C=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_MMC_OMAP_HS=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_MTD_RAW_NAND=y +CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y +CONFIG_SYS_NAND_U_BOOT_OFFS=0x20000 +CONFIG_DM_SPI_FLASH=y +CONFIG_DM_ETH=y +CONFIG_MII=y +CONFIG_DRIVER_TI_CPSW=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_OMAP3_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_USB_MUSB_HOST=y +CONFIG_USB_MUSB_GADGET=y +CONFIG_USB_MUSB_TI=y +CONFIG_USB_GADGET=y +CONFIG_USB_ETHER=y +CONFIG_FDT_FIXUP_PARTITIONS=y +# CONFIG_EFI_LOADER is not set From 4fcc084eeb8cd7db77263672c6a43da629a4ed48 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Mon, 26 Oct 2020 22:36:15 +0100 Subject: [PATCH 02/10] power: twl4030: Add twl4030_i2c_read() function MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Function twl4030_i2c_read() is like twl4030_i2c_read_u8() but instead of single value it rather returns array of values. Signed-off-by: Pali Rohár Reviewed-by: Jaehoon Chung --- drivers/power/twl4030.c | 7 +++---- include/twl4030.h | 12 +++++++++--- 2 files changed, 12 insertions(+), 7 deletions(-) diff --git a/drivers/power/twl4030.c b/drivers/power/twl4030.c index b0d5cba2c4..f48af84e17 100644 --- a/drivers/power/twl4030.c +++ b/drivers/power/twl4030.c @@ -201,7 +201,7 @@ int twl4030_i2c_write_u8(u8 chip_no, u8 reg, u8 val) return 0; } -int twl4030_i2c_read_u8(u8 chip_no, u8 reg, u8 *valp) +int twl4030_i2c_read(u8 chip_no, u8 reg, u8 *valp, int len) { struct udevice *dev; int ret; @@ -211,12 +211,11 @@ int twl4030_i2c_read_u8(u8 chip_no, u8 reg, u8 *valp) pr_err("unable to get I2C bus. ret %d\n", ret); return ret; } - ret = dm_i2c_reg_read(dev, reg); - if (ret < 0) { + ret = dm_i2c_read(dev, reg, valp, len); + if (ret) { pr_err("reading from twl4030 failed. ret %d\n", ret); return ret; } - *valp = (u8)ret; return 0; } #endif diff --git a/include/twl4030.h b/include/twl4030.h index c27ad615ee..ef05193996 100644 --- a/include/twl4030.h +++ b/include/twl4030.h @@ -654,14 +654,20 @@ static inline int twl4030_i2c_write_u8(u8 chip_no, u8 reg, u8 val) return i2c_write(chip_no, reg, 1, &val, 1); } -static inline int twl4030_i2c_read_u8(u8 chip_no, u8 reg, u8 *val) +static inline int twl4030_i2c_read(u8 chip_no, u8 reg, u8 *val, int len) { - return i2c_read(chip_no, reg, 1, val, 1); + return i2c_read(chip_no, reg, 1, val, len); } #else int twl4030_i2c_write_u8(u8 chip_no, u8 reg, u8 val); -int twl4030_i2c_read_u8(u8 chip_no, u8 reg, u8 *val); +int twl4030_i2c_read(u8 chip_no, u8 reg, u8 *val, int len); #endif + +static inline int twl4030_i2c_read_u8(u8 chip_no, u8 reg, u8 *val) +{ + return twl4030_i2c_read(chip_no, reg, val, 1); +} + /* * Power */ From 8d8c181703253e8162ed9b2bdfd353bf44448770 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Mon, 26 Oct 2020 23:45:11 +0100 Subject: [PATCH 03/10] Nokia RX-51: Convert to CONFIG_DM_I2C MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use twl4030_i2c_read(), i2c_get_chip_for_busnum() and remove CONFIG_SYS_I2C. Signed-off-by: Pali Rohár --- board/nokia/rx51/rx51.c | 25 +++++++++++++++++++------ configs/nokia_rx51_defconfig | 2 ++ include/configs/nokia_rx51.h | 2 -- 3 files changed, 21 insertions(+), 8 deletions(-) diff --git a/board/nokia/rx51/rx51.c b/board/nokia/rx51/rx51.c index f624dbfbeb..63531e1420 100644 --- a/board/nokia/rx51/rx51.c +++ b/board/nokia/rx51/rx51.c @@ -22,6 +22,7 @@ */ #include +#include #include #include #include @@ -33,6 +34,7 @@ #include #include #include +#include #include #include #include @@ -386,14 +388,13 @@ static void omap3_update_aux_cr_secure_rx51(u32 set_bits, u32 clear_bits) */ int misc_init_r(void) { + struct udevice *dev; char buf[12]; u8 state; /* reset lp5523 led */ - i2c_set_bus_num(1); - state = 0xff; - i2c_write(0x32, 0x3d, 1, &state, 1); - i2c_set_bus_num(0); + if (i2c_get_chip_for_busnum(1, 0x32, 1, &dev) == 0) + dm_i2c_reg_write(dev, 0x3d, 0xff); /* initialize twl4030 power managment */ twl4030_power_init(); @@ -626,8 +627,8 @@ int rx51_kp_tstc(struct stdio_dev *sdev) continue; /* read the key state */ - i2c_read(TWL4030_CHIP_KEYPAD, - TWL4030_KEYPAD_FULL_CODE_7_0, 1, keys, 8); + twl4030_i2c_read(TWL4030_CHIP_KEYPAD, + TWL4030_KEYPAD_FULL_CODE_7_0, keys, 8); /* cut out modifier keys from the keystate */ mods = keys[4] >> 4; @@ -684,3 +685,15 @@ void board_mmc_power_init(void) twl4030_power_mmc_init(0); twl4030_power_mmc_init(1); } + +static const struct omap_i2c_platdata rx51_i2c[] = { + { I2C_BASE1, 2200000, OMAP_I2C_REV_V1 }, + { I2C_BASE2, 100000, OMAP_I2C_REV_V1 }, + { I2C_BASE3, 400000, OMAP_I2C_REV_V1 }, +}; + +U_BOOT_DEVICES(rx51_i2c) = { + { "i2c_omap", &rx51_i2c[0] }, + { "i2c_omap", &rx51_i2c[1] }, + { "i2c_omap", &rx51_i2c[2] }, +}; diff --git a/configs/nokia_rx51_defconfig b/configs/nokia_rx51_defconfig index 1d353520a9..6310a12aaa 100644 --- a/configs/nokia_rx51_defconfig +++ b/configs/nokia_rx51_defconfig @@ -60,3 +60,5 @@ CONFIG_CFB_CONSOLE_ANSI=y # CONFIG_VGA_AS_SINGLE_DEVICE is not set CONFIG_SPLASH_SCREEN=y # CONFIG_GZIP is not set +CONFIG_DM=y +CONFIG_DM_I2C=y diff --git a/include/configs/nokia_rx51.h b/include/configs/nokia_rx51.h index c86c429413..9b89120342 100644 --- a/include/configs/nokia_rx51.h +++ b/include/configs/nokia_rx51.h @@ -77,8 +77,6 @@ /* commands to include */ -#define CONFIG_SYS_I2C - /* * TWL4030 */ From 87c5bc80fcd641375d5d633199a136b7b0931149 Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Fri, 30 Oct 2020 15:00:24 +0200 Subject: [PATCH 04/10] configs: am65/j72x: Set CONFIG_LOGLEVEL to 7 By default CONFIG_LOGLEVEL seems to be set to 4 which is too low and doesn't show dev_info/dev_notice/dev_warn messages on console. This has been deliberately set low globally to be conservative setting across the board due to primary bootloader size limitations. It is best to tune per board config as per user needs. On K3 we have separate SPL and u-boot configs so we can afford to set u-boot CONFIG_LOGLEVEL to 7. On AM65 this patch causes u-boot.img size to change from 932KB to 940KB with 1 line additional print during MMC boot. i.e. details of Net subsystem "Net: K3 CPSW: nuss_ver: 0x6BA00102 cpsw_ver: 0x6BA80102 ale_ver: 0x00293904 Ports:1 mdio_freq:1000000" Similar 8KB difference was seen on J721E. Signed-off-by: Roger Quadros Reviewed-by: Nishanth Menon --- configs/am65x_evm_a53_defconfig | 1 + configs/am65x_hs_evm_a53_defconfig | 1 + configs/j7200_evm_a72_defconfig | 1 + configs/j721e_evm_a72_defconfig | 1 + configs/j721e_hs_evm_a72_defconfig | 1 + 5 files changed, 5 insertions(+) diff --git a/configs/am65x_evm_a53_defconfig b/configs/am65x_evm_a53_defconfig index 8a94ad1530..941073ce7f 100644 --- a/configs/am65x_evm_a53_defconfig +++ b/configs/am65x_evm_a53_defconfig @@ -30,6 +30,7 @@ CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000 # CONFIG_USE_SPL_FIT_GENERATOR is not set CONFIG_OF_BOARD_SETUP=y CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run boot_rprocs; run get_kern_${boot}; run get_fdt_${boot}; run get_overlay_${boot}; run run_kern" +CONFIG_LOGLEVEL=7 CONFIG_CONSOLE_MUX=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_STACK_R=y diff --git a/configs/am65x_hs_evm_a53_defconfig b/configs/am65x_hs_evm_a53_defconfig index 2c7217afb6..7d467c167e 100644 --- a/configs/am65x_hs_evm_a53_defconfig +++ b/configs/am65x_hs_evm_a53_defconfig @@ -32,6 +32,7 @@ CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y # CONFIG_USE_SPL_FIT_GENERATOR is not set CONFIG_OF_BOARD_SETUP=y CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run get_fit_${boot}; run get_overlaystring; run run_fit" +CONFIG_LOGLEVEL=7 CONFIG_CONSOLE_MUX=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_STACK_R=y diff --git a/configs/j7200_evm_a72_defconfig b/configs/j7200_evm_a72_defconfig index 7c900b1d2e..1d2526b5f1 100644 --- a/configs/j7200_evm_a72_defconfig +++ b/configs/j7200_evm_a72_defconfig @@ -31,6 +31,7 @@ CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000 # CONFIG_USE_SPL_FIT_GENERATOR is not set CONFIG_OF_BOARD_SETUP=y CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run boot_rprocs; run get_kern_${boot}; run get_fdt_${boot}; run get_overlay_${boot}; run run_kern" +CONFIG_LOGLEVEL=7 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_STACK_R=y diff --git a/configs/j721e_evm_a72_defconfig b/configs/j721e_evm_a72_defconfig index 6de8666956..982e3df2f2 100644 --- a/configs/j721e_evm_a72_defconfig +++ b/configs/j721e_evm_a72_defconfig @@ -30,6 +30,7 @@ CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000 # CONFIG_USE_SPL_FIT_GENERATOR is not set CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run boot_rprocs; run get_kern_${boot}; run get_fdt_${boot}; run get_overlay_${boot}; run run_kern" +CONFIG_LOGLEVEL=7 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_STACK_R=y diff --git a/configs/j721e_hs_evm_a72_defconfig b/configs/j721e_hs_evm_a72_defconfig index acbc04359c..28bf56e7e1 100644 --- a/configs/j721e_hs_evm_a72_defconfig +++ b/configs/j721e_hs_evm_a72_defconfig @@ -31,6 +31,7 @@ CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000 CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y # CONFIG_USE_SPL_FIT_GENERATOR is not set CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run boot_rprocs; run get_fit_${boot}; run get_overlaystring; run run_fit" +CONFIG_LOGLEVEL=7 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_STACK_R=y From e4f7592196570db82343cedf156f4d3477f69610 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Sat, 31 Oct 2020 17:32:45 +0100 Subject: [PATCH 05/10] Nokia RX-51: Remove old comments from configs/nokia_rx51.h file MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit These comments are relict for old, now removed config options. So remove these obsoleted comments too. Signed-off-by: Pali Rohár --- include/configs/nokia_rx51.h | 10 ---------- 1 file changed, 10 deletions(-) diff --git a/include/configs/nokia_rx51.h b/include/configs/nokia_rx51.h index 9b89120342..6879f52a0c 100644 --- a/include/configs/nokia_rx51.h +++ b/include/configs/nokia_rx51.h @@ -75,12 +75,6 @@ #define CONFIG_USBD_MANUFACTURER "Nokia" #define CONFIG_USBD_PRODUCT_NAME "N900" -/* commands to include */ - -/* - * TWL4030 - */ - #define GPIO_SLIDE 71 /* @@ -229,10 +223,6 @@ int rx51_kp_getc(struct stdio_dev *sdev); "run attachboot;" \ "echo" -/* - * Miscellaneous configurable options - */ - /* default load address */ #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) From 94f69f4c14cafcce11544d8a615eff3767d66acd Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Sat, 31 Oct 2020 17:32:46 +0100 Subject: [PATCH 06/10] Nokia RX-51: Fix crashing in U-Boot mmc function omap_hsmmc_stop_clock() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit After commit 04a2ea248f58 ("mmc: disable UHS modes if Vcc cannot be switched on and off") U-Boot started crashing on Nokia RX-51 while initializing mmc and caused reboot loop. It looks like that some clocks were not enabled and this patch fixes U-Boot mmc crash. Signed-off-by: Pali Rohár Cc: Ivaylo Dimitrov --- board/nokia/rx51/rx51.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/board/nokia/rx51/rx51.c b/board/nokia/rx51/rx51.c index 63531e1420..e11c527226 100644 --- a/board/nokia/rx51/rx51.c +++ b/board/nokia/rx51/rx51.c @@ -202,6 +202,8 @@ int board_init(void) { /* in SRAM or SDRAM, finish GPMC */ gpmc_init(); + /* Enable the clks & power */ + per_clocks_enable(); /* boot param addr */ gd->bd->bi_boot_params = OMAP34XX_SDRC_CS0 + 0x100; return 0; From b95ffd3051bf730371cee38580b59250813431e8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Sat, 31 Oct 2020 17:32:47 +0100 Subject: [PATCH 07/10] Nokia RX-51: During init disable lp5523 led instead of resetting it MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit After commit d5243359e1af ("OMAP24xx I2C: Add support for set-speed") U-Boot is unstable to reset lp5523 led. That commit added pooling for i2c poll ARDY bit which apparently is never set. It is not known what is happening here. Purpose of resetting lp5523 led in Nokia RX-51 code is just to turn off very bright led which is powered on by NOLO and expects next boot image (kernel or U-Boot) to turn it off. After testing we observed that just disabling lp5523 led is working fine. So as a workaround to this ARDY bit i2c issue we disable lp5523 led instead of resetting it. Signed-off-by: Pali Rohár Cc: Ivaylo Dimitrov --- board/nokia/rx51/rx51.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/nokia/rx51/rx51.c b/board/nokia/rx51/rx51.c index e11c527226..528c592441 100644 --- a/board/nokia/rx51/rx51.c +++ b/board/nokia/rx51/rx51.c @@ -394,9 +394,9 @@ int misc_init_r(void) char buf[12]; u8 state; - /* reset lp5523 led */ + /* disable lp5523 led */ if (i2c_get_chip_for_busnum(1, 0x32, 1, &dev) == 0) - dm_i2c_reg_write(dev, 0x3d, 0xff); + dm_i2c_reg_write(dev, 0x00, 0x00); /* initialize twl4030 power managment */ twl4030_power_init(); From 56847f3a5e0c03d41cb092065d56e59da4e1c20f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Sat, 31 Oct 2020 17:32:48 +0100 Subject: [PATCH 08/10] Nokia RX-51: Update test script MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Include emmc/nand suffix into bootmenu script names and fix leaking sleep processes when asynchronously waiting for them. 'wait -n' is not provided by /bin/sh, so run script under bash. Signed-off-by: Pali Rohár --- test/nokia_rx51_test.sh | 27 +++++++++++++++------------ 1 file changed, 15 insertions(+), 12 deletions(-) diff --git a/test/nokia_rx51_test.sh b/test/nokia_rx51_test.sh index b17542b8c1..23fa935310 100755 --- a/test/nokia_rx51_test.sh +++ b/test/nokia_rx51_test.sh @@ -1,4 +1,4 @@ -#!/bin/sh -e +#!/bin/bash -e # SPDX-License-Identifier: GPL-2.0+ # (C) 2020 Pali Rohár @@ -157,7 +157,7 @@ setenv bootmenu_1; setenv bootmenu_delay 1; setenv bootdelay 1; EOF -./mkimage -A arm -O linux -T script -C none -a 0 -e 0 -n bootmenu -d bootmenu_emmc bootmenu_emmc.scr +./mkimage -A arm -O linux -T script -C none -a 0 -e 0 -n bootmenu_emmc -d bootmenu_emmc bootmenu_emmc.scr # Generate bootmenu for OneNAND booting cat > bootmenu_nand << EOF @@ -166,7 +166,7 @@ setenv bootmenu_1; setenv bootmenu_delay 1; setenv bootdelay 1; EOF -./mkimage -A arm -O linux -T script -C none -a 0 -e 0 -n bootmenu -d bootmenu_nand bootmenu_nand.scr +./mkimage -A arm -O linux -T script -C none -a 0 -e 0 -n bootmenu_nand -d bootmenu_nand bootmenu_nand.scr # Generate combined image from u-boot and Maemo fiasco kernel dd if=kernel_2.6.28/boot/zImage-2.6.28-20103103+0m5.fiasco of=zImage-2.6.28-omap1 skip=95 bs=1 @@ -214,10 +214,11 @@ rm -f qemu_ram.log qemu_pid=$! tail -F qemu_ram.log & tail_pid=$! -{ sleep 300 || true; kill -9 $qemu_pid $tail_pid 2>/dev/null || true; } & +sleep 300 & sleep_pid=$! -wait $qemu_pid || true -kill -9 $tail_pid $sleep_pid 2>/dev/null || true +wait -n $sleep_pid $qemu_pid || true +kill -9 $tail_pid $sleep_pid $qemu_pid 2>/dev/null || true +wait || true # Run MTD image in qemu and wait for 300s if kernel from eMMC is correctly booted rm -f qemu_emmc.log @@ -225,10 +226,11 @@ rm -f qemu_emmc.log qemu_pid=$! tail -F qemu_emmc.log & tail_pid=$! -{ sleep 300 || true; kill -9 $qemu_pid $tail_pid 2>/dev/null || true; } & +sleep 300 & sleep_pid=$! -wait $qemu_pid || true -kill -9 $tail_pid $sleep_pid 2>/dev/null || true +wait -n $sleep_pid $qemu_pid || true +kill -9 $tail_pid $sleep_pid $qemu_pid 2>/dev/null || true +wait || true # Run MTD image in qemu and wait for 300s if kernel from OneNAND is correctly booted rm -f qemu_nand.log @@ -236,10 +238,11 @@ rm -f qemu_nand.log qemu_pid=$! tail -F qemu_nand.log & tail_pid=$! -{ sleep 300 || true; kill -9 $qemu_pid $tail_pid 2>/dev/null || true; } & +sleep 300 & sleep_pid=$! -wait $qemu_pid || true -kill -9 $tail_pid $sleep_pid 2>/dev/null || true +wait -n $sleep_pid $qemu_pid || true +kill -9 $tail_pid $sleep_pid $qemu_pid 2>/dev/null || true +wait || true echo echo "=============================" From 71c27dbaaeea11b54f36c8f865f0a0cbeddaa19e Mon Sep 17 00:00:00 2001 From: Ivaylo Dimitrov Date: Sat, 31 Oct 2020 17:32:49 +0100 Subject: [PATCH 09/10] Nokia RX-51: Make onenand working MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit set_gpmc_cs0() sets wrong timings and size for Nokia N900 onenand flash. Fix that by setting the correct timings and size from the board code Signed-off-by: Ivaylo Dimitrov Tested-by: Pali Rohár --- board/nokia/rx51/rx51.c | 15 +++++++++++++++ board/nokia/rx51/rx51.h | 7 +++++++ 2 files changed, 22 insertions(+) diff --git a/board/nokia/rx51/rx51.c b/board/nokia/rx51/rx51.c index 528c592441..3d62b5d9ad 100644 --- a/board/nokia/rx51/rx51.c +++ b/board/nokia/rx51/rx51.c @@ -200,8 +200,23 @@ static void reuse_atags(void) */ int board_init(void) { +#if defined(CONFIG_CMD_ONENAND) + const u32 gpmc_regs_onenandrx51[GPMC_MAX_REG] = { + ONENAND_GPMC_CONFIG1_RX51, + ONENAND_GPMC_CONFIG2_RX51, + ONENAND_GPMC_CONFIG3_RX51, + ONENAND_GPMC_CONFIG4_RX51, + ONENAND_GPMC_CONFIG5_RX51, + ONENAND_GPMC_CONFIG6_RX51, + 0 + }; +#endif /* in SRAM or SDRAM, finish GPMC */ gpmc_init(); +#if defined(CONFIG_CMD_ONENAND) + enable_gpmc_cs_config(gpmc_regs_onenandrx51, &gpmc_cfg->cs[0], + CONFIG_SYS_ONENAND_BASE, GPMC_SIZE_256M); +#endif /* Enable the clks & power */ per_clocks_enable(); /* boot param addr */ diff --git a/board/nokia/rx51/rx51.h b/board/nokia/rx51/rx51.h index fa1b42bf21..4eff823a1b 100644 --- a/board/nokia/rx51/rx51.h +++ b/board/nokia/rx51/rx51.h @@ -367,4 +367,11 @@ struct emu_hal_params_rx51 { MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) /*UART2_RTS*/\ MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) /*UART2_TX*/ +#define ONENAND_GPMC_CONFIG1_RX51 0xfb001202 +#define ONENAND_GPMC_CONFIG2_RX51 0x00111100 +#define ONENAND_GPMC_CONFIG3_RX51 0x00020200 +#define ONENAND_GPMC_CONFIG4_RX51 0x11001102 +#define ONENAND_GPMC_CONFIG5_RX51 0x03101616 +#define ONENAND_GPMC_CONFIG6_RX51 0x90060000 + #endif From 914689a204308df47eb60dfbb394fa4cee4fda31 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Sat, 31 Oct 2020 17:32:50 +0100 Subject: [PATCH 10/10] mtd: OneNAND: Set MTD type MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit onenand_probe() function is missing to set mtd->type. So set same type as which sets onenand Linux kernel driver. After this change 'mtd list' prints correct type instead of 'Unknown'. Signed-off-by: Pali Rohár --- drivers/mtd/onenand/onenand_base.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mtd/onenand/onenand_base.c b/drivers/mtd/onenand/onenand_base.c index 36daef01ae..09daa0dd36 100644 --- a/drivers/mtd/onenand/onenand_base.c +++ b/drivers/mtd/onenand/onenand_base.c @@ -2657,6 +2657,7 @@ int onenand_probe(struct mtd_info *mtd) else mtd->size = this->chipsize; + mtd->type = ONENAND_IS_MLC(this) ? MTD_MLCNANDFLASH : MTD_NANDFLASH; mtd->flags = MTD_CAP_NANDFLASH; mtd->_erase = onenand_erase; mtd->_read_oob = onenand_read_oob;