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fsl/mpc85xx: define common serdes_clock_to_string function
This allows to share some common code for the boards that use a corenet base SoC. Two different versions of the function are available in fsl_corenet_serdes.c and fsl_corenet2_serdes.c files. Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> [York Sun: fix t1040qds.c] Acked-by: York Sun <yorksun@freescale.com>
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8 changed files with 39 additions and 74 deletions
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@ -201,3 +201,24 @@ void fsl_serdes_init(void)
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#endif
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}
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const char *serdes_clock_to_string(u32 clock)
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{
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switch (clock) {
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case SRDS_PLLCR0_RFCK_SEL_100:
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return "100";
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case SRDS_PLLCR0_RFCK_SEL_125:
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return "125";
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case SRDS_PLLCR0_RFCK_SEL_156_25:
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return "156.25";
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case SRDS_PLLCR0_RFCK_SEL_161_13:
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return "161.1328123";
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default:
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#if defined(CONFIG_T4240QDS)
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return "???";
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#else
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return "122.88";
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#endif
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}
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}
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@ -858,3 +858,20 @@ void fsl_serdes_init(void)
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}
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#endif
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}
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const char *serdes_clock_to_string(u32 clock)
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{
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switch (clock) {
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case SRDS_PLLCR0_RFCK_SEL_100:
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return "100";
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case SRDS_PLLCR0_RFCK_SEL_125:
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return "125";
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case SRDS_PLLCR0_RFCK_SEL_156_25:
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return "156.25";
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case SRDS_PLLCR0_RFCK_SEL_161_13:
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return "161.1328123";
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default:
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return "150";
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}
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}
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@ -86,6 +86,7 @@ enum srds {
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int is_serdes_configured(enum srds_prtcl device);
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void fsl_serdes_init(void);
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const char *serdes_clock_to_string(u32 clock);
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#ifdef CONFIG_FSL_CORENET
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#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
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@ -457,22 +457,6 @@ static int serdes_refclock(u8 sw, u8 sdclk)
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return ret;
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}
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static const char *serdes_clock_to_string(u32 clock)
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{
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switch (clock) {
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case SRDS_PLLCR0_RFCK_SEL_100:
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return "100";
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case SRDS_PLLCR0_RFCK_SEL_125:
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return "125";
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case SRDS_PLLCR0_RFCK_SEL_156_25:
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return "156.25";
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case SRDS_PLLCR0_RFCK_SEL_161_13:
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return "161.13";
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default:
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return "122.88";
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}
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}
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#define NUM_SRDS_BANKS 2
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int misc_init_r(void)
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@ -127,20 +127,6 @@ int board_early_init_r(void)
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return 0;
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}
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static const char *serdes_clock_to_string(u32 clock)
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{
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switch(clock) {
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case SRDS_PLLCR0_RFCK_SEL_100:
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return "100";
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case SRDS_PLLCR0_RFCK_SEL_125:
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return "125";
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case SRDS_PLLCR0_RFCK_SEL_156_25:
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return "156.25";
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default:
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return "150";
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}
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}
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#define NUM_SRDS_BANKS 3
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int misc_init_r(void)
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@ -155,20 +155,6 @@ unsigned long get_board_sys_clk(unsigned long dummy)
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}
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}
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static const char *serdes_clock_to_string(u32 clock)
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{
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switch (clock) {
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case SRDS_PLLCR0_RFCK_SEL_100:
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return "100";
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case SRDS_PLLCR0_RFCK_SEL_125:
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return "125";
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case SRDS_PLLCR0_RFCK_SEL_156_25:
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return "156.25";
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default:
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return "150";
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}
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}
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#define NUM_SRDS_BANKS 2
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int misc_init_r(void)
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@ -160,20 +160,6 @@ unsigned long get_board_ddr_clk(void)
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return 66666666;
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}
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static const char *serdes_clock_to_string(u32 clock)
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{
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switch (clock) {
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case SRDS_PLLCR0_RFCK_SEL_100:
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return "100";
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case SRDS_PLLCR0_RFCK_SEL_125:
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return "125";
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case SRDS_PLLCR0_RFCK_SEL_156_25:
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return "156.25";
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default:
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return "Unknown frequency";
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}
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}
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#define NUM_SRDS_BANKS 2
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int misc_init_r(void)
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{
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@ -608,22 +608,6 @@ unsigned long get_board_ddr_clk(void)
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return 66666666;
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}
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static const char *serdes_clock_to_string(u32 clock)
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{
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switch (clock) {
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case SRDS_PLLCR0_RFCK_SEL_100:
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return "100";
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case SRDS_PLLCR0_RFCK_SEL_125:
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return "125";
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case SRDS_PLLCR0_RFCK_SEL_156_25:
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return "156.25";
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case SRDS_PLLCR0_RFCK_SEL_161_13:
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return "161.1328125";
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default:
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return "???";
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}
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}
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int misc_init_r(void)
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{
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u8 sw;
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