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Fix CFG_HZ problems on AT91RM9200 systems
[Remember: CFG_HZ should be 1000 on ALL systems!]
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4 changed files with 28 additions and 10 deletions
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@ -2,6 +2,9 @@
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Changes since U-Boot 1.1.1:
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======================================================================
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* Fix CFG_HZ problems on AT91RM9200 systems
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[Remember: CFG_HZ should be 1000 on ALL systems!]
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* Patch by Gridish Shlomi, 30 Aug 2004:
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- Add support to revA version of PQ27 and PQ27E.
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- Reverted MPC8260ADS baudrate back to original 115200
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@ -37,8 +37,8 @@
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extern void reset_cpu(ulong addr);
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/* we always count down the max. */
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#define TIMER_LOAD_VAL 0xffff
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/* the number of clocks per CFG_HZ */
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#define TIMER_LOAD_VAL (CFG_HZ_CLOCK/CFG_HZ)
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/* macro to read the 16 bit timer */
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#define READ_TIMER (tmr->TC_CV & 0x0000ffff)
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@ -165,11 +165,13 @@ int interrupt_init (void)
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*AT91C_TCB0_BCR = 0;
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*AT91C_TCB0_BMR = AT91C_TCB_TC0XC0S_NONE | AT91C_TCB_TC1XC1S_NONE | AT91C_TCB_TC2XC2S_NONE;
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tmr->TC_CCR = AT91C_TC_CLKDIS;
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tmr->TC_CMR = AT91C_TC_TIMER_DIV1_CLOCK; /* set to MCLK/2 */
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#define AT91C_TC_CMR_CPCTRG (1 << 14)
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/* set to MCLK/2 and restart the timer when the vlaue in TC_RC is reached */
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tmr->TC_CMR = AT91C_TC_TIMER_DIV1_CLOCK | AT91C_TC_CMR_CPCTRG;
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tmr->TC_IDR = ~0ul;
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tmr->TC_RC = TIMER_LOAD_VAL;
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lastinc = TIMER_LOAD_VAL;
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lastinc = 0;
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tmr->TC_CCR = AT91C_TC_SWTRG | AT91C_TC_CLKEN;
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timestamp = 0;
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@ -207,7 +209,7 @@ void reset_timer_masked (void)
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timestamp = 0;
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}
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ulong get_timer_masked (void)
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ulong get_timer_raw (void)
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{
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ulong now = READ_TIMER;
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@ -223,17 +225,27 @@ ulong get_timer_masked (void)
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return timestamp;
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}
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ulong get_timer_masked (void)
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{
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return get_timer_raw()/TIMER_LOAD_VAL;
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}
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void udelay_masked (unsigned long usec)
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{
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ulong tmo;
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#if 0 /* doesn't work for usec < 1000 */
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tmo = usec / 1000;
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tmo *= CFG_HZ;
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tmo *= CFG_HZ_CLOCK;
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#else
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tmo = CFG_HZ_CLOCK / 1000;
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tmo *= usec;
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#endif
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tmo /= 1000;
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reset_timer_masked ();
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while (get_timer_masked () < tmo)
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while (get_timer_raw () < tmo)
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/*NOP*/;
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}
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@ -182,7 +182,8 @@ struct bd_info_ext {
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};
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#endif
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#define CFG_HZ AT91C_MASTER_CLOCK/2 /* AT91C_TC0_CMR is implicitly set to */
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#define CFG_HZ 1000
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#define CFG_HZ_CLOCK AT91C_MASTER_CLOCK/2 /* AT91C_TC0_CMR is implicitly set to */
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/* AT91C_TC_TIMER_DIV1_CLOCK */
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#define CONFIG_STACKSIZE (32*1024) /* regular stack */
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@ -71,7 +71,7 @@
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#undef CONFIG_MODEM_SUPPORT /* disable modem initialization stuff */
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#define CONFIG_HARD_I2C
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#undef CONFIG_HARD_I2C
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#ifdef CONFIG_HARD_I2C
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#define CFG_I2C_SPEED 0 /* not used */
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@ -90,6 +90,7 @@
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#define CONFIG_COMMANDS \
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((CONFIG_CMD_DFL | \
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CFG_CMD_I2C | \
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CFG_CMD_DATE | \
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CFG_CMD_EEPROM | \
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CFG_CMD_DHCP ) & \
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~(CFG_CMD_BDI | \
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@ -213,7 +214,8 @@ struct bd_info_ext {
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};
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#endif
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#define CFG_HZ AT91C_MASTER_CLOCK/2 /* AT91C_TC0_CMR is implicitly set to */
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#define CFG_HZ 1000
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#define CFG_HZ_CLOCK AT91C_MASTER_CLOCK/2 /* AT91C_TC0_CMR is implicitly set to */
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/* AT91C_TC_TIMER_DIV1_CLOCK */
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#define CONFIG_STACKSIZE (32*1024) /* regular stack */
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