GitHub-Mirror/u-boot
2
0
Fork 0
mirror of https://github.com/Fishwaldo/u-boot.git synced 2025-03-21 06:31:31 +00:00
Code Issues Projects Releases Packages Wiki Activity Actions

Merge branch 'master' of git://git.denx.de/u-boot-i2c

Browse source 
* 'master' of git://git.denx.de/u-boot-i2c:
  km/common: remove printfs for i2c deblocking code
  CONFIG: SMDK5250: I2C: Enable I2C
  I2C: Add support for Multi channel
  I2C: Modify the I2C driver for EXYNOS5
  I2C: Move struct s3c24x0_i2c to a common place.
  EXYNOS: PINMUX: Add pinmux support for I2C
  EXYNOS5: define EXYNOS5_I2C_SPACING
  EXYNOS: Add I2C base address.
  EXYNOS: CLK: Add i2c clock
  mx6qsabrelite: add i2c multi-bus support
  imx-common: add i2c.c for bus recovery support
  i.mx53: add definition for I2C3_BASE_ADDR
  i.mx: iomux-v3.c: move to imx-common directory
  i.mx: iomux-v3.h: move to imx-common include directory
  iomux-v3: remove include of mx6x_pins.h
  mxc_i2c: finish adding CONFIG_I2C_MULTI_BUS support
  mxc_i2c: add bus recovery support
  mxc_i2c: prep work for multiple busses support
  mxc_i2c: add i2c_regs argument to i2c_imx_stop
  mxc_i2c: add retries
  mxc_i2c: check for arbitration lost
  mxc_i2c: change slave addr if conflicts with destination.
  mxc_i2c: don't disable controller after every transaction
  mxc_i2c: place i2c_reset code inline
  mxc_i2c: place imx_start code inline
  mxc_i2c: remove redundant read
  mxc_i2c: combine i2c_imx_bus_busy and i2c_imx_trx_complete into wait_for_sr_state
  mxc_i2c.c: code i2c_probe as a 0 length i2c_write
  mxc_i2c: call i2c_imx_stop on error in i2c_read/i2c_write
  mxc_i2c: create i2c_init_transfer
  mxc_i2c: clear i2sr before waiting for bit
  mxc_i2c: create tx_byte function
  mxc_i2c: remove ifdef of CONFIG_HARD_I2C
  mxc_i2c: fix i2c_imx_stop
  i2c: deblock i2c bus also if accessed before realocation

Signed-off-by: Wolfgang Denk <wd@denx.de>
This commit is contained in:
Wolfgang Denk 2012-07-31 22:07:42 +02:00
commit 948fa1713c
29 changed files with 831 additions and 330 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

33
arch/arm/cpu/armv7/exynos/clock.c
View file

@ -578,6 +578,29 @@ void exynos4_set_mipi_clk(void)
writel(cfg, &clk->div_lcd0);
}
/*
* I2C
*
* exynos5: obtaining the I2C clock
*/
static unsigned long exynos5_get_i2c_clk(void)
{
struct exynos5_clock *clk =
(struct exynos5_clock *)samsung_get_base_clock();
unsigned long aclk_66, aclk_66_pre, sclk;
unsigned int ratio;
sclk = get_pll_clk(MPLL);
ratio = (readl(&clk->div_top1)) >> 24;
ratio &= 0x7;
aclk_66_pre = sclk / (ratio + 1);
ratio = readl(&clk->div_top0);
ratio &= 0x7;
aclk_66 = aclk_66_pre / (ratio + 1);
return aclk_66;
}
unsigned long get_pll_clk(int pllreg)
{
if (cpu_is_exynos5())
@ -594,6 +617,16 @@ unsigned long get_arm_clk(void)
return exynos4_get_arm_clk();
}
unsigned long get_i2c_clk(void)
{
if (cpu_is_exynos5()) {
return exynos5_get_i2c_clk();
} else {
debug("I2C clock is not set for this CPU\n");
return 0;
}
}
unsigned long get_pwm_clk(void)
{
if (cpu_is_exynos5())

52
arch/arm/cpu/armv7/exynos/pinmux.c
View file

@ -184,6 +184,48 @@ static void exynos5_sromc_config(int flags)
}
}
static void exynos5_i2c_config(int peripheral, int flags)
{
struct exynos5_gpio_part1 *gpio1 =
(struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
switch (peripheral) {
case PERIPH_ID_I2C0:
s5p_gpio_cfg_pin(&gpio1->b3, 0, GPIO_FUNC(0x2));
s5p_gpio_cfg_pin(&gpio1->b3, 1, GPIO_FUNC(0x2));
break;
case PERIPH_ID_I2C1:
s5p_gpio_cfg_pin(&gpio1->b3, 2, GPIO_FUNC(0x2));
s5p_gpio_cfg_pin(&gpio1->b3, 3, GPIO_FUNC(0x2));
break;
case PERIPH_ID_I2C2:
s5p_gpio_cfg_pin(&gpio1->a0, 6, GPIO_FUNC(0x3));
s5p_gpio_cfg_pin(&gpio1->a0, 7, GPIO_FUNC(0x3));
break;
case PERIPH_ID_I2C3:
s5p_gpio_cfg_pin(&gpio1->a1, 2, GPIO_FUNC(0x3));
s5p_gpio_cfg_pin(&gpio1->a1, 3, GPIO_FUNC(0x3));
break;
case PERIPH_ID_I2C4:
s5p_gpio_cfg_pin(&gpio1->a2, 0, GPIO_FUNC(0x3));
s5p_gpio_cfg_pin(&gpio1->a2, 1, GPIO_FUNC(0x3));
break;
case PERIPH_ID_I2C5:
s5p_gpio_cfg_pin(&gpio1->a2, 2, GPIO_FUNC(0x3));
s5p_gpio_cfg_pin(&gpio1->a2, 3, GPIO_FUNC(0x3));
break;
case PERIPH_ID_I2C6:
s5p_gpio_cfg_pin(&gpio1->b1, 3, GPIO_FUNC(0x4));
s5p_gpio_cfg_pin(&gpio1->b1, 4, GPIO_FUNC(0x4));
break;
case PERIPH_ID_I2C7:
s5p_gpio_cfg_pin(&gpio1->b2, 2, GPIO_FUNC(0x3));
s5p_gpio_cfg_pin(&gpio1->b2, 3, GPIO_FUNC(0x3));
break;
}
}
static int exynos5_pinmux_config(int peripheral, int flags)
{
switch (peripheral) {
@ -201,6 +243,16 @@ static int exynos5_pinmux_config(int peripheral, int flags)
case PERIPH_ID_SROMC:
exynos5_sromc_config(flags);
break;
case PERIPH_ID_I2C0:
case PERIPH_ID_I2C1:
case PERIPH_ID_I2C2:
case PERIPH_ID_I2C3:
case PERIPH_ID_I2C4:
case PERIPH_ID_I2C5:
case PERIPH_ID_I2C6:
case PERIPH_ID_I2C7:
exynos5_i2c_config(peripheral, flags);
break;
default:
debug("%s: invalid peripheral %d", __func__, peripheral);
return -1;

4
arch/arm/cpu/armv7/imx-common/Makefile
View file

@ -27,7 +27,9 @@ include $(TOPDIR)/config.mk
LIB = $(obj)libimx-common.o
COBJS = timer.o cpu.o speed.o
COBJS-y = iomux-v3.o timer.o cpu.o speed.o
COBJS-$(CONFIG_I2C_MXC) += i2c.o
COBJS := $(sort $(COBJS-y))
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))

99
arch/arm/cpu/armv7/imx-common/i2c.c Normal file
View file

@ -0,0 +1,99 @@
/*
* Copyright (C) 2012 Boundary Devices Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#include <asm/errno.h>
#include <asm/gpio.h>
#include <asm/imx-common/mxc_i2c.h>
#include <watchdog.h>
static int force_idle_bus(void *priv)
{
int i;
int sda, scl;
ulong elapsed, start_time;
struct i2c_pads_info *p = (struct i2c_pads_info *)priv;
int ret = 0;
gpio_direction_input(p->sda.gp);
gpio_direction_input(p->scl.gp);
imx_iomux_v3_setup_pad(p->sda.gpio_mode);
imx_iomux_v3_setup_pad(p->scl.gpio_mode);
sda = gpio_get_value(p->sda.gp);
scl = gpio_get_value(p->scl.gp);
if ((sda & scl) == 1)
goto exit; /* Bus is idle already */
printf("%s: sda=%d scl=%d sda.gp=0x%x scl.gp=0x%x\n", __func__,
sda, scl, p->sda.gp, p->scl.gp);
/* Send high and low on the SCL line */
for (i = 0; i < 9; i++) {
gpio_direction_output(p->scl.gp, 0);
udelay(50);
gpio_direction_input(p->scl.gp);
udelay(50);
}
start_time = get_timer(0);
for (;;) {
sda = gpio_get_value(p->sda.gp);
scl = gpio_get_value(p->scl.gp);
if ((sda & scl) == 1)
break;
WATCHDOG_RESET();
elapsed = get_timer(start_time);
if (elapsed > (CONFIG_SYS_HZ / 5)) { /* .2 seconds */
ret = -EBUSY;
printf("%s: failed to clear bus, sda=%d scl=%d\n",
__func__, sda, scl);
break;
}
}
exit:
imx_iomux_v3_setup_pad(p->sda.i2c_mode);
imx_iomux_v3_setup_pad(p->scl.i2c_mode);
return ret;
}
static void * const i2c_bases[] = {
(void *)I2C1_BASE_ADDR,
(void *)I2C2_BASE_ADDR,
#ifdef I2C3_BASE_ADDR
(void *)I2C3_BASE_ADDR,
#endif
};
/* i2c_index can be from 0 - 2 */
void setup_i2c(unsigned i2c_index, int speed, int slave_addr,
struct i2c_pads_info *p)
{
if (i2c_index >= ARRAY_SIZE(i2c_bases))
return;
/* Enable i2c clock */
enable_i2c_clk(1, i2c_index);
/* Make sure bus is idle */
force_idle_bus(p);
bus_i2c_init(i2c_bases[i2c_index], speed, slave_addr,
force_idle_bus, p);
}

3
arch/arm/cpu/armv7/mx6/iomux-v3.c → arch/arm/cpu/armv7/imx-common/iomux-v3.c
View file

@ -23,8 +23,7 @@
#include <common.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/mx6x_pins.h>
#include <asm/arch/iomux-v3.h>
#include <asm/imx-common/iomux-v3.h>
static void *base = (void *)IOMUXC_BASE_ADDR;

20
arch/arm/cpu/armv7/mx5/clock.c
View file

@ -117,6 +117,26 @@ void enable_usboh3_clk(unsigned char enable)
writel(reg, &mxc_ccm->CCGR2);
}
#ifdef CONFIG_I2C_MXC
/* i2c_num can be from 0 - 2 */
int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
{
u32 reg;
u32 mask;
if (i2c_num > 2)
return -EINVAL;
mask = MXC_CCM_CCGR_CG_MASK << ((i2c_num + 9) << 1);
reg = __raw_readl(&mxc_ccm->CCGR1);
if (enable)
reg |= mask;
else
reg &= ~mask;
__raw_writel(reg, &mxc_ccm->CCGR1);
return 0;
}
#endif
void set_usb_phy1_clk(void)
{
unsigned int reg;

2
arch/arm/cpu/armv7/mx6/Makefile
View file

@ -27,7 +27,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(SOC).o
COBJS = soc.o clock.o iomux-v3.o
COBJS = soc.o clock.o
SOBJS = lowlevel_init.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)

20
arch/arm/cpu/armv7/mx6/clock.c
View file

@ -50,6 +50,26 @@ void enable_usboh3_clk(unsigned char enable)
}
#ifdef CONFIG_I2C_MXC
/* i2c_num can be from 0 - 2 */
int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
{
u32 reg;
u32 mask;
if (i2c_num > 2)
return -EINVAL;
mask = MXC_CCM_CCGR_CG_MASK << ((i2c_num + 3) << 1);
reg = __raw_readl(&imx_ccm->CCGR2);
if (enable)
reg |= mask;
else
reg &= ~mask;
__raw_writel(reg, &imx_ccm->CCGR2);
return 0;
}
#endif
static u32 decode_pll(enum pll_clocks pll, u32 infreq)
{
u32 div;

1
arch/arm/include/asm/arch-exynos/clk.h
View file

@ -30,6 +30,7 @@
unsigned long get_pll_clk(int pllreg);
unsigned long get_arm_clk(void);
unsigned long get_i2c_clk(void);
unsigned long get_pwm_clk(void);
unsigned long get_uart_clk(int dev_index);
void set_mmc_clk(int dev_index, unsigned int div);

5
arch/arm/include/asm/arch-exynos/cpu.h
View file

@ -49,6 +49,7 @@
#define EXYNOS4_USB_HOST_EHCI_BASE 0x12580000
#define EXYNOS4_USBPHY_BASE 0x125B0000
#define EXYNOS4_UART_BASE 0x13800000
#define EXYNOS4_I2C_BASE 0x13860000
#define EXYNOS4_ADC_BASE 0x13910000
#define EXYNOS4_PWMTIMER_BASE 0x139D0000
#define EXYNOS4_MODEM_BASE 0x13A00000
@ -57,6 +58,8 @@
#define EXYNOS4_GPIO_PART4_BASE DEVICE_NOT_AVAILABLE
/* EXYNOS5 */
#define EXYNOS5_I2C_SPACING 0x10000
#define EXYNOS5_GPIO_PART4_BASE 0x03860000
#define EXYNOS5_PRO_ID 0x10000000
#define EXYNOS5_CLOCK_BASE 0x10010000
@ -76,6 +79,7 @@
#define EXYNOS5_MMC_BASE 0x12200000
#define EXYNOS5_SROMC_BASE 0x12250000
#define EXYNOS5_UART_BASE 0x12C00000
#define EXYNOS5_I2C_BASE 0x12C60000
#define EXYNOS5_PWMTIMER_BASE 0x12DD0000
#define EXYNOS5_GPIO_PART2_BASE 0x13400000
#define EXYNOS5_FIMD_BASE 0x14400000
@ -148,6 +152,7 @@ SAMSUNG_BASE(adc, ADC_BASE)
SAMSUNG_BASE(clock, CLOCK_BASE)
SAMSUNG_BASE(sysreg, SYSREG_BASE)
SAMSUNG_BASE(fimd, FIMD_BASE)
SAMSUNG_BASE(i2c, I2C_BASE)
SAMSUNG_BASE(mipi_dsim, MIPI_DSIM_BASE)
SAMSUNG_BASE(gpio_part1, GPIO_PART1_BASE)
SAMSUNG_BASE(gpio_part2, GPIO_PART2_BASE)

8
arch/arm/include/asm/arch-exynos/periph.h
View file

@ -30,6 +30,14 @@
*
*/
enum periph_id {
PERIPH_ID_I2C0,
PERIPH_ID_I2C1,
PERIPH_ID_I2C2,
PERIPH_ID_I2C3,
PERIPH_ID_I2C4,
PERIPH_ID_I2C5,
PERIPH_ID_I2C6,
PERIPH_ID_I2C7,
PERIPH_ID_SDMMC0,
PERIPH_ID_SDMMC1,
PERIPH_ID_SDMMC2,

1
arch/arm/include/asm/arch-mx5/clock.h
View file

@ -49,5 +49,6 @@ void enable_usb_phy2_clk(unsigned char enable);
void set_usboh3_clk(void);
void enable_usboh3_clk(unsigned char enable);
void mxc_set_sata_internal_clock(void);
int enable_i2c_clk(unsigned char enable, unsigned i2c_num);
#endif /* __ASM_ARCH_CLOCK_H */

1
arch/arm/include/asm/arch-mx5/imx-regs.h
View file

@ -96,6 +96,7 @@
#define GPIO5_BASE_ADDR (AIPS1_BASE_ADDR + 0x000DC000)
#define GPIO6_BASE_ADDR (AIPS1_BASE_ADDR + 0x000E0000)
#define GPIO7_BASE_ADDR (AIPS1_BASE_ADDR + 0x000E4000)
#define I2C3_BASE_ADDR (AIPS1_BASE_ADDR + 0x000EC000)
#define UART4_BASE_ADDR (AIPS1_BASE_ADDR + 0x000F0000)
#endif
/*

1
arch/arm/include/asm/arch-mx6/clock.h
View file

@ -48,5 +48,6 @@ u32 imx_get_fecclk(void);
unsigned int mxc_get_clock(enum mxc_clock clk);
void enable_usboh3_clk(unsigned char enable);
int enable_sata_clock(void);
int enable_i2c_clk(unsigned char enable, unsigned i2c_num);
#endif /* __ASM_ARCH_CLOCK_H */

2
arch/arm/include/asm/arch-mx6/mx6x_pins.h
View file

@ -22,7 +22,7 @@
#ifndef __ASM_ARCH_MX6_MX6X_PINS_H__
#define __ASM_ARCH_MX6_MX6X_PINS_H__
#include <asm/arch/iomux-v3.h>
#include <asm/imx-common/iomux-v3.h>
/* Use to set PAD control */
#define PAD_CTL_HYS (1 << 16)

10
arch/arm/include/asm/arch-s3c24x0/s3c24x0.h
View file

@ -343,16 +343,6 @@ struct s3c24x0_watchdog {
u32 wtcnt;
};
/* IIC (see manual chapter 20) */
struct s3c24x0_i2c {
u32 iiccon;
u32 iicstat;
u32 iicadd;
u32 iicds;
};
/* IIS (see manual chapter 21) */
struct s3c24x0_i2s {
#ifdef __BIG_ENDIAN

0
arch/arm/include/asm/arch-mx6/iomux-v3.h → arch/arm/include/asm/imx-common/iomux-v3.h
View file

42
arch/arm/include/asm/imx-common/mxc_i2c.h Normal file
View file

@ -0,0 +1,42 @@
/*
* Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*/
#ifndef __ASM_ARCH_MXC_MXC_I2C_H__
#define __ASM_ARCH_MXC_MXC_I2C_H__
#include <asm/imx-common/iomux-v3.h>
struct i2c_pin_ctrl {
iomux_v3_cfg_t i2c_mode;
iomux_v3_cfg_t gpio_mode;
unsigned char gp;
unsigned char spare;
};
struct i2c_pads_info {
struct i2c_pin_ctrl scl;
struct i2c_pin_ctrl sda;
};
void setup_i2c(unsigned i2c_index, int speed, int slave_addr,
struct i2c_pads_info *p);
void bus_i2c_init(void *base, int speed, int slave_addr,
int (*idle_bus_fn)(void *p), void *p);
int bus_i2c_read(void *base, uchar chip, uint addr, int alen, uchar *buf,
int len);
int bus_i2c_write(void *base, uchar chip, uint addr, int alen,
const uchar *buf, int len);
#endif

2
board/freescale/mx6qarm2/mx6qarm2.c
View file

@ -24,9 +24,9 @@
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/mx6x_pins.h>
#include <asm/arch/iomux-v3.h>
#include <asm/errno.h>
#include <asm/gpio.h>
#include <asm/imx-common/iomux-v3.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <miiphy.h>

54
board/freescale/mx6qsabrelite/mx6qsabrelite.c
View file

@ -22,12 +22,13 @@
#include <common.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/mx6x_pins.h>
#include <asm/arch/iomux-v3.h>
#include <asm/arch/clock.h>
#include <asm/errno.h>
#include <asm/gpio.h>
#include <asm/imx-common/iomux-v3.h>
#include <asm/imx-common/mxc_i2c.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <micrel.h>
@ -77,9 +78,48 @@ iomux_v3_cfg_t uart2_pads[] = {
MX6Q_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
};
iomux_v3_cfg_t i2c3_pads[] = {
MX6Q_PAD_GPIO_5__I2C3_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL),
MX6Q_PAD_GPIO_16__I2C3_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL),
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
/* I2C1, SGTL5000 */
struct i2c_pads_info i2c_pad_info0 = {
.scl = {
.i2c_mode = MX6Q_PAD_EIM_D21__I2C1_SCL | PC,
.gpio_mode = MX6Q_PAD_EIM_D21__GPIO_3_21 | PC,
.gp = GPIO_NUMBER(3, 21)
},
.sda = {
.i2c_mode = MX6Q_PAD_EIM_D28__I2C1_SDA | PC,
.gpio_mode = MX6Q_PAD_EIM_D28__GPIO_3_28 | PC,
.gp = GPIO_NUMBER(3, 28)
}
};
/* I2C2 Camera, MIPI */
struct i2c_pads_info i2c_pad_info1 = {
.scl = {
.i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | PC,
.gpio_mode = MX6Q_PAD_KEY_COL3__GPIO_4_12 | PC,
.gp = GPIO_NUMBER(4, 12)
},
.sda = {
.i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC,
.gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO_4_13 | PC,
.gp = GPIO_NUMBER(4, 13)
}
};
/* I2C3, J15 - RGB connector */
struct i2c_pads_info i2c_pad_info2 = {
.scl = {
.i2c_mode = MX6Q_PAD_GPIO_5__I2C3_SCL | PC,
.gpio_mode = MX6Q_PAD_GPIO_5__GPIO_1_5 | PC,
.gp = GPIO_NUMBER(1, 5)
},
.sda = {
.i2c_mode = MX6Q_PAD_GPIO_16__I2C3_SDA | PC,
.gpio_mode = MX6Q_PAD_GPIO_16__GPIO_7_11 | PC,
.gp = GPIO_NUMBER(7, 11)
}
};
iomux_v3_cfg_t usdhc3_pads[] = {
@ -346,7 +386,9 @@ int board_init(void)
#ifdef CONFIG_MXC_SPI
setup_spi();
#endif
imx_iomux_v3_setup_multiple_pads(i2c3_pads, ARRAY_SIZE(i2c3_pads));
setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);
setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
#ifdef CONFIG_CMD_SATA
setup_sata();

3
board/keymile/common/common.c
View file

@ -151,7 +151,6 @@ int i2c_make_abort(void)
sda_state = get_sda();
if (scl_state && sda_state) {
ret = 0;
printf("[INFO] i2c abort after %d clocks\n", i);
break;
}
}
@ -159,8 +158,6 @@ int i2c_make_abort(void)
if (ret == 0)
for (i = 0; i < 5; i++)
i2c_write_start_seq();
else
printf("[ERROR] i2c abort failed\n");
/* respect stop setup time */
udelay(DELAY_ABORT_SEQ);

30
board/samsung/smdk5250/smdk5250.c
View file

@ -22,6 +22,7 @@
#include <common.h>
#include <asm/io.h>
#include <i2c.h>
#include <netdev.h>
#include <asm/arch/cpu.h>
#include <asm/arch/gpio.h>
@ -172,9 +173,36 @@ static int board_uart_init(void)
return 0;
}
#ifdef CONFIG_SYS_I2C_INIT_BOARD
static int board_i2c_init(void)
{
int i, err;
for (i = 0; i < CONFIG_MAX_I2C_NUM; i++) {
err = exynos_pinmux_config((PERIPH_ID_I2C0 + i),
PINMUX_FLAG_NONE);
if (err) {
debug("I2C%d not configured\n", (PERIPH_ID_I2C0 + i));
return err;
}
}
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
return 0;
}
#endif
#ifdef CONFIG_BOARD_EARLY_INIT_F
int board_early_init_f(void)
{
return board_uart_init();
int err;
err = board_uart_init();
if (err) {
debug("UART init failed\n");
return err;
}
#ifdef CONFIG_SYS_I2C_INIT_BOARD
err = board_i2c_init();
#endif
return err;
}
#endif

1
common/cmd_i2c.c
View file

@ -1445,6 +1445,7 @@ int i2c_mux_ident_muxstring_f (uchar *buf)
oldpos = pos;
}
i2c_init_board();
return 0;
}

495
drivers/i2c/mxc_i2c.c
View file

@ -31,13 +31,12 @@
*/
#include <common.h>
#include <asm/io.h>
#if defined(CONFIG_HARD_I2C)
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#include <asm/errno.h>
#include <asm/io.h>
#include <i2c.h>
#include <watchdog.h>
struct mxc_i2c_regs {
uint32_t iadr;
@ -56,17 +55,14 @@ struct mxc_i2c_regs {
#define I2SR_ICF (1 << 7)
#define I2SR_IBB (1 << 5)
#define I2SR_IAL (1 << 4)
#define I2SR_IIF (1 << 1)
#define I2SR_RX_NO_AK (1 << 0)
#ifdef CONFIG_SYS_I2C_BASE
#define I2C_BASE CONFIG_SYS_I2C_BASE
#else
#if defined(CONFIG_HARD_I2C) && !defined(CONFIG_SYS_I2C_BASE)
#error "define CONFIG_SYS_I2C_BASE to use the mxc_i2c driver"
#endif
#define I2C_MAX_TIMEOUT 10000
static u16 i2c_clk_div[50][2] = {
{ 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 },
{ 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 },
@ -117,46 +113,29 @@ static uint8_t i2c_imx_get_clk(unsigned int rate)
}
/*
* Reset I2C Controller
* Set I2C Bus speed
*/
void i2c_reset(void)
int bus_i2c_set_bus_speed(void *base, int speed)
{
struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
writeb(0, &i2c_regs->i2cr); /* Reset module */
writeb(0, &i2c_regs->i2sr);
}
/*
* Init I2C Bus
*/
void i2c_init(int speed, int unused)
{
struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)base;
u8 clk_idx = i2c_imx_get_clk(speed);
u8 idx = i2c_clk_div[clk_idx][1];
/* Store divider value */
writeb(idx, &i2c_regs->ifdr);
i2c_reset();
}
/*
* Set I2C Speed
*/
int i2c_set_bus_speed(unsigned int speed)
{
i2c_init(speed, 0);
/* Reset module */
writeb(0, &i2c_regs->i2cr);
writeb(0, &i2c_regs->i2sr);
return 0;
}
/*
* Get I2C Speed
*/
unsigned int i2c_get_bus_speed(void)
unsigned int bus_i2c_get_bus_speed(void *base)
{
struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)base;
u8 clk_idx = readb(&i2c_regs->ifdr);
u8 clk_div;
@ -166,210 +145,163 @@ unsigned int i2c_get_bus_speed(void)
return mxc_get_clock(MXC_IPG_PERCLK) / i2c_clk_div[clk_div][0];
}
/*
* Wait for bus to be busy (or free if for_busy = 0)
*
* for_busy = 1: Wait for IBB to be asserted
* for_busy = 0: Wait for IBB to be de-asserted
*/
int i2c_imx_bus_busy(int for_busy)
#define ST_BUS_IDLE (0 | (I2SR_IBB << 8))
#define ST_BUS_BUSY (I2SR_IBB | (I2SR_IBB << 8))
#define ST_IIF (I2SR_IIF | (I2SR_IIF << 8))
static int wait_for_sr_state(struct mxc_i2c_regs *i2c_regs, unsigned state)
{
struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
unsigned int temp;
int timeout = I2C_MAX_TIMEOUT;
while (timeout--) {
temp = readb(&i2c_regs->i2sr);
if (for_busy && (temp & I2SR_IBB))
return 0;
if (!for_busy && !(temp & I2SR_IBB))
return 0;
udelay(1);
}
return 1;
}
/*
* Wait for transaction to complete
*/
int i2c_imx_trx_complete(void)
{
struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
int timeout = I2C_MAX_TIMEOUT;
while (timeout--) {
if (readb(&i2c_regs->i2sr) & I2SR_IIF) {
writeb(0, &i2c_regs->i2sr);
return 0;
unsigned sr;
ulong elapsed;
ulong start_time = get_timer(0);
for (;;) {
sr = readb(&i2c_regs->i2sr);
if (sr & I2SR_IAL) {
writeb(sr & ~I2SR_IAL, &i2c_regs->i2sr);
printf("%s: Arbitration lost sr=%x cr=%x state=%x\n",
__func__, sr, readb(&i2c_regs->i2cr), state);
return -ERESTART;
}
udelay(1);
if ((sr & (state >> 8)) == (unsigned char)state)
return sr;
WATCHDOG_RESET();
elapsed = get_timer(start_time);
if (elapsed > (CONFIG_SYS_HZ / 10)) /* .1 seconds */
break;
}
printf("%s: failed sr=%x cr=%x state=%x\n", __func__,
sr, readb(&i2c_regs->i2cr), state);
return -ETIMEDOUT;
}
return 1;
static int tx_byte(struct mxc_i2c_regs *i2c_regs, u8 byte)
{
int ret;
writeb(0, &i2c_regs->i2sr);
writeb(byte, &i2c_regs->i2dr);
ret = wait_for_sr_state(i2c_regs, ST_IIF);
if (ret < 0)
return ret;
if (ret & I2SR_RX_NO_AK)
return -ENODEV;
return 0;
}
/*
* Check if the transaction was ACKed
* Stop I2C transaction
*/
int i2c_imx_acked(void)
static void i2c_imx_stop(struct mxc_i2c_regs *i2c_regs)
{
struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
int ret;
unsigned int temp = readb(&i2c_regs->i2cr);
return readb(&i2c_regs->i2sr) & I2SR_RX_NO_AK;
temp &= ~(I2CR_MSTA | I2CR_MTX);
writeb(temp, &i2c_regs->i2cr);
ret = wait_for_sr_state(i2c_regs, ST_BUS_IDLE);
if (ret < 0)
printf("%s:trigger stop failed\n", __func__);
}
/*
* Start the controller
* Send start signal, chip address and
* write register address
*/
int i2c_imx_start(void)
static int i2c_init_transfer_(struct mxc_i2c_regs *i2c_regs,
uchar chip, uint addr, int alen)
{
struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
unsigned int temp = 0;
int result;
unsigned int temp;
int ret;
/* Enable I2C controller */
if (!(readb(&i2c_regs->i2cr) & I2CR_IEN)) {
writeb(I2CR_IEN, &i2c_regs->i2cr);
/* Wait for controller to be stable */
udelay(50);
}
if (readb(&i2c_regs->iadr) == (chip << 1))
writeb((chip << 1) ^ 2, &i2c_regs->iadr);
writeb(0, &i2c_regs->i2sr);
writeb(I2CR_IEN, &i2c_regs->i2cr);
/* Wait controller to be stable */
udelay(50);
ret = wait_for_sr_state(i2c_regs, ST_BUS_IDLE);
if (ret < 0)
return ret;
/* Start I2C transaction */
temp = readb(&i2c_regs->i2cr);
temp |= I2CR_MSTA;
writeb(temp, &i2c_regs->i2cr);
result = i2c_imx_bus_busy(1);
if (result)
return result;
ret = wait_for_sr_state(i2c_regs, ST_BUS_BUSY);
if (ret < 0)
return ret;
temp |= I2CR_MTX | I2CR_TX_NO_AK;
writeb(temp, &i2c_regs->i2cr);
/* write slave address */
ret = tx_byte(i2c_regs, chip << 1);
if (ret < 0)
return ret;
while (alen--) {
ret = tx_byte(i2c_regs, (addr >> (alen * 8)) & 0xff);
if (ret < 0)
return ret;
}
return 0;
}
/*
* Stop the controller
*/
void i2c_imx_stop(void)
static int i2c_idle_bus(void *base);
static int i2c_init_transfer(struct mxc_i2c_regs *i2c_regs,
uchar chip, uint addr, int alen)
{
struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
unsigned int temp = 0;
/* Stop I2C transaction */
temp = readb(&i2c_regs->i2cr);
temp |= ~(I2CR_MSTA | I2CR_MTX);
writeb(temp, &i2c_regs->i2cr);
i2c_imx_bus_busy(0);
/* Disable I2C controller */
writeb(0, &i2c_regs->i2cr);
}
/*
* Set chip address and access mode
*
* read = 1: READ access
* read = 0: WRITE access
*/
int i2c_imx_set_chip_addr(uchar chip, int read)
{
struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
int retry;
int ret;
for (retry = 0; retry < 3; retry++) {
ret = i2c_init_transfer_(i2c_regs, chip, addr, alen);
if (ret >= 0)
return 0;
i2c_imx_stop(i2c_regs);
if (ret == -ENODEV)
return ret;
writeb((chip << 1) | read, &i2c_regs->i2dr);
ret = i2c_imx_trx_complete();
if (ret)
return ret;
ret = i2c_imx_acked();
if (ret)
return ret;
return ret;
}
/*
* Write register address
*/
int i2c_imx_set_reg_addr(uint addr, int alen)
{
struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
int ret = 0;
while (alen--) {
writeb((addr >> (alen * 8)) & 0xff, &i2c_regs->i2dr);
ret = i2c_imx_trx_complete();
if (ret)
break;
ret = i2c_imx_acked();
if (ret)
printf("%s: failed for chip 0x%x retry=%d\n", __func__, chip,
retry);
if (ret != -ERESTART)
writeb(0, &i2c_regs->i2cr); /* Disable controller */
udelay(100);
if (i2c_idle_bus(i2c_regs) < 0)
break;
}
return ret;
}
/*
* Try if a chip add given address responds (probe the chip)
*/
int i2c_probe(uchar chip)
{
int ret;
ret = i2c_imx_start();
if (ret)
return ret;
ret = i2c_imx_set_chip_addr(chip, 0);
if (ret)
return ret;
i2c_imx_stop();
printf("%s: give up i2c_regs=%p\n", __func__, i2c_regs);
return ret;
}
/*
* Read data from I2C device
*/
int i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len)
int bus_i2c_read(void *base, uchar chip, uint addr, int alen, uchar *buf,
int len)
{
struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
int ret;
unsigned int temp;
int i;
struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)base;
ret = i2c_imx_start();
if (ret)
return ret;
/* write slave address */
ret = i2c_imx_set_chip_addr(chip, 0);
if (ret)
return ret;
ret = i2c_imx_set_reg_addr(addr, alen);
if (ret)
ret = i2c_init_transfer(i2c_regs, chip, addr, alen);
if (ret < 0)
return ret;
temp = readb(&i2c_regs->i2cr);
temp |= I2CR_RSTA;
writeb(temp, &i2c_regs->i2cr);
ret = i2c_imx_set_chip_addr(chip, 1);
if (ret)
ret = tx_byte(i2c_regs, (chip << 1) | 1);
if (ret < 0) {
i2c_imx_stop(i2c_regs);
return ret;
}
/* setup bus to read data */
temp = readb(&i2c_regs->i2cr);
@ -377,73 +309,192 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len)
if (len == 1)
temp |= I2CR_TX_NO_AK;
writeb(temp, &i2c_regs->i2cr);
readb(&i2c_regs->i2dr);
writeb(0, &i2c_regs->i2sr);
readb(&i2c_regs->i2dr); /* dummy read to clear ICF */
/* read data */
for (i = 0; i < len; i++) {
ret = i2c_imx_trx_complete();
if (ret)
ret = wait_for_sr_state(i2c_regs, ST_IIF);
if (ret < 0) {
i2c_imx_stop(i2c_regs);
return ret;
}
/*
* It must generate STOP before read I2DR to prevent
* controller from generating another clock cycle
*/
if (i == (len - 1)) {
temp = readb(&i2c_regs->i2cr);
temp &= ~(I2CR_MSTA | I2CR_MTX);
writeb(temp, &i2c_regs->i2cr);
i2c_imx_bus_busy(0);
i2c_imx_stop(i2c_regs);
} else if (i == (len - 2)) {
temp = readb(&i2c_regs->i2cr);
temp |= I2CR_TX_NO_AK;
writeb(temp, &i2c_regs->i2cr);
}
writeb(0, &i2c_regs->i2sr);
buf[i] = readb(&i2c_regs->i2dr);
}
i2c_imx_stop();
return ret;
i2c_imx_stop(i2c_regs);
return 0;
}
/*
* Write data to I2C device
*/
int i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len)
int bus_i2c_write(void *base, uchar chip, uint addr, int alen,
const uchar *buf, int len)
{
struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
int ret;
int i;
struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)base;
ret = i2c_imx_start();
if (ret)
return ret;
/* write slave address */
ret = i2c_imx_set_chip_addr(chip, 0);
if (ret)
return ret;
ret = i2c_imx_set_reg_addr(addr, alen);
if (ret)
ret = i2c_init_transfer(i2c_regs, chip, addr, alen);
if (ret < 0)
return ret;
for (i = 0; i < len; i++) {
writeb(buf[i], &i2c_regs->i2dr);
ret = i2c_imx_trx_complete();
if (ret)
return ret;
ret = i2c_imx_acked();
if (ret)
return ret;
ret = tx_byte(i2c_regs, buf[i]);
if (ret < 0)
break;
}
i2c_imx_stop();
i2c_imx_stop(i2c_regs);
return ret;
}
#endif /* CONFIG_HARD_I2C */
struct i2c_parms {
void *base;
void *idle_bus_data;
int (*idle_bus_fn)(void *p);
};
struct sram_data {
unsigned curr_i2c_bus;
struct i2c_parms i2c_data[3];
};
/*
* For SPL boot some boards need i2c before SDRAM is initialized so force
* variables to live in SRAM
*/
static struct sram_data __attribute__((section(".data"))) srdata;
void *get_base(void)
{
#ifdef CONFIG_SYS_I2C_BASE
#ifdef CONFIG_I2C_MULTI_BUS
void *ret = srdata.i2c_data[srdata.curr_i2c_bus].base;
if (ret)
return ret;
#endif
return (void *)CONFIG_SYS_I2C_BASE;
#elif defined(CONFIG_I2C_MULTI_BUS)
return srdata.i2c_data[srdata.curr_i2c_bus].base;
#else
return srdata.i2c_data[0].base;
#endif
}
static struct i2c_parms *i2c_get_parms(void *base)
{
int i = 0;
struct i2c_parms *p = srdata.i2c_data;
while (i < ARRAY_SIZE(srdata.i2c_data)) {
if (p->base == base)
return p;
p++;
i++;
}
printf("Invalid I2C base: %p\n", base);
return NULL;
}
static int i2c_idle_bus(void *base)
{
struct i2c_parms *p = i2c_get_parms(base);
if (p && p->idle_bus_fn)
return p->idle_bus_fn(p->idle_bus_data);
return 0;
}
#ifdef CONFIG_I2C_MULTI_BUS
unsigned int i2c_get_bus_num(void)
{
return srdata.curr_i2c_bus;
}
int i2c_set_bus_num(unsigned bus_idx)
{
if (bus_idx >= ARRAY_SIZE(srdata.i2c_data))
return -1;
if (!srdata.i2c_data[bus_idx].base)
return -1;
srdata.curr_i2c_bus = bus_idx;
return 0;
}
#endif
int i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len)
{
return bus_i2c_read(get_base(), chip, addr, alen, buf, len);
}
int i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len)
{
return bus_i2c_write(get_base(), chip, addr, alen, buf, len);
}
/*
* Test if a chip at a given address responds (probe the chip)
*/
int i2c_probe(uchar chip)
{
return bus_i2c_write(get_base(), chip, 0, 0, NULL, 0);
}
void bus_i2c_init(void *base, int speed, int unused,
int (*idle_bus_fn)(void *p), void *idle_bus_data)
{
int i = 0;
struct i2c_parms *p = srdata.i2c_data;
if (!base)
return;
for (;;) {
if (!p->base || (p->base == base)) {
p->base = base;
if (idle_bus_fn) {
p->idle_bus_fn = idle_bus_fn;
p->idle_bus_data = idle_bus_data;
}
break;
}
p++;
i++;
if (i >= ARRAY_SIZE(srdata.i2c_data))
return;
}
bus_i2c_set_bus_speed(base, speed);
}
/*
* Init I2C Bus
*/
void i2c_init(int speed, int unused)
{
bus_i2c_init(get_base(), speed, unused, NULL, NULL);
}
/*
* Set I2C Speed
*/
int i2c_set_bus_speed(unsigned int speed)
{
return bus_i2c_set_bus_speed(get_base(), speed);
}
/*
* Get I2C Speed
*/
unsigned int i2c_get_bus_speed(void)
{
return bus_i2c_get_bus_speed(get_base());
}

221
drivers/i2c/s3c24x0_i2c.c
View file

@ -27,10 +27,15 @@
*/
#include <common.h>
#ifdef CONFIG_EXYNOS5
#include <asm/arch/clk.h>
#include <asm/arch/cpu.h>
#else
#include <asm/arch/s3c24x0_cpu.h>
#endif
#include <asm/io.h>
#include <i2c.h>
#include "s3c24x0_i2c.h"
#ifdef CONFIG_HARD_I2C
@ -45,6 +50,7 @@
#define I2CSTAT_BSY 0x20 /* Busy bit */
#define I2CSTAT_NACK 0x01 /* Nack bit */
#define I2CCON_ACKGEN 0x80 /* Acknowledge generation */
#define I2CCON_IRPND 0x10 /* Interrupt pending bit */
#define I2C_MODE_MT 0xC0 /* Master Transmit Mode */
#define I2C_MODE_MR 0x80 /* Master Receive Mode */
@ -53,6 +59,10 @@
#define I2C_TIMEOUT 1 /* 1 second */
static unsigned int g_current_bus; /* Stores Current I2C Bus */
#ifndef CONFIG_EXYNOS5
static int GetI2CSDA(void)
{
struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
@ -77,16 +87,17 @@ static void SetI2CSCL(int x)
struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
#ifdef CONFIG_S3C2410
writel((readl(&gpio->gpedat) & ~0x4000) | (x & 1) << 14, &gpio->gpedat);
writel((readl(&gpio->gpedat) & ~0x4000) |
(x & 1) << 14, &gpio->gpedat);
#endif
#ifdef CONFIG_S3C2400
writel((readl(&gpio->pgdat) & ~0x0040) | (x & 1) << 6, &gpio->pgdat);
#endif
}
#endif
static int WaitForXfer(void)
static int WaitForXfer(struct s3c24x0_i2c *i2c)
{
struct s3c24x0_i2c *i2c = s3c24x0_get_base_i2c();
int i;
i = I2C_TIMEOUT * 10000;
@ -98,35 +109,102 @@ static int WaitForXfer(void)
return (readl(&i2c->iiccon) & I2CCON_IRPND) ? I2C_OK : I2C_NOK_TOUT;
}
static int IsACK(void)
static int IsACK(struct s3c24x0_i2c *i2c)
{
struct s3c24x0_i2c *i2c = s3c24x0_get_base_i2c();
return !(readl(&i2c->iicstat) & I2CSTAT_NACK);
}
static void ReadWriteByte(void)
static void ReadWriteByte(struct s3c24x0_i2c *i2c)
{
struct s3c24x0_i2c *i2c = s3c24x0_get_base_i2c();
writel(readl(&i2c->iiccon) & ~I2CCON_IRPND, &i2c->iiccon);
}
static struct s3c24x0_i2c *get_base_i2c(void)
{
#ifdef CONFIG_EXYNOS5
struct s3c24x0_i2c *i2c = (struct s3c24x0_i2c *)(samsung_get_base_i2c()
+ (EXYNOS5_I2C_SPACING
* g_current_bus));
return i2c;
#else
return s3c24x0_get_base_i2c();
#endif
}
static void i2c_ch_init(struct s3c24x0_i2c *i2c, int speed, int slaveadd)
{
ulong freq, pres = 16, div;
#ifdef CONFIG_EXYNOS5
freq = get_i2c_clk();
#else
freq = get_PCLK();
#endif
/* calculate prescaler and divisor values */
if ((freq / pres / (16 + 1)) > speed)
/* set prescaler to 512 */
pres = 512;
div = 0;
while ((freq / pres / (div + 1)) > speed)
div++;
/* set prescaler, divisor according to freq, also set ACKGEN, IRQ */
writel((div & 0x0F) | 0xA0 | ((pres == 512) ? 0x40 : 0), &i2c->iiccon);
/* init to SLAVE REVEIVE and set slaveaddr */
writel(0, &i2c->iicstat);
writel(slaveadd, &i2c->iicadd);
/* program Master Transmit (and implicit STOP) */
writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->iicstat);
}
/*
* MULTI BUS I2C support
*/
#ifdef CONFIG_I2C_MULTI_BUS
int i2c_set_bus_num(unsigned int bus)
{
struct s3c24x0_i2c *i2c;
if ((bus < 0) || (bus >= CONFIG_MAX_I2C_NUM)) {
debug("Bad bus: %d\n", bus);
return -1;
}
g_current_bus = bus;
i2c = get_base_i2c();
i2c_ch_init(i2c, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
return 0;
}
unsigned int i2c_get_bus_num(void)
{
return g_current_bus;
}
#endif
void i2c_init(int speed, int slaveadd)
{
struct s3c24x0_i2c *i2c = s3c24x0_get_base_i2c();
struct s3c24x0_i2c *i2c;
#ifndef CONFIG_EXYNOS5
struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
ulong freq, pres = 16, div;
#endif
int i;
/* wait for some time to give previous transfer a chance to finish */
/* By default i2c channel 0 is the current bus */
g_current_bus = 0;
i2c = get_base_i2c();
/* wait for some time to give previous transfer a chance to finish */
i = I2C_TIMEOUT * 1000;
while ((readl(&i2c->iicstat) && I2CSTAT_BSY) && (i > 0)) {
while ((readl(&i2c->iicstat) & I2CSTAT_BSY) && (i > 0)) {
udelay(1000);
i--;
}
#ifndef CONFIG_EXYNOS5
if ((readl(&i2c->iicstat) & I2CSTAT_BSY) || GetI2CSDA() == 0) {
#ifdef CONFIG_S3C2410
ulong old_gpecon = readl(&gpio->gpecon);
@ -170,27 +248,8 @@ void i2c_init(int speed, int slaveadd)
writel(old_gpecon, &gpio->pgcon);
#endif
}
/* calculate prescaler and divisor values */
freq = get_PCLK();
if ((freq / pres / (16 + 1)) > speed)
/* set prescaler to 512 */
pres = 512;
div = 0;
while ((freq / pres / (div + 1)) > speed)
div++;
/* set prescaler, divisor according to freq, also set
* ACKGEN, IRQ */
writel((div & 0x0F) | 0xA0 | ((pres == 512) ? 0x40 : 0), &i2c->iiccon);
/* init to SLAVE REVEIVE and set slaveaddr */
writel(0, &i2c->iicstat);
writel(slaveadd, &i2c->iicadd);
/* program Master Transmit (and implicit STOP) */
writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->iicstat);
#endif /* #ifndef CONFIG_EXYNOS5 */
i2c_ch_init(i2c, speed, slaveadd);
}
/*
@ -200,19 +259,19 @@ void i2c_init(int speed, int slaveadd)
* by the char, we could make it larger if needed. If it is
* 0 we skip the address write cycle.
*/
static
int i2c_transfer(unsigned char cmd_type,
unsigned char chip,
unsigned char addr[],
unsigned char addr_len,
unsigned char data[], unsigned short data_len)
static int i2c_transfer(struct s3c24x0_i2c *i2c,
unsigned char cmd_type,
unsigned char chip,
unsigned char addr[],
unsigned char addr_len,
unsigned char data[],
unsigned short data_len)
{
struct s3c24x0_i2c *i2c = s3c24x0_get_base_i2c();
int i, result;
if (data == 0 || data_len == 0) {
/*Don't support data transfer of no length or to address 0 */
printf("i2c_transfer: bad call\n");
debug("i2c_transfer: bad call\n");
return I2C_NOK;
}
@ -226,7 +285,7 @@ int i2c_transfer(unsigned char cmd_type,
if (readl(&i2c->iicstat) & I2CSTAT_BSY)
return I2C_NOK_TOUT;
writel(readl(&i2c->iiccon) | 0x80, &i2c->iiccon);
writel(readl(&i2c->iiccon) | I2CCON_ACKGEN, &i2c->iiccon);
result = I2C_OK;
switch (cmd_type) {
@ -238,16 +297,16 @@ int i2c_transfer(unsigned char cmd_type,
&i2c->iicstat);
i = 0;
while ((i < addr_len) && (result == I2C_OK)) {
result = WaitForXfer();
result = WaitForXfer(i2c);
writel(addr[i], &i2c->iicds);
ReadWriteByte();
ReadWriteByte(i2c);
i++;
}
i = 0;
while ((i < data_len) && (result == I2C_OK)) {
result = WaitForXfer();
result = WaitForXfer(i2c);
writel(data[i], &i2c->iicds);
ReadWriteByte();
ReadWriteByte(i2c);
i++;
}
} else {
@ -257,19 +316,19 @@ int i2c_transfer(unsigned char cmd_type,
&i2c->iicstat);
i = 0;
while ((i < data_len) && (result = I2C_OK)) {
result = WaitForXfer();
result = WaitForXfer(i2c);
writel(data[i], &i2c->iicds);
ReadWriteByte();
ReadWriteByte(i2c);
i++;
}
}
if (result == I2C_OK)
result = WaitForXfer();
result = WaitForXfer(i2c);
/* send STOP */
writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat);
ReadWriteByte();
ReadWriteByte(i2c);
break;
case I2C_READ:
@ -279,13 +338,13 @@ int i2c_transfer(unsigned char cmd_type,
/* send START */
writel(readl(&i2c->iicstat) | I2C_START_STOP,
&i2c->iicstat);
result = WaitForXfer();
if (IsACK()) {
result = WaitForXfer(i2c);
if (IsACK(i2c)) {
i = 0;
while ((i < addr_len) && (result == I2C_OK)) {
writel(addr[i], &i2c->iicds);
ReadWriteByte();
result = WaitForXfer();
ReadWriteByte(i2c);
result = WaitForXfer(i2c);
i++;
}
@ -293,16 +352,17 @@ int i2c_transfer(unsigned char cmd_type,
/* resend START */
writel(I2C_MODE_MR | I2C_TXRX_ENA |
I2C_START_STOP, &i2c->iicstat);
ReadWriteByte();
result = WaitForXfer();
ReadWriteByte(i2c);
result = WaitForXfer(i2c);
i = 0;
while ((i < data_len) && (result == I2C_OK)) {
/* disable ACK for final READ */
if (i == data_len - 1)
writel(readl(&i2c->iiccon)
& ~0x80, &i2c->iiccon);
ReadWriteByte();
result = WaitForXfer();
& ~I2CCON_ACKGEN,
&i2c->iiccon);
ReadWriteByte(i2c);
result = WaitForXfer(i2c);
data[i] = readl(&i2c->iicds);
i++;
}
@ -316,17 +376,18 @@ int i2c_transfer(unsigned char cmd_type,
/* send START */
writel(readl(&i2c->iicstat) | I2C_START_STOP,
&i2c->iicstat);
result = WaitForXfer();
result = WaitForXfer(i2c);
if (IsACK()) {
if (IsACK(i2c)) {
i = 0;
while ((i < data_len) && (result == I2C_OK)) {
/* disable ACK for final READ */
if (i == data_len - 1)
writel(readl(&i2c->iiccon) &
~0x80, &i2c->iiccon);
ReadWriteByte();
result = WaitForXfer();
~I2CCON_ACKGEN,
&i2c->iiccon);
ReadWriteByte(i2c);
result = WaitForXfer(i2c);
data[i] = readl(&i2c->iicds);
i++;
}
@ -337,22 +398,24 @@ int i2c_transfer(unsigned char cmd_type,
/* send STOP */
writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat);
ReadWriteByte();
ReadWriteByte(i2c);
break;
default:
printf("i2c_transfer: bad call\n");
debug("i2c_transfer: bad call\n");
result = I2C_NOK;
break;
}
return (result);
return result;
}
int i2c_probe(uchar chip)
{
struct s3c24x0_i2c *i2c;
uchar buf[1];
i2c = get_base_i2c();
buf[0] = 0;
/*
@ -360,16 +423,17 @@ int i2c_probe(uchar chip)
* address was <ACK>ed (i.e. there was a chip at that address which
* drove the data line low).
*/
return i2c_transfer(I2C_READ, chip << 1, 0, 0, buf, 1) != I2C_OK;
return i2c_transfer(i2c, I2C_READ, chip << 1, 0, 0, buf, 1) != I2C_OK;
}
int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
{
struct s3c24x0_i2c *i2c;
uchar xaddr[4];
int ret;
if (alen > 4) {
printf("I2C read: addr len %d not supported\n", alen);
debug("I2C read: addr len %d not supported\n", alen);
return 1;
}
@ -396,10 +460,11 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
chip |= ((addr >> (alen * 8)) &
CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
#endif
if ((ret =
i2c_transfer(I2C_READ, chip << 1, &xaddr[4 - alen], alen,
buffer, len)) != 0) {
printf("I2c read: failed %d\n", ret);
i2c = get_base_i2c();
ret = i2c_transfer(i2c, I2C_READ, chip << 1, &xaddr[4 - alen], alen,
buffer, len);
if (ret != 0) {
debug("I2c read: failed %d\n", ret);
return 1;
}
return 0;
@ -407,10 +472,11 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
{
struct s3c24x0_i2c *i2c;
uchar xaddr[4];
if (alen > 4) {
printf("I2C write: addr len %d not supported\n", alen);
debug("I2C write: addr len %d not supported\n", alen);
return 1;
}
@ -436,8 +502,9 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
chip |= ((addr >> (alen * 8)) &
CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
#endif
i2c = get_base_i2c();
return (i2c_transfer
(I2C_WRITE, chip << 1, &xaddr[4 - alen], alen, buffer,
(i2c, I2C_WRITE, chip << 1, &xaddr[4 - alen], alen, buffer,
len) != 0);
}
#endif /* CONFIG_HARD_I2C */

33
drivers/i2c/s3c24x0_i2c.h Normal file
View file

@ -0,0 +1,33 @@
/*
* Copyright (C) 2012 Samsung Electronics
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _S3C24X0_I2C_H
#define _S3C24X0_I2C_H
struct s3c24x0_i2c {
u32 iiccon;
u32 iicstat;
u32 iicadd;
u32 iicds;
u32 iiclc;
};
#endif /* _S3C24X0_I2C_H */

2
drivers/usb/host/ehci-mx6.c
View file

@ -22,7 +22,7 @@
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
#include <asm/arch/mx6x_pins.h>
#include <asm/arch/iomux-v3.h>
#include <asm/imx-common/iomux-v3.h>
#include "ehci.h"
#include "ehci-core.h"

6
include/configs/mx6qsabrelite.h
View file

@ -60,11 +60,9 @@
/* I2C Configs */
#define CONFIG_CMD_I2C
#define CONFIG_HARD_I2C
#define CONFIG_I2C_MULTI_BUS
#define CONFIG_I2C_MXC
#define CONFIG_SYS_I2C_BASE I2C3_BASE_ADDR
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_SYS_I2C_SLAVE 0xfe
#define CONFIG_SYS_I2C_SPEED 100000
/* MMC Configs */
#define CONFIG_FSL_ESDHC

10
include/configs/smdk5250.h
View file

@ -193,6 +193,16 @@
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - 0x1000000)
/* I2C */
#define CONFIG_SYS_I2C_INIT_BOARD
#define CONFIG_HARD_I2C
#define CONFIG_CMD_I2C
#define CONFIG_SYS_I2C_SPEED 100000 /* 100 Kbps */
#define CONFIG_DRIVER_S3C24X0_I2C
#define CONFIG_I2C_MULTI_BUS
#define CONFIG_MAX_I2C_NUM 8
#define CONFIG_SYS_I2C_SLAVE 0x0
/* Ethernet Controllor Driver */
#ifdef CONFIG_CMD_NET
#define CONFIG_SMC911X