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sifive_cache: add flush_range func in sifive cache driver
Signed-off-by: Wei Fu <wefu@redhat.com>
This commit is contained in:
parent
28db513a7d
commit
954644d8f5
2 changed files with 81 additions and 1 deletions
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@ -25,3 +25,24 @@ void enable_caches(void)
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log_debug("ccache enable failed");
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}
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}
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void flush_dcache_range(unsigned long start, unsigned long end)
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{
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struct udevice *dev;
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int ret;
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/* Enable ways of ccache */
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ret = uclass_get_device_by_driver(UCLASS_CACHE,
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DM_DRIVER_GET(sifive_ccache),
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&dev);
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if (ret) {
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log_debug("Cannot flush dcache in %p - %p",
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(void *)start, (void *)end);
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} else {
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ret = flush_range(dev, start, end);
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if (ret)
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log_debug("ccache flush failed in %p - %p",
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(void *)start, (void *)end);
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}
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}
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61
drivers/cache/cache-sifive-ccache.c
vendored
61
drivers/cache/cache-sifive-ccache.c
vendored
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@ -7,16 +7,22 @@
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#include <cache.h>
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#include <dm.h>
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#include <asm/io.h>
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#include <dm/device.h>
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#include <linux/bitfield.h>
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#include <fdt_support.h>
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#define SIFIVE_CCACHE_CONFIG 0x000
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#define SIFIVE_CCACHE_CONFIG_WAYS GENMASK(15, 8)
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#define SIFIVE_CCACHE_WAY_ENABLE 0x008
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#define SIFIVE_CCACHE_FLUSH64 0x200
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static bool range_check = false;
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struct sifive_ccache {
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void __iomem *base;
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int cache_line_size;
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phys_addr_t flush_start; /* Start physical address of flush range limit. */
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phys_addr_t flush_end; /* End physical address of flush range limit. */
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};
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static int sifive_ccache_enable(struct udevice *dev)
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@ -43,19 +49,72 @@ static int sifive_ccache_get_info(struct udevice *dev, struct cache_info *info)
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return 0;
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}
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static int sifive_ccache_flush_range(struct udevice *dev,
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unsigned long start, unsigned long end)
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{
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unsigned long line;
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volatile unsigned long *flush64;
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struct sifive_ccache *priv = dev_get_priv(dev);
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if (range_check) {
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/* make sure the address is in the range */
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if(start > end ||
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start < priv->flush_start || end > priv->flush_end)
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return -EINVAL;
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} else {
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pr_warn("skip checking range.");
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}
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/* make sure we won't get into infinite loop below */
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if (!priv->cache_line_size) {
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pr_warn("missing cache_line_size, skip flush.");
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return -EINVAL;
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}
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flush64 = (volatile unsigned long *)(priv->base + SIFIVE_CCACHE_FLUSH64);
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/* memory barrier */
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mb();
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for (line = start; line < end; line += priv->cache_line_size)
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(*flush64) = line;
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/* memory barrier */
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mb();
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return 0;
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}
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static const struct cache_ops sifive_ccache_ops = {
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.enable = sifive_ccache_enable,
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.get_info = sifive_ccache_get_info,
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.flush_range = sifive_ccache_flush_range,
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};
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static int sifive_ccache_probe(struct udevice *dev)
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{
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int ret;
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uint64_t addr, len;
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struct sifive_ccache *priv = dev_get_priv(dev);
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priv->base = dev_read_addr_ptr(dev);
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if (!priv->base)
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return -EINVAL;
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priv->cache_line_size =
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dev_read_u32_default(dev, "cache-line-size",
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CONFIG_SYS_CACHELINE_SIZE);
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/* only read range index 0 */
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ret = fdt_read_range((void *)gd->fdt_blob, dev_of_offset(dev), 0,
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NULL, &addr, &len);
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if (ret) {
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pr_warn("missing flush range, ignore range check.");
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return 0;
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}
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range_check = true;
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priv->flush_start = addr;
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priv->flush_end = addr + len - 1;
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return 0;
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}
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