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arm, davinci: Remove the duplication of LPSC functions
The LPSC functions defined in arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c are replaced by those already defined in arch/arm/cpu/arm926ejs/davinci/psc.c. Signed-off-by: Christian Riesch <christian.riesch@omicron.at> Cc: Heiko Schocher <hs@denx.de> Cc: Paulraj Sandeep <s-paulraj@ti.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Acked-by: Heiko Schocher <hs@denx.de> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
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1 changed files with 4 additions and 92 deletions
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@ -153,49 +153,12 @@ int da850_pll_init(struct davinci_pllc_regs *reg, unsigned long pllmult)
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return 0;
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}
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void da850_lpc_transition(unsigned char pscnum, unsigned char module,
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unsigned char domain, unsigned char state)
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{
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struct davinci_psc_regs *reg;
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dv_reg_p mdstat, mdctl;
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if (pscnum == 0) {
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reg = davinci_psc0_regs;
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mdstat = ®->psc0.mdstat[module];
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mdctl = ®->psc0.mdctl[module];
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} else {
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reg = davinci_psc1_regs;
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mdstat = ®->psc1.mdstat[module];
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mdctl = ®->psc1.mdctl[module];
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}
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/* Wait for any outstanding transition to complete */
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while ((readl(®->ptstat) & (0x00000001 << domain)))
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;
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/* If we are already in that state, just return */
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if ((readl(mdstat) & 0x1F) == state)
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return;
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/* Perform transition */
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writel((readl(mdctl) & 0xFFFFFFE0) | state, mdctl);
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setbits_le32(®->ptcmd, (0x00000001 << domain));
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/* Wait for transition to complete */
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while (readl(®->ptstat) & (0x00000001 << domain))
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;
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/* Wait and verify the state */
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while ((readl(mdstat) & 0x1F) != state)
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;
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}
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int da850_ddr_setup(unsigned int freq)
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{
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unsigned long tmp;
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/* Enable the Clock to DDR2/mDDR */
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da850_lpc_transition(1, 6, 0, PSC_ENABLE);
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lpsc_on(DAVINCI_LPSC_DDR_EMIF);
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tmp = readl(&davinci_syscfg1_regs->vtpio_ctl);
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if ((tmp & VTP_POWERDWN) == VTP_POWERDWN) {
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@ -244,9 +207,9 @@ int da850_ddr_setup(unsigned int freq)
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&dv_ddr2_regs_ctrl->sdrcr);
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/* SyncReset the Clock to EMIF3A SDRAM */
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da850_lpc_transition(1, 6, 0, PSC_SYNCRESET);
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lpsc_syncreset(DAVINCI_LPSC_DDR_EMIF);
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/* Enable the Clock to EMIF3A SDRAM */
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da850_lpc_transition(1, 6, 0, PSC_ENABLE);
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lpsc_on(DAVINCI_LPSC_DDR_EMIF);
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/* disable self refresh */
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clrbits_le32(&dv_ddr2_regs_ctrl->sdrcr, 0xc0000000);
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@ -255,54 +218,6 @@ int da850_ddr_setup(unsigned int freq)
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return 0;
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}
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static void da850_set_mdctl(dv_reg_p mdctl)
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{
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if ((readl(mdctl) & 0x1F) != PSC_ENABLE)
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writel(((readl(mdctl) & 0xFFFFFFE0) | PSC_ENABLE), mdctl);
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}
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void da850_psc_init(void)
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{
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struct davinci_psc_regs *reg;
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int i;
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/* PSC 0 domain 0 init */
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reg = davinci_psc0_regs;
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while ((readl(®->ptstat) & 0x00000001))
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;
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for (i = 3; i <= 4 ; i++)
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da850_set_mdctl(®->psc0.mdctl[i]);
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for (i = 7; i <= 12 ; i++)
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da850_set_mdctl(®->psc0.mdctl[i]);
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/* Do Always-On Power Domain Transitions */
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setbits_le32(®->ptcmd, 0x00000001);
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while (readl(®->ptstat) & 0x00000001)
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;
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/* PSC1, domain 1 init */
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reg = davinci_psc1_regs;
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while ((readl(®->ptstat) & 0x00000001))
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;
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da850_set_mdctl(®->psc1.mdctl[3]);
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da850_set_mdctl(®->psc1.mdctl[6]);
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/* UART1 + UART2 */
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for (i = 12 ; i <= 13 ; i++)
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da850_set_mdctl(®->psc1.mdctl[i]);
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da850_set_mdctl(®->psc1.mdctl[26]);
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da850_set_mdctl(®->psc1.mdctl[31]);
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/* Do Always-On Power Domain Transitions */
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setbits_le32(®->ptcmd, 0x00000001);
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while (readl(®->ptstat) & 0x00000001)
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;
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}
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void da850_pinmux_ctl(unsigned long offset, unsigned long mask,
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unsigned long value)
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{
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@ -368,9 +283,6 @@ int arch_cpu_init(void)
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dv_maskbits(&davinci_syscfg_regs->suspsrc,
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((1 << 27) | (1 << 22) | (1 << 20) | (1 << 5) | (1 << 16)));
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/* System PSC setup - enable all */
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da850_psc_init();
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/* Setup Pinmux */
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da850_pinmux_ctl(0, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX0);
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da850_pinmux_ctl(1, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX1);
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@ -404,7 +316,7 @@ int arch_cpu_init(void)
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writel(CONFIG_SYS_DA850_CS2CFG, &davinci_emif_regs->ab1cr);
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writel(CONFIG_SYS_DA850_CS3CFG, &davinci_emif_regs->ab2cr);
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da850_lpc_transition(1, 13, 0, PSC_ENABLE);
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lpsc_on(DAVINCI_LPSC_UART2);
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NS16550_init((NS16550_t)(CONFIG_SYS_NS16550_COM1),
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CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
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