mirror of
https://github.com/Fishwaldo/u-boot.git
synced 2025-03-18 13:11:31 +00:00
Merge samsung, imx, tegra into u-boot-arm/master
This commit merges branches from samsung, imx and tegra meant to fix merge issues between u-boot/master and u-boot-arm/master, as well as a few manual merge fixes.
This commit is contained in:
commit
96764df1b4
500 changed files with 29214 additions and 3668 deletions
2
.gitignore
vendored
2
.gitignore
vendored
|
@ -38,12 +38,12 @@
|
|||
/u-boot.sha1
|
||||
/u-boot.dis
|
||||
/u-boot.lds
|
||||
/u-boot.lst
|
||||
/u-boot.ubl
|
||||
/u-boot.ais
|
||||
/u-boot.dtb
|
||||
/u-boot.sb
|
||||
/u-boot.geany
|
||||
/include/u-boot.lst
|
||||
|
||||
#
|
||||
# Generated files
|
||||
|
|
|
@ -7,6 +7,10 @@
|
|||
# and Cc: the <u-boot@lists.denx.de> mailing list. #
|
||||
# #
|
||||
# Note: lists sorted by Maintainer Name #
|
||||
# Note: These are the maintainers for specific *boards*. The #
|
||||
# custodians for general architectures and subsystems can #
|
||||
# be found here -- http://www.denx.de/wiki/U-Boot/Custodians #
|
||||
# #
|
||||
#########################################################################
|
||||
|
||||
|
||||
|
@ -388,6 +392,8 @@ Ricardo Ribalda <ricardo.ribalda@uam.es>
|
|||
|
||||
Stefan Roese <sr@denx.de>
|
||||
|
||||
a3m071 MPC5200
|
||||
|
||||
P3M7448 MPC7448
|
||||
|
||||
uc100 MPC857
|
||||
|
@ -800,7 +806,7 @@ Veli-Pekka Peltola <veli-pekka.peltola@bluegiga.com>
|
|||
|
||||
apx4devkit i.MX28
|
||||
|
||||
Luka Perkov <uboot@lukaperkov.net>
|
||||
Luka Perkov <luka@openwrt.org>
|
||||
|
||||
ib62x0 ARM926EJS
|
||||
iconnect ARM926EJS
|
||||
|
|
69
MAKEALL
69
MAKEALL
|
@ -20,6 +20,8 @@ usage()
|
|||
-m, --maintainers List all targets and maintainer email
|
||||
-M, --mails List all targets and all affilated emails
|
||||
-C, --check Enable build checking
|
||||
-n, --continue Continue (skip boards already built)
|
||||
-r, --rebuild-errors Rebuild any boards that errored
|
||||
-h, --help This help output
|
||||
|
||||
Selections by these options are logically ANDed; if the same option
|
||||
|
@ -52,8 +54,8 @@ usage()
|
|||
exit ${ret}
|
||||
}
|
||||
|
||||
SHORT_OPTS="ha:c:v:s:lmMC"
|
||||
LONG_OPTS="help,arch:,cpu:,vendor:,soc:,list,maintainers,mails,check"
|
||||
SHORT_OPTS="ha:c:v:s:lmMCnr"
|
||||
LONG_OPTS="help,arch:,cpu:,vendor:,soc:,list,maintainers,mails,check,continue,rebuild-errors"
|
||||
|
||||
# Option processing based on util-linux-2.13/getopt-parse.bash
|
||||
|
||||
|
@ -73,6 +75,8 @@ SELECTED=''
|
|||
ONLY_LIST=''
|
||||
PRINT_MAINTS=''
|
||||
MAINTAINERS_ONLY=''
|
||||
CONTINUE=''
|
||||
REBUILD_ERRORS=''
|
||||
|
||||
while true ; do
|
||||
case "$1" in
|
||||
|
@ -115,6 +119,12 @@ while true ; do
|
|||
-C|--check)
|
||||
CHECK='C=1'
|
||||
shift ;;
|
||||
-n|--continue)
|
||||
CONTINUE='y'
|
||||
shift ;;
|
||||
-r|--rebuild-errors)
|
||||
REBUILD_ERRORS='y'
|
||||
shift ;;
|
||||
-l|--list)
|
||||
ONLY_LIST='y'
|
||||
shift ;;
|
||||
|
@ -198,7 +208,9 @@ fi
|
|||
OUTPUT_PREFIX="${BUILD_DIR}"
|
||||
|
||||
[ -d ${LOG_DIR} ] || mkdir "${LOG_DIR}" || exit 1
|
||||
find "${LOG_DIR}/" -type f -exec rm -f {} +
|
||||
if [ "$CONTINUE" != 'y' -a "$REBUILD_ERRORS" != 'y' ] ; then
|
||||
find "${LOG_DIR}/" -type f -exec rm -f {} +
|
||||
fi
|
||||
|
||||
LIST=""
|
||||
|
||||
|
@ -208,6 +220,7 @@ ERR_LIST=""
|
|||
WRN_CNT=0
|
||||
WRN_LIST=""
|
||||
TOTAL_CNT=0
|
||||
SKIP_CNT=0
|
||||
CURRENT_CNT=0
|
||||
OLDEST_IDX=1
|
||||
RC=0
|
||||
|
@ -380,6 +393,12 @@ LIST_pxa="$(boards_by_cpu pxa)"
|
|||
|
||||
LIST_ixp="$(boards_by_cpu ixp)"
|
||||
|
||||
#########################################################################
|
||||
## SPEAr Systems
|
||||
#########################################################################
|
||||
|
||||
LIST_spear="$(boards_by_soc spear)"
|
||||
|
||||
#########################################################################
|
||||
## ARM groups
|
||||
#########################################################################
|
||||
|
@ -610,6 +629,13 @@ list_target() {
|
|||
donep="${LOG_DIR}/._done_"
|
||||
skipp="${LOG_DIR}/._skip_"
|
||||
|
||||
build_target_killed() {
|
||||
echo "Aborted $target build."
|
||||
# Remove the logs for this board since it was aborted
|
||||
rm -f ${LOG_DIR}/$target.MAKELOG ${LOG_DIR}/$target.ERR
|
||||
exit
|
||||
}
|
||||
|
||||
build_target() {
|
||||
target=$1
|
||||
build_idx=$2
|
||||
|
@ -622,6 +648,7 @@ build_target() {
|
|||
if [ $BUILD_MANY == 1 ] ; then
|
||||
output_dir="${OUTPUT_PREFIX}/${target}"
|
||||
mkdir -p "${output_dir}"
|
||||
trap build_target_killed TERM
|
||||
else
|
||||
output_dir="${OUTPUT_PREFIX}"
|
||||
fi
|
||||
|
@ -640,6 +667,8 @@ build_target() {
|
|||
fi
|
||||
|
||||
if [ $BUILD_MANY == 1 ] ; then
|
||||
trap - TERM
|
||||
|
||||
${MAKE} -s tidy
|
||||
|
||||
if [ -s ${LOG_DIR}/${target}.ERR ] ; then
|
||||
|
@ -718,10 +747,20 @@ build_targets() {
|
|||
: $((CURRENT_CNT += 1))
|
||||
rm -f "${donep}${TOTAL_CNT}"
|
||||
rm -f "${skipp}${TOTAL_CNT}"
|
||||
if [ $BUILD_MANY == 1 ] ; then
|
||||
build_target ${t} ${TOTAL_CNT} &
|
||||
if [ "$CONTINUE" = 'y' -a -e ${LOG_DIR}/$t.MAKELOG ] ; then
|
||||
: $((SKIP_CNT += 1))
|
||||
touch "${donep}${TOTAL_CNT}"
|
||||
elif [ "$REBUILD_ERRORS" = 'y' -a ! -e ${LOG_DIR}/$t.ERR ] ; then
|
||||
: $((SKIP_CNT += 1))
|
||||
touch "${donep}${TOTAL_CNT}"
|
||||
else
|
||||
build_target ${t} ${TOTAL_CNT}
|
||||
if [ $BUILD_MANY == 1 ] ; then
|
||||
build_target ${t} ${TOTAL_CNT} &
|
||||
else
|
||||
CUR_TGT="${t}"
|
||||
build_target ${t} ${TOTAL_CNT}
|
||||
CUR_TGT=''
|
||||
fi
|
||||
fi
|
||||
fi
|
||||
|
||||
|
@ -745,7 +784,11 @@ build_targets() {
|
|||
#-----------------------------------------------------------------------
|
||||
|
||||
kill_children() {
|
||||
kill -- "-$1"
|
||||
local pgid=`ps -p $$ --no-headers -o "%r" | tr -d ' '`
|
||||
local children=`pgrep -g $pgid | grep -v $$ | grep -v $pgid`
|
||||
|
||||
kill $children 2> /dev/null
|
||||
wait $children 2> /dev/null
|
||||
|
||||
exit
|
||||
}
|
||||
|
@ -753,6 +796,9 @@ kill_children() {
|
|||
print_stats() {
|
||||
if [ "$ONLY_LIST" == 'y' ] ; then return ; fi
|
||||
|
||||
# Only count boards that completed
|
||||
: $((TOTAL_CNT = `find ${skipp}* 2> /dev/null | wc -l`))
|
||||
|
||||
rm -f ${donep}* ${skipp}*
|
||||
|
||||
if [ $BUILD_MANY == 1 ] && [ -e "${OUTPUT_PREFIX}/ERR" ] ; then
|
||||
|
@ -762,10 +808,17 @@ print_stats() {
|
|||
WRN_LIST=`grep -riwL error ${OUTPUT_PREFIX}/ERR/`
|
||||
WRN_LIST=`for f in $WRN_LIST ; do echo -n " $(basename $f)" ; done`
|
||||
WRN_CNT=`echo $WRN_LIST | wc -w | awk '{print $1}'`
|
||||
else
|
||||
# Remove the logs for any board that was interrupted
|
||||
rm -f ${LOG_DIR}/${CUR_TGT}.MAKELOG ${LOG_DIR}/${CUR_TGT}.ERR
|
||||
fi
|
||||
|
||||
: $((TOTAL_CNT -= ${SKIP_CNT}))
|
||||
echo ""
|
||||
echo "--------------------- SUMMARY ----------------------------"
|
||||
if [ "$CONTINUE" = 'y' -o "$REBUILD_ERRORS" = 'y' ] ; then
|
||||
echo "Boards skipped: ${SKIP_CNT}"
|
||||
fi
|
||||
echo "Boards compiled: ${TOTAL_CNT}"
|
||||
if [ ${ERR_CNT} -gt 0 ] ; then
|
||||
echo "Boards with errors: ${ERR_CNT} (${ERR_LIST} )"
|
||||
|
@ -776,7 +829,7 @@ print_stats() {
|
|||
echo "----------------------------------------------------------"
|
||||
|
||||
if [ $BUILD_MANY == 1 ] ; then
|
||||
kill_children $$ &
|
||||
kill_children
|
||||
fi
|
||||
|
||||
exit $RC
|
||||
|
|
64
Makefile
64
Makefile
|
@ -24,7 +24,7 @@
|
|||
VERSION = 2013
|
||||
PATCHLEVEL = 01
|
||||
SUBLEVEL =
|
||||
EXTRAVERSION = -rc1
|
||||
EXTRAVERSION = -rc2
|
||||
ifneq "$(SUBLEVEL)" ""
|
||||
U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)
|
||||
else
|
||||
|
@ -231,8 +231,8 @@ endif
|
|||
|
||||
OBJS = $(CPUDIR)/start.o
|
||||
ifeq ($(CPU),x86)
|
||||
OBJS += $(CPUDIR)/start16.o
|
||||
OBJS += $(CPUDIR)/resetvec.o
|
||||
RESET_OBJS-$(CONFIG_X86_NO_RESET_VECTOR) += $(CPUDIR)/start16.o
|
||||
RESET_OBJS-$(CONFIG_X86_NO_RESET_VECTOR) += $(CPUDIR)/resetvec.o
|
||||
endif
|
||||
ifeq ($(CPU),ppc4xx)
|
||||
OBJS += $(CPUDIR)/resetvec.o
|
||||
|
@ -241,7 +241,7 @@ ifeq ($(CPU),mpc85xx)
|
|||
OBJS += $(CPUDIR)/resetvec.o
|
||||
endif
|
||||
|
||||
OBJS := $(addprefix $(obj),$(OBJS))
|
||||
OBJS := $(addprefix $(obj),$(OBJS) $(RESET_OBJS-))
|
||||
|
||||
HAVE_VENDOR_COMMON_LIB = $(if $(wildcard board/$(VENDOR)/common/Makefile),y,n)
|
||||
|
||||
|
@ -293,7 +293,10 @@ LIBS-y += drivers/net/libnet.o
|
|||
LIBS-y += drivers/net/phy/libphy.o
|
||||
LIBS-y += drivers/pci/libpci.o
|
||||
LIBS-y += drivers/pcmcia/libpcmcia.o
|
||||
LIBS-y += drivers/power/libpower.o
|
||||
LIBS-y += drivers/power/libpower.o \
|
||||
drivers/power/fuel_gauge/libfuel_gauge.o \
|
||||
drivers/power/pmic/libpmic.o \
|
||||
drivers/power/battery/libbattery.o
|
||||
LIBS-y += drivers/spi/libspi.o
|
||||
LIBS-y += drivers/dfu/libdfu.o
|
||||
ifeq ($(CPU),mpc83xx)
|
||||
|
@ -320,6 +323,7 @@ LIBS-y += drivers/usb/eth/libusb_eth.o
|
|||
LIBS-y += drivers/usb/gadget/libusb_gadget.o
|
||||
LIBS-y += drivers/usb/host/libusb_host.o
|
||||
LIBS-y += drivers/usb/musb/libusb_musb.o
|
||||
LIBS-y += drivers/usb/musb-new/libusb_musb-new.o
|
||||
LIBS-y += drivers/usb/phy/libusb_phy.o
|
||||
LIBS-y += drivers/usb/ulpi/libusb_ulpi.o
|
||||
LIBS-y += drivers/video/libvideo.o
|
||||
|
@ -387,12 +391,12 @@ __LIBS := $(subst $(obj),,$(LIBS)) $(subst $(obj),,$(LIBBOARD))
|
|||
ifneq ($(CONFIG_BOARD_SIZE_LIMIT),)
|
||||
BOARD_SIZE_CHECK = \
|
||||
@actual=`wc -c $@ | awk '{print $$1}'`; \
|
||||
limit=$(CONFIG_BOARD_SIZE_LIMIT); \
|
||||
limit=`printf "%d" $(CONFIG_BOARD_SIZE_LIMIT)`; \
|
||||
if test $$actual -gt $$limit; then \
|
||||
echo "$@ exceeds file size limit:"; \
|
||||
echo " limit: $$limit bytes"; \
|
||||
echo " actual: $$actual bytes"; \
|
||||
echo " excess: $$((actual - limit)) bytes"; \
|
||||
echo "$@ exceeds file size limit:" >&2 ; \
|
||||
echo " limit: $$limit bytes" >&2 ; \
|
||||
echo " actual: $$actual bytes" >&2 ; \
|
||||
echo " excess: $$((actual - limit)) bytes" >&2; \
|
||||
exit 1; \
|
||||
fi
|
||||
else
|
||||
|
@ -405,6 +409,7 @@ ALL-y += $(obj)u-boot.srec $(obj)u-boot.bin $(obj)System.map
|
|||
ALL-$(CONFIG_NAND_U_BOOT) += $(obj)u-boot-nand.bin
|
||||
ALL-$(CONFIG_ONENAND_U_BOOT) += $(obj)u-boot-onenand.bin
|
||||
ALL-$(CONFIG_SPL) += $(obj)spl/u-boot-spl.bin
|
||||
ALL-$(CONFIG_SPL) += $(obj)$(subst ",,$(CONFIG_SPL_TARGET))
|
||||
ALL-$(CONFIG_OF_SEPARATE) += $(obj)u-boot.dtb $(obj)u-boot-dtb.bin
|
||||
|
||||
# enable combined SPL/u-boot/dtb rules for tegra
|
||||
|
@ -446,9 +451,18 @@ $(obj)u-boot.ldr.hex: $(obj)u-boot.ldr
|
|||
$(obj)u-boot.ldr.srec: $(obj)u-boot.ldr
|
||||
$(OBJCOPY) ${OBJCFLAGS} -O srec $< $@ -I binary
|
||||
|
||||
#
|
||||
# U-Boot entry point, needed for booting of full-blown U-Boot
|
||||
# from the SPL U-Boot version.
|
||||
#
|
||||
ifndef CONFIG_SYS_UBOOT_START
|
||||
CONFIG_SYS_UBOOT_START := 0
|
||||
endif
|
||||
|
||||
$(obj)u-boot.img: $(obj)u-boot.bin
|
||||
$(obj)tools/mkimage -A $(ARCH) -T firmware -C none \
|
||||
-O u-boot -a $(CONFIG_SYS_TEXT_BASE) -e 0 \
|
||||
-O u-boot -a $(CONFIG_SYS_TEXT_BASE) \
|
||||
-e $(CONFIG_SYS_UBOOT_START) \
|
||||
-n $(shell sed -n -e 's/.*U_BOOT_VERSION//p' $(VERSION_FILE) | \
|
||||
sed -e 's/"[ ]*$$/ for $(BOARD) board"/') \
|
||||
-d $< $@
|
||||
|
@ -472,14 +486,15 @@ $(obj)u-boot.sha1: $(obj)u-boot.bin
|
|||
$(obj)u-boot.dis: $(obj)u-boot
|
||||
$(OBJDUMP) -d $< > $@
|
||||
|
||||
$(obj)u-boot.ubl: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin
|
||||
$(obj)u-boot-with-spl.bin: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin
|
||||
$(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $(obj)spl/u-boot-spl $(obj)spl/u-boot-spl-pad.bin
|
||||
cat $(obj)spl/u-boot-spl-pad.bin $(obj)u-boot.bin > $(obj)u-boot-ubl.bin
|
||||
$(obj)tools/mkimage -n $(UBL_CONFIG) -T ublimage \
|
||||
-e $(CONFIG_SYS_TEXT_BASE) -d $(obj)u-boot-ubl.bin $(obj)u-boot.ubl
|
||||
rm $(obj)u-boot-ubl.bin
|
||||
cat $(obj)spl/u-boot-spl-pad.bin $(obj)u-boot.bin > $@
|
||||
rm $(obj)spl/u-boot-spl-pad.bin
|
||||
|
||||
$(obj)u-boot.ubl: $(obj)u-boot-with-spl.bin
|
||||
$(obj)tools/mkimage -n $(UBL_CONFIG) -T ublimage \
|
||||
-e $(CONFIG_SYS_TEXT_BASE) -d $< $(obj)u-boot.ubl
|
||||
|
||||
$(obj)u-boot.ais: $(obj)spl/u-boot-spl.bin $(obj)u-boot.img
|
||||
$(obj)tools/mkimage -s -n $(if $(CONFIG_AIS_CONFIG_FILE),$(CONFIG_AIS_CONFIG_FILE),"/dev/null") \
|
||||
-T aisimage \
|
||||
|
@ -496,7 +511,7 @@ $(obj)u-boot.ais: $(obj)spl/u-boot-spl.bin $(obj)u-boot.img
|
|||
ELFTOSB_TARGET-$(CONFIG_MX28) = imx28
|
||||
|
||||
$(obj)u-boot.sb: $(obj)u-boot.bin $(obj)spl/u-boot-spl.bin
|
||||
elftosb -zdf $(ELFTOSB_TARGET-y) -c $(TOPDIR)/$(CPUDIR)/$(SOC)/u-boot-$(ELFTOSB_TARGET-y).bd \
|
||||
elftosb -zf $(ELFTOSB_TARGET-y) -c $(TOPDIR)/$(CPUDIR)/$(SOC)/u-boot-$(ELFTOSB_TARGET-y).bd \
|
||||
-o $(obj)u-boot.sb
|
||||
|
||||
# On x600 (SPEAr600) U-Boot is appended to U-Boot SPL.
|
||||
|
@ -530,6 +545,9 @@ $(obj)u-boot-$(nodtb)-tegra.bin: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin $(dtb
|
|||
rm $(obj)spl/u-boot-spl-pad.bin
|
||||
endif
|
||||
|
||||
$(obj)u-boot-img.bin: $(obj)spl/u-boot-spl.bin $(obj)u-boot.img
|
||||
cat $(obj)spl/u-boot-spl.bin $(obj)u-boot.img > $@
|
||||
|
||||
ifeq ($(CONFIG_SANDBOX),y)
|
||||
GEN_UBOOT = \
|
||||
cd $(LNDIR) && $(CC) $(SYMS) -T $(obj)u-boot.lds \
|
||||
|
@ -639,6 +657,16 @@ checkthumb:
|
|||
echo '*** Your board is configured for THUMB mode.'; \
|
||||
false; \
|
||||
fi
|
||||
|
||||
# GCC 3.x is reported to have problems generating the type of relocation
|
||||
# that U-Boot wants.
|
||||
# See http://lists.denx.de/pipermail/u-boot/2012-September/135156.html
|
||||
checkgcc4:
|
||||
@if test $(call cc-version) -lt 0400; then \
|
||||
echo -n '*** Your GCC is too old, please upgrade to GCC 4.x or newer'; \
|
||||
false; \
|
||||
fi
|
||||
|
||||
#
|
||||
# Auto-generate the autoconf.mk file (which is included by all makefiles)
|
||||
#
|
||||
|
@ -812,7 +840,7 @@ clean:
|
|||
@rm -f $(obj)include/generated/asm-offsets.h
|
||||
@rm -f $(obj)$(CPUDIR)/$(SOC)/asm-offsets.s
|
||||
@rm -f $(TIMESTAMP_FILE) $(VERSION_FILE)
|
||||
@$(MAKE) -C doc/DocBook/ cleandocs
|
||||
@$(MAKE) -s -C doc/DocBook/ cleandocs
|
||||
@find $(OBJTREE) -type f \
|
||||
\( -name 'core' -o -name '*.bak' -o -name '*~' -o -name '*.su' \
|
||||
-o -name '*.o' -o -name '*.a' -o -name '*.exe' \) -print \
|
||||
|
|
199
README
199
README
|
@ -54,6 +54,11 @@ In case of problems see the CHANGELOG and CREDITS files to find out
|
|||
who contributed the specific port. The MAINTAINERS file lists board
|
||||
maintainers.
|
||||
|
||||
Note: There is no CHANGELOG file in the actual U-Boot source tree;
|
||||
it can be created dynamically from the Git log using:
|
||||
|
||||
make CHANGELOG
|
||||
|
||||
|
||||
Where to get help:
|
||||
==================
|
||||
|
@ -810,6 +815,8 @@ The following options need to be configured:
|
|||
CONFIG_CMD_EDITENV edit env variable
|
||||
CONFIG_CMD_EEPROM * EEPROM read/write support
|
||||
CONFIG_CMD_ELF * bootelf, bootvx
|
||||
CONFIG_CMD_ENV_CALLBACK * display details about env callbacks
|
||||
CONFIG_CMD_ENV_FLAGS * display details about env flags
|
||||
CONFIG_CMD_EXPORTENV * export the environment
|
||||
CONFIG_CMD_EXT2 * ext2 command support
|
||||
CONFIG_CMD_EXT4 * ext4 command support
|
||||
|
@ -819,8 +826,10 @@ The following options need to be configured:
|
|||
CONFIG_CMD_FDOS * Dos diskette Support
|
||||
CONFIG_CMD_FLASH flinfo, erase, protect
|
||||
CONFIG_CMD_FPGA FPGA device initialization support
|
||||
CONFIG_CMD_GETTIME * Get time since boot
|
||||
CONFIG_CMD_GO * the 'go' command (exec code)
|
||||
CONFIG_CMD_GREPENV * search environment
|
||||
CONFIG_CMD_HASH * calculate hash / digest
|
||||
CONFIG_CMD_HWFLOW * RTS/CTS hw flow control
|
||||
CONFIG_CMD_I2C * I2C serial bus support
|
||||
CONFIG_CMD_IDE * IDE harddisk support
|
||||
|
@ -855,6 +864,7 @@ The following options need to be configured:
|
|||
CONFIG_CMD_PING * send ICMP ECHO_REQUEST to network
|
||||
host
|
||||
CONFIG_CMD_PORTIO * Port I/O
|
||||
CONFIG_CMD_READ * Read raw data from partition
|
||||
CONFIG_CMD_REGINFO * Register dump
|
||||
CONFIG_CMD_RUN run command in env variable
|
||||
CONFIG_CMD_SAVES * save S record dump
|
||||
|
@ -1409,6 +1419,13 @@ CBFS (Coreboot Filesystem) support
|
|||
boot. See the documentation file README.video for a
|
||||
description of this variable.
|
||||
|
||||
CONFIG_VIDEO_VGA
|
||||
|
||||
Enable the VGA video / BIOS for x86. The alternative if you
|
||||
are using coreboot is to use the coreboot frame buffer
|
||||
driver.
|
||||
|
||||
|
||||
- Keyboard Support:
|
||||
CONFIG_KEYBOARD
|
||||
|
||||
|
@ -1469,7 +1486,6 @@ CBFS (Coreboot Filesystem) support
|
|||
Normally display is black on white background; define
|
||||
CONFIG_SYS_WHITE_ON_BLACK to get it inverted.
|
||||
|
||||
|
||||
CONFIG_LCD_ALIGNMENT
|
||||
|
||||
Normally the LCD is page-aligned (tyically 4KB). If this is
|
||||
|
@ -1485,6 +1501,15 @@ CBFS (Coreboot Filesystem) support
|
|||
the console jump but can help speed up operation when scrolling
|
||||
is slow.
|
||||
|
||||
CONFIG_LCD_BMP_RLE8
|
||||
|
||||
Support drawing of RLE8-compressed bitmaps on the LCD.
|
||||
|
||||
CONFIG_I2C_EDID
|
||||
|
||||
Enables an 'i2c edid' command which can read EDID
|
||||
information over I2C from an attached LCD display.
|
||||
|
||||
- Splash Screen Support: CONFIG_SPLASH_SCREEN
|
||||
|
||||
If this option is set, the environment is checked for
|
||||
|
@ -2178,6 +2203,11 @@ CBFS (Coreboot Filesystem) support
|
|||
serial# is unaffected by this, i. e. it remains
|
||||
read-only.]
|
||||
|
||||
The same can be accomplished in a more flexible way
|
||||
for any variable by configuring the type of access
|
||||
to allow for those variables in the ".flags" variable
|
||||
or define CONFIG_ENV_FLAGS_LIST_STATIC.
|
||||
|
||||
- Protected RAM:
|
||||
CONFIG_PRAM
|
||||
|
||||
|
@ -2211,6 +2241,14 @@ CBFS (Coreboot Filesystem) support
|
|||
HERMES, IP860, RPXlite, LWMON,
|
||||
FLAGADM, TQM8260
|
||||
|
||||
- Access to physical memory region (> 4GB)
|
||||
Some basic support is provided for operations on memory not
|
||||
normally accessible to U-Boot - e.g. some architectures
|
||||
support access to more than 4GB of memory on 32-bit
|
||||
machines using physical address extension or similar.
|
||||
Define CONFIG_PHYSMEM to access this basic support, which
|
||||
currently only supports clearing the memory.
|
||||
|
||||
- Error Recovery:
|
||||
CONFIG_PANIC_HANG
|
||||
|
||||
|
@ -2400,6 +2438,23 @@ CBFS (Coreboot Filesystem) support
|
|||
A better solution is to properly configure the firewall,
|
||||
but sometimes that is not allowed.
|
||||
|
||||
- Hashing support:
|
||||
CONFIG_CMD_HASH
|
||||
|
||||
This enables a generic 'hash' command which can produce
|
||||
hashes / digests from a few algorithms (e.g. SHA1, SHA256).
|
||||
|
||||
CONFIG_HASH_VERIFY
|
||||
|
||||
Enable the hash verify command (hash -v). This adds to code
|
||||
size a little.
|
||||
|
||||
CONFIG_SHA1 - support SHA1 hashing
|
||||
CONFIG_SHA256 - support SHA256 hashing
|
||||
|
||||
Note: There is also a sha1sum command, which should perhaps
|
||||
be deprecated in favour of 'hash sha1'.
|
||||
|
||||
- Show boot progress:
|
||||
CONFIG_SHOW_BOOT_PROGRESS
|
||||
|
||||
|
@ -2613,6 +2668,17 @@ FIT uImage format:
|
|||
-150 common/cmd_nand.c Incorrect FIT image format
|
||||
151 common/cmd_nand.c FIT image format OK
|
||||
|
||||
- FIT image support:
|
||||
CONFIG_FIT
|
||||
Enable support for the FIT uImage format.
|
||||
|
||||
CONFIG_FIT_BEST_MATCH
|
||||
When no configuration is explicitly selected, default to the
|
||||
one whose fdt's compatibility field best matches that of
|
||||
U-Boot itself. A match is considered "best" if it matches the
|
||||
most specific compatibility entry of U-Boot's fdt's root node.
|
||||
The order of entries in the configuration's fdt is ignored.
|
||||
|
||||
- Standalone program support:
|
||||
CONFIG_STANDALONE_LOAD_ADDR
|
||||
|
||||
|
@ -2664,6 +2730,10 @@ FIT uImage format:
|
|||
CONFIG_SPL_TEXT_BASE
|
||||
TEXT_BASE for linking the SPL binary.
|
||||
|
||||
CONFIG_SPL_RELOC_TEXT_BASE
|
||||
Address to relocate to. If unspecified, this is equal to
|
||||
CONFIG_SPL_TEXT_BASE (i.e. no relocation is done).
|
||||
|
||||
CONFIG_SPL_BSS_START_ADDR
|
||||
Link address for the BSS within the SPL binary.
|
||||
|
||||
|
@ -2673,6 +2743,11 @@ FIT uImage format:
|
|||
CONFIG_SPL_STACK
|
||||
Adress of the start of the stack SPL will use
|
||||
|
||||
CONFIG_SPL_RELOC_STACK
|
||||
Adress of the start of the stack SPL will use after
|
||||
relocation. If unspecified, this is equal to
|
||||
CONFIG_SPL_STACK.
|
||||
|
||||
CONFIG_SYS_SPL_MALLOC_START
|
||||
Starting address of the malloc pool used in SPL.
|
||||
|
||||
|
@ -2688,6 +2763,9 @@ FIT uImage format:
|
|||
For ARM, enable an optional function to print more information
|
||||
about the running system.
|
||||
|
||||
CONFIG_SPL_INIT_MINIMAL
|
||||
Arch init code should be built for a very small image
|
||||
|
||||
CONFIG_SPL_LIBCOMMON_SUPPORT
|
||||
Support for common/libcommon.o in SPL binary
|
||||
|
||||
|
@ -2715,8 +2793,19 @@ FIT uImage format:
|
|||
CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME
|
||||
Filename to read to load U-Boot when reading from FAT
|
||||
|
||||
CONFIG_SPL_NAND_BASE
|
||||
Include nand_base.c in the SPL. Requires
|
||||
CONFIG_SPL_NAND_DRIVERS.
|
||||
|
||||
CONFIG_SPL_NAND_DRIVERS
|
||||
SPL uses normal NAND drivers, not minimal drivers.
|
||||
|
||||
CONFIG_SPL_NAND_ECC
|
||||
Include standard software ECC in the SPL
|
||||
|
||||
CONFIG_SPL_NAND_SIMPLE
|
||||
Support for drivers/mtd/nand/libnand.o in SPL binary
|
||||
Support for NAND boot using simple NAND drivers that
|
||||
expose the cmd_ctrl() interface.
|
||||
|
||||
CONFIG_SYS_NAND_5_ADDR_CYCLE, CONFIG_SYS_NAND_PAGE_COUNT,
|
||||
CONFIG_SYS_NAND_PAGE_SIZE, CONFIG_SYS_NAND_OOBSIZE,
|
||||
|
@ -2724,15 +2813,19 @@ FIT uImage format:
|
|||
CONFIG_SYS_NAND_ECCPOS, CONFIG_SYS_NAND_ECCSIZE,
|
||||
CONFIG_SYS_NAND_ECCBYTES
|
||||
Defines the size and behavior of the NAND that SPL uses
|
||||
to read U-Boot with CONFIG_SPL_NAND_SIMPLE
|
||||
to read U-Boot
|
||||
|
||||
CONFIG_SYS_NAND_U_BOOT_OFFS
|
||||
Location in NAND for CONFIG_SPL_NAND_SIMPLE to read U-Boot
|
||||
from.
|
||||
Location in NAND to read U-Boot from
|
||||
|
||||
CONFIG_SYS_NAND_U_BOOT_DST
|
||||
Location in memory to load U-Boot to
|
||||
|
||||
CONFIG_SYS_NAND_U_BOOT_SIZE
|
||||
Size of image to load
|
||||
|
||||
CONFIG_SYS_NAND_U_BOOT_START
|
||||
Location in memory for CONFIG_SPL_NAND_SIMPLE to load U-Boot
|
||||
to.
|
||||
Entry point in loaded image to jump to
|
||||
|
||||
CONFIG_SYS_NAND_HW_ECC_OOBFIRST
|
||||
Define this if you need to first read the OOB and then the
|
||||
|
@ -2757,6 +2850,11 @@ FIT uImage format:
|
|||
CONFIG_SPL_LIBGENERIC_SUPPORT
|
||||
Support for lib/libgeneric.o in SPL binary
|
||||
|
||||
CONFIG_SPL_TARGET
|
||||
Final target image containing SPL and payload. Some SPLs
|
||||
use an arch-specific makefile fragment instead, for
|
||||
example if more than one image needs to be produced.
|
||||
|
||||
Modem Support:
|
||||
--------------
|
||||
|
||||
|
@ -2891,9 +2989,6 @@ Configuration Settings:
|
|||
non page size aligned address and this could cause major
|
||||
problems.
|
||||
|
||||
- CONFIG_SYS_TFTP_LOADADDR:
|
||||
Default load address for network file downloads
|
||||
|
||||
- CONFIG_SYS_LOADS_BAUD_CHANGE:
|
||||
Enable temporary baudrate change while serial download
|
||||
|
||||
|
@ -3035,6 +3130,49 @@ Configuration Settings:
|
|||
cases. This setting can be used to tune behaviour; see
|
||||
lib/hashtable.c for details.
|
||||
|
||||
- CONFIG_ENV_FLAGS_LIST_DEFAULT
|
||||
- CONFIG_ENV_FLAGS_LIST_STATIC
|
||||
Enable validation of the values given to enviroment variables when
|
||||
calling env set. Variables can be restricted to only decimal,
|
||||
hexadecimal, or boolean. If CONFIG_CMD_NET is also defined,
|
||||
the variables can also be restricted to IP address or MAC address.
|
||||
|
||||
The format of the list is:
|
||||
type_attribute = [s|d|x|b|i|m]
|
||||
access_atribute = [a|r|o|c]
|
||||
attributes = type_attribute[access_atribute]
|
||||
entry = variable_name[:attributes]
|
||||
list = entry[,list]
|
||||
|
||||
The type attributes are:
|
||||
s - String (default)
|
||||
d - Decimal
|
||||
x - Hexadecimal
|
||||
b - Boolean ([1yYtT|0nNfF])
|
||||
i - IP address
|
||||
m - MAC address
|
||||
|
||||
The access attributes are:
|
||||
a - Any (default)
|
||||
r - Read-only
|
||||
o - Write-once
|
||||
c - Change-default
|
||||
|
||||
- CONFIG_ENV_FLAGS_LIST_DEFAULT
|
||||
Define this to a list (string) to define the ".flags"
|
||||
envirnoment variable in the default or embedded environment.
|
||||
|
||||
- CONFIG_ENV_FLAGS_LIST_STATIC
|
||||
Define this to a list (string) to define validation that
|
||||
should be done if an entry is not found in the ".flags"
|
||||
environment variable. To override a setting in the static
|
||||
list, simply add an entry for the same variable name to the
|
||||
".flags" variable.
|
||||
|
||||
- CONFIG_ENV_ACCESS_IGNORE_FORCE
|
||||
If defined, don't allow the -f switch to env set override variable
|
||||
access flags.
|
||||
|
||||
The following definitions that deal with the placement and management
|
||||
of environment data (variable area); in general, we support the
|
||||
following configurations:
|
||||
|
@ -3632,6 +3770,16 @@ Low Level (hardware related) configuration options:
|
|||
be used if available. These functions may be faster under some
|
||||
conditions but may increase the binary size.
|
||||
|
||||
- CONFIG_X86_NO_RESET_VECTOR
|
||||
If defined, the x86 reset vector code is excluded. You will need
|
||||
to do this when U-Boot is running from Coreboot.
|
||||
|
||||
- CONFIG_X86_NO_REAL_MODE
|
||||
If defined, x86 real mode code is omitted. This assumes a
|
||||
32-bit environment where such code is not needed. You will
|
||||
need to do this when U-Boot is running from Coreboot.
|
||||
|
||||
|
||||
Freescale QE/FMAN Firmware Support:
|
||||
-----------------------------------
|
||||
|
||||
|
@ -3859,6 +4007,7 @@ saveenv - save environment variables to persistent storage
|
|||
protect - enable or disable FLASH write protection
|
||||
erase - erase FLASH memory
|
||||
flinfo - print FLASH memory information
|
||||
nand - NAND memory operations (see doc/README.nand)
|
||||
bdinfo - print Board Info structure
|
||||
iminfo - print header information for application image
|
||||
coninfo - print console devices and informations
|
||||
|
@ -4125,6 +4274,36 @@ Please note that changes to some configuration parameters may take
|
|||
only effect after the next boot (yes, that's just like Windoze :-).
|
||||
|
||||
|
||||
Callback functions for environment variables:
|
||||
---------------------------------------------
|
||||
|
||||
For some environment variables, the behavior of u-boot needs to change
|
||||
when their values are changed. This functionailty allows functions to
|
||||
be associated with arbitrary variables. On creation, overwrite, or
|
||||
deletion, the callback will provide the opportunity for some side
|
||||
effect to happen or for the change to be rejected.
|
||||
|
||||
The callbacks are named and associated with a function using the
|
||||
U_BOOT_ENV_CALLBACK macro in your board or driver code.
|
||||
|
||||
These callbacks are associated with variables in one of two ways. The
|
||||
static list can be added to by defining CONFIG_ENV_CALLBACK_LIST_STATIC
|
||||
in the board configuration to a string that defines a list of
|
||||
associations. The list must be in the following format:
|
||||
|
||||
entry = variable_name[:callback_name]
|
||||
list = entry[,list]
|
||||
|
||||
If the callback name is not specified, then the callback is deleted.
|
||||
Spaces are also allowed anywhere in the list.
|
||||
|
||||
Callbacks can also be associated by defining the ".callbacks" variable
|
||||
with the same list format above. Any association in ".callbacks" will
|
||||
override any association in the static list. You can define
|
||||
CONFIG_ENV_CALLBACK_LIST_DEFAULT to a list (string) to define the
|
||||
".callbacks" envirnoment variable in the default or embedded environment.
|
||||
|
||||
|
||||
Command Line Parsing:
|
||||
=====================
|
||||
|
||||
|
|
|
@ -333,6 +333,8 @@ uint32_t mxc_get_clock(enum mxc_clock clk)
|
|||
return mx28_get_sspclk(MXC_SSPCLK2);
|
||||
case MXC_SSP3_CLK:
|
||||
return mx28_get_sspclk(MXC_SSPCLK3);
|
||||
case MXC_XTAL_CLK:
|
||||
return XTAL_FREQ_KHZ * 1000;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
|
|
@ -50,7 +50,7 @@ void early_delay(int delay)
|
|||
}
|
||||
|
||||
#define MUX_CONFIG_BOOTMODE_PAD (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
|
||||
const iomux_cfg_t iomux_boot[] = {
|
||||
static const iomux_cfg_t iomux_boot[] = {
|
||||
MX28_PAD_LCD_D00__GPIO_1_0 | MUX_CONFIG_BOOTMODE_PAD,
|
||||
MX28_PAD_LCD_D01__GPIO_1_1 | MUX_CONFIG_BOOTMODE_PAD,
|
||||
MX28_PAD_LCD_D02__GPIO_1_2 | MUX_CONFIG_BOOTMODE_PAD,
|
||||
|
@ -59,7 +59,7 @@ const iomux_cfg_t iomux_boot[] = {
|
|||
MX28_PAD_LCD_D05__GPIO_1_5 | MUX_CONFIG_BOOTMODE_PAD,
|
||||
};
|
||||
|
||||
uint8_t mxs_get_bootmode_index(void)
|
||||
static uint8_t mxs_get_bootmode_index(void)
|
||||
{
|
||||
uint8_t bootmode = 0;
|
||||
int i;
|
||||
|
|
|
@ -30,7 +30,11 @@
|
|||
|
||||
#include "mxs_init.h"
|
||||
|
||||
static uint32_t mx28_dram_vals[] = {
|
||||
static uint32_t dram_vals[] = {
|
||||
/*
|
||||
* i.MX28 DDR2 at 200MHz
|
||||
*/
|
||||
#if defined(CONFIG_MX28)
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
|
@ -79,6 +83,9 @@ static uint32_t mx28_dram_vals[] = {
|
|||
0x06120612, 0x04320432, 0x04320432, 0x00040004,
|
||||
0x00040004, 0x00000000, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00010001
|
||||
#else
|
||||
#error Unsupported memory initialization
|
||||
#endif
|
||||
};
|
||||
|
||||
void __mxs_adjust_memory_params(uint32_t *dram_vals)
|
||||
|
@ -87,17 +94,17 @@ void __mxs_adjust_memory_params(uint32_t *dram_vals)
|
|||
void mxs_adjust_memory_params(uint32_t *dram_vals)
|
||||
__attribute__((weak, alias("__mxs_adjust_memory_params")));
|
||||
|
||||
void init_mx28_200mhz_ddr2(void)
|
||||
static void initialize_dram_values(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
mxs_adjust_memory_params(mx28_dram_vals);
|
||||
mxs_adjust_memory_params(dram_vals);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(mx28_dram_vals); i++)
|
||||
writel(mx28_dram_vals[i], MXS_DRAM_BASE + (4 * i));
|
||||
for (i = 0; i < ARRAY_SIZE(dram_vals); i++)
|
||||
writel(dram_vals[i], MXS_DRAM_BASE + (4 * i));
|
||||
}
|
||||
|
||||
void mxs_mem_init_clock(void)
|
||||
static void mxs_mem_init_clock(void)
|
||||
{
|
||||
struct mxs_clkctrl_regs *clkctrl_regs =
|
||||
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
|
||||
|
@ -128,7 +135,7 @@ void mxs_mem_init_clock(void)
|
|||
early_delay(10000);
|
||||
}
|
||||
|
||||
void mxs_mem_setup_cpu_and_hbus(void)
|
||||
static void mxs_mem_setup_cpu_and_hbus(void)
|
||||
{
|
||||
struct mxs_clkctrl_regs *clkctrl_regs =
|
||||
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
|
||||
|
@ -160,7 +167,7 @@ void mxs_mem_setup_cpu_and_hbus(void)
|
|||
early_delay(15000);
|
||||
}
|
||||
|
||||
void mxs_mem_setup_vdda(void)
|
||||
static void mxs_mem_setup_vdda(void)
|
||||
{
|
||||
struct mxs_power_regs *power_regs =
|
||||
(struct mxs_power_regs *)MXS_POWER_BASE;
|
||||
|
@ -171,17 +178,6 @@ void mxs_mem_setup_vdda(void)
|
|||
&power_regs->hw_power_vddactrl);
|
||||
}
|
||||
|
||||
void mxs_mem_setup_vddd(void)
|
||||
{
|
||||
struct mxs_power_regs *power_regs =
|
||||
(struct mxs_power_regs *)MXS_POWER_BASE;
|
||||
|
||||
writel((0x1c << POWER_VDDDCTRL_TRG_OFFSET) |
|
||||
(0x7 << POWER_VDDDCTRL_BO_OFFSET_OFFSET) |
|
||||
POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW,
|
||||
&power_regs->hw_power_vdddctrl);
|
||||
}
|
||||
|
||||
uint32_t mxs_mem_get_size(void)
|
||||
{
|
||||
uint32_t sz, da;
|
||||
|
@ -229,7 +225,7 @@ void mxs_mem_init(void)
|
|||
/* Clear START bit from DRAM_CTL16 */
|
||||
clrbits_le32(MXS_DRAM_BASE + 0x40, 1);
|
||||
|
||||
init_mx28_200mhz_ddr2();
|
||||
initialize_dram_values();
|
||||
|
||||
/* Clear SREFRESH bit from DRAM_CTL17 */
|
||||
clrbits_le32(MXS_DRAM_BASE + 0x44, 1);
|
||||
|
@ -241,8 +237,6 @@ void mxs_mem_init(void)
|
|||
while (!(readl(MXS_DRAM_BASE + 0xe8) & (1 << 20)))
|
||||
;
|
||||
|
||||
mxs_mem_setup_vddd();
|
||||
|
||||
early_delay(10000);
|
||||
|
||||
mxs_mem_setup_cpu_and_hbus();
|
||||
|
|
|
@ -30,7 +30,7 @@
|
|||
|
||||
#include "mxs_init.h"
|
||||
|
||||
void mxs_power_clock2xtal(void)
|
||||
static void mxs_power_clock2xtal(void)
|
||||
{
|
||||
struct mxs_clkctrl_regs *clkctrl_regs =
|
||||
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
|
||||
|
@ -40,7 +40,7 @@ void mxs_power_clock2xtal(void)
|
|||
&clkctrl_regs->hw_clkctrl_clkseq_set);
|
||||
}
|
||||
|
||||
void mxs_power_clock2pll(void)
|
||||
static void mxs_power_clock2pll(void)
|
||||
{
|
||||
struct mxs_clkctrl_regs *clkctrl_regs =
|
||||
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
|
||||
|
@ -52,7 +52,7 @@ void mxs_power_clock2pll(void)
|
|||
CLKCTRL_CLKSEQ_BYPASS_CPU);
|
||||
}
|
||||
|
||||
void mxs_power_clear_auto_restart(void)
|
||||
static void mxs_power_clear_auto_restart(void)
|
||||
{
|
||||
struct mxs_rtc_regs *rtc_regs =
|
||||
(struct mxs_rtc_regs *)MXS_RTC_BASE;
|
||||
|
@ -85,7 +85,7 @@ void mxs_power_clear_auto_restart(void)
|
|||
;
|
||||
}
|
||||
|
||||
void mxs_power_set_linreg(void)
|
||||
static void mxs_power_set_linreg(void)
|
||||
{
|
||||
struct mxs_power_regs *power_regs =
|
||||
(struct mxs_power_regs *)MXS_POWER_BASE;
|
||||
|
@ -104,7 +104,7 @@ void mxs_power_set_linreg(void)
|
|||
POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_BELOW);
|
||||
}
|
||||
|
||||
int mxs_get_batt_volt(void)
|
||||
static int mxs_get_batt_volt(void)
|
||||
{
|
||||
struct mxs_power_regs *power_regs =
|
||||
(struct mxs_power_regs *)MXS_POWER_BASE;
|
||||
|
@ -115,12 +115,12 @@ int mxs_get_batt_volt(void)
|
|||
return volt;
|
||||
}
|
||||
|
||||
int mxs_is_batt_ready(void)
|
||||
static int mxs_is_batt_ready(void)
|
||||
{
|
||||
return (mxs_get_batt_volt() >= 3600);
|
||||
}
|
||||
|
||||
int mxs_is_batt_good(void)
|
||||
static int mxs_is_batt_good(void)
|
||||
{
|
||||
struct mxs_power_regs *power_regs =
|
||||
(struct mxs_power_regs *)MXS_POWER_BASE;
|
||||
|
@ -160,7 +160,7 @@ int mxs_is_batt_good(void)
|
|||
return 0;
|
||||
}
|
||||
|
||||
void mxs_power_setup_5v_detect(void)
|
||||
static void mxs_power_setup_5v_detect(void)
|
||||
{
|
||||
struct mxs_power_regs *power_regs =
|
||||
(struct mxs_power_regs *)MXS_POWER_BASE;
|
||||
|
@ -172,7 +172,7 @@ void mxs_power_setup_5v_detect(void)
|
|||
POWER_5VCTRL_PWRUP_VBUS_CMPS);
|
||||
}
|
||||
|
||||
void mxs_src_power_init(void)
|
||||
static void mxs_src_power_init(void)
|
||||
{
|
||||
struct mxs_power_regs *power_regs =
|
||||
(struct mxs_power_regs *)MXS_POWER_BASE;
|
||||
|
@ -203,7 +203,7 @@ void mxs_src_power_init(void)
|
|||
clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
|
||||
}
|
||||
|
||||
void mxs_power_init_4p2_params(void)
|
||||
static void mxs_power_init_4p2_params(void)
|
||||
{
|
||||
struct mxs_power_regs *power_regs =
|
||||
(struct mxs_power_regs *)MXS_POWER_BASE;
|
||||
|
@ -227,7 +227,7 @@ void mxs_power_init_4p2_params(void)
|
|||
0x3f << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
|
||||
}
|
||||
|
||||
void mxs_enable_4p2_dcdc_input(int xfer)
|
||||
static void mxs_enable_4p2_dcdc_input(int xfer)
|
||||
{
|
||||
struct mxs_power_regs *power_regs =
|
||||
(struct mxs_power_regs *)MXS_POWER_BASE;
|
||||
|
@ -323,7 +323,7 @@ void mxs_enable_4p2_dcdc_input(int xfer)
|
|||
POWER_CTRL_ENIRQ_VDD5V_DROOP);
|
||||
}
|
||||
|
||||
void mxs_power_init_4p2_regulator(void)
|
||||
static void mxs_power_init_4p2_regulator(void)
|
||||
{
|
||||
struct mxs_power_regs *power_regs =
|
||||
(struct mxs_power_regs *)MXS_POWER_BASE;
|
||||
|
@ -407,7 +407,7 @@ void mxs_power_init_4p2_regulator(void)
|
|||
writel(POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr);
|
||||
}
|
||||
|
||||
void mxs_power_init_dcdc_4p2_source(void)
|
||||
static void mxs_power_init_dcdc_4p2_source(void)
|
||||
{
|
||||
struct mxs_power_regs *power_regs =
|
||||
(struct mxs_power_regs *)MXS_POWER_BASE;
|
||||
|
@ -429,7 +429,7 @@ void mxs_power_init_dcdc_4p2_source(void)
|
|||
}
|
||||
}
|
||||
|
||||
void mxs_power_enable_4p2(void)
|
||||
static void mxs_power_enable_4p2(void)
|
||||
{
|
||||
struct mxs_power_regs *power_regs =
|
||||
(struct mxs_power_regs *)MXS_POWER_BASE;
|
||||
|
@ -488,7 +488,7 @@ void mxs_power_enable_4p2(void)
|
|||
&power_regs->hw_power_charge_clr);
|
||||
}
|
||||
|
||||
void mxs_boot_valid_5v(void)
|
||||
static void mxs_boot_valid_5v(void)
|
||||
{
|
||||
struct mxs_power_regs *power_regs =
|
||||
(struct mxs_power_regs *)MXS_POWER_BASE;
|
||||
|
@ -511,7 +511,7 @@ void mxs_boot_valid_5v(void)
|
|||
mxs_power_enable_4p2();
|
||||
}
|
||||
|
||||
void mxs_powerdown(void)
|
||||
static void mxs_powerdown(void)
|
||||
{
|
||||
struct mxs_power_regs *power_regs =
|
||||
(struct mxs_power_regs *)MXS_POWER_BASE;
|
||||
|
@ -520,7 +520,7 @@ void mxs_powerdown(void)
|
|||
&power_regs->hw_power_reset);
|
||||
}
|
||||
|
||||
void mxs_batt_boot(void)
|
||||
static void mxs_batt_boot(void)
|
||||
{
|
||||
struct mxs_power_regs *power_regs =
|
||||
(struct mxs_power_regs *)MXS_POWER_BASE;
|
||||
|
@ -564,7 +564,7 @@ void mxs_batt_boot(void)
|
|||
0x8 << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
|
||||
}
|
||||
|
||||
void mxs_handle_5v_conflict(void)
|
||||
static void mxs_handle_5v_conflict(void)
|
||||
{
|
||||
struct mxs_power_regs *power_regs =
|
||||
(struct mxs_power_regs *)MXS_POWER_BASE;
|
||||
|
@ -600,7 +600,7 @@ void mxs_handle_5v_conflict(void)
|
|||
}
|
||||
}
|
||||
|
||||
void mxs_5v_boot(void)
|
||||
static void mxs_5v_boot(void)
|
||||
{
|
||||
struct mxs_power_regs *power_regs =
|
||||
(struct mxs_power_regs *)MXS_POWER_BASE;
|
||||
|
@ -623,7 +623,7 @@ void mxs_5v_boot(void)
|
|||
mxs_handle_5v_conflict();
|
||||
}
|
||||
|
||||
void mxs_init_batt_bo(void)
|
||||
static void mxs_init_batt_bo(void)
|
||||
{
|
||||
struct mxs_power_regs *power_regs =
|
||||
(struct mxs_power_regs *)MXS_POWER_BASE;
|
||||
|
@ -637,7 +637,7 @@ void mxs_init_batt_bo(void)
|
|||
writel(POWER_CTRL_ENIRQ_BATT_BO, &power_regs->hw_power_ctrl_clr);
|
||||
}
|
||||
|
||||
void mxs_switch_vddd_to_dcdc_source(void)
|
||||
static void mxs_switch_vddd_to_dcdc_source(void)
|
||||
{
|
||||
struct mxs_power_regs *power_regs =
|
||||
(struct mxs_power_regs *)MXS_POWER_BASE;
|
||||
|
@ -651,7 +651,7 @@ void mxs_switch_vddd_to_dcdc_source(void)
|
|||
POWER_VDDDCTRL_DISABLE_STEPPING);
|
||||
}
|
||||
|
||||
void mxs_power_configure_power_source(void)
|
||||
static void mxs_power_configure_power_source(void)
|
||||
{
|
||||
int batt_ready, batt_good;
|
||||
struct mxs_power_regs *power_regs =
|
||||
|
@ -689,7 +689,7 @@ void mxs_power_configure_power_source(void)
|
|||
mxs_switch_vddd_to_dcdc_source();
|
||||
}
|
||||
|
||||
void mxs_enable_output_rail_protection(void)
|
||||
static void mxs_enable_output_rail_protection(void)
|
||||
{
|
||||
struct mxs_power_regs *power_regs =
|
||||
(struct mxs_power_regs *)MXS_POWER_BASE;
|
||||
|
@ -707,7 +707,7 @@ void mxs_enable_output_rail_protection(void)
|
|||
POWER_VDDIOCTRL_PWDN_BRNOUT);
|
||||
}
|
||||
|
||||
int mxs_get_vddio_power_source_off(void)
|
||||
static int mxs_get_vddio_power_source_off(void)
|
||||
{
|
||||
struct mxs_power_regs *power_regs =
|
||||
(struct mxs_power_regs *)MXS_POWER_BASE;
|
||||
|
@ -735,7 +735,7 @@ int mxs_get_vddio_power_source_off(void)
|
|||
|
||||
}
|
||||
|
||||
int mxs_get_vddd_power_source_off(void)
|
||||
static int mxs_get_vddd_power_source_off(void)
|
||||
{
|
||||
struct mxs_power_regs *power_regs =
|
||||
(struct mxs_power_regs *)MXS_POWER_BASE;
|
||||
|
@ -766,201 +766,115 @@ int mxs_get_vddd_power_source_off(void)
|
|||
return 0;
|
||||
}
|
||||
|
||||
void mxs_power_set_vddio(uint32_t new_target, uint32_t new_brownout)
|
||||
struct mxs_vddx_cfg {
|
||||
uint32_t *reg;
|
||||
uint8_t step_mV;
|
||||
uint16_t lowest_mV;
|
||||
int (*powered_by_linreg)(void);
|
||||
uint32_t trg_mask;
|
||||
uint32_t bo_irq;
|
||||
uint32_t bo_enirq;
|
||||
uint32_t bo_offset_mask;
|
||||
uint32_t bo_offset_offset;
|
||||
};
|
||||
|
||||
static const struct mxs_vddx_cfg mxs_vddio_cfg = {
|
||||
.reg = &(((struct mxs_power_regs *)MXS_POWER_BASE)->
|
||||
hw_power_vddioctrl),
|
||||
.step_mV = 50,
|
||||
.lowest_mV = 2800,
|
||||
.powered_by_linreg = mxs_get_vddio_power_source_off,
|
||||
.trg_mask = POWER_VDDIOCTRL_TRG_MASK,
|
||||
.bo_irq = POWER_CTRL_VDDIO_BO_IRQ,
|
||||
.bo_enirq = POWER_CTRL_ENIRQ_VDDIO_BO,
|
||||
.bo_offset_mask = POWER_VDDIOCTRL_BO_OFFSET_MASK,
|
||||
.bo_offset_offset = POWER_VDDIOCTRL_BO_OFFSET_OFFSET,
|
||||
};
|
||||
|
||||
static const struct mxs_vddx_cfg mxs_vddd_cfg = {
|
||||
.reg = &(((struct mxs_power_regs *)MXS_POWER_BASE)->
|
||||
hw_power_vdddctrl),
|
||||
.step_mV = 25,
|
||||
.lowest_mV = 800,
|
||||
.powered_by_linreg = mxs_get_vddd_power_source_off,
|
||||
.trg_mask = POWER_VDDDCTRL_TRG_MASK,
|
||||
.bo_irq = POWER_CTRL_VDDD_BO_IRQ,
|
||||
.bo_enirq = POWER_CTRL_ENIRQ_VDDD_BO,
|
||||
.bo_offset_mask = POWER_VDDDCTRL_BO_OFFSET_MASK,
|
||||
.bo_offset_offset = POWER_VDDDCTRL_BO_OFFSET_OFFSET,
|
||||
};
|
||||
|
||||
static void mxs_power_set_vddx(const struct mxs_vddx_cfg *cfg,
|
||||
uint32_t new_target, uint32_t new_brownout)
|
||||
{
|
||||
struct mxs_power_regs *power_regs =
|
||||
(struct mxs_power_regs *)MXS_POWER_BASE;
|
||||
uint32_t cur_target, diff, bo_int = 0;
|
||||
uint32_t powered_by_linreg = 0;
|
||||
int adjust_up, tmp;
|
||||
|
||||
new_brownout = (new_target - new_brownout + 25) / 50;
|
||||
new_brownout = DIV_ROUND(new_target - new_brownout, cfg->step_mV);
|
||||
|
||||
cur_target = readl(&power_regs->hw_power_vddioctrl);
|
||||
cur_target &= POWER_VDDIOCTRL_TRG_MASK;
|
||||
cur_target *= 50; /* 50 mV step*/
|
||||
cur_target += 2800; /* 2800 mV lowest */
|
||||
cur_target = readl(cfg->reg);
|
||||
cur_target &= cfg->trg_mask;
|
||||
cur_target *= cfg->step_mV;
|
||||
cur_target += cfg->lowest_mV;
|
||||
|
||||
powered_by_linreg = mxs_get_vddio_power_source_off();
|
||||
if (new_target > cur_target) {
|
||||
adjust_up = new_target > cur_target;
|
||||
powered_by_linreg = cfg->powered_by_linreg();
|
||||
|
||||
if (adjust_up) {
|
||||
if (powered_by_linreg) {
|
||||
bo_int = readl(&power_regs->hw_power_vddioctrl);
|
||||
clrbits_le32(&power_regs->hw_power_vddioctrl,
|
||||
POWER_CTRL_ENIRQ_VDDIO_BO);
|
||||
bo_int = readl(cfg->reg);
|
||||
clrbits_le32(cfg->reg, cfg->bo_enirq);
|
||||
}
|
||||
|
||||
setbits_le32(&power_regs->hw_power_vddioctrl,
|
||||
POWER_VDDIOCTRL_BO_OFFSET_MASK);
|
||||
do {
|
||||
if (new_target - cur_target > 100)
|
||||
diff = cur_target + 100;
|
||||
else
|
||||
diff = new_target;
|
||||
|
||||
diff -= 2800;
|
||||
diff /= 50;
|
||||
|
||||
clrsetbits_le32(&power_regs->hw_power_vddioctrl,
|
||||
POWER_VDDIOCTRL_TRG_MASK, diff);
|
||||
|
||||
if (powered_by_linreg ||
|
||||
(readl(&power_regs->hw_power_sts) &
|
||||
POWER_STS_VDD5V_GT_VDDIO))
|
||||
early_delay(500);
|
||||
else {
|
||||
while (!(readl(&power_regs->hw_power_sts) &
|
||||
POWER_STS_DC_OK))
|
||||
;
|
||||
|
||||
}
|
||||
|
||||
cur_target = readl(&power_regs->hw_power_vddioctrl);
|
||||
cur_target &= POWER_VDDIOCTRL_TRG_MASK;
|
||||
cur_target *= 50; /* 50 mV step*/
|
||||
cur_target += 2800; /* 2800 mV lowest */
|
||||
} while (new_target > cur_target);
|
||||
|
||||
if (powered_by_linreg) {
|
||||
writel(POWER_CTRL_VDDIO_BO_IRQ,
|
||||
&power_regs->hw_power_ctrl_clr);
|
||||
if (bo_int & POWER_CTRL_ENIRQ_VDDIO_BO)
|
||||
setbits_le32(&power_regs->hw_power_vddioctrl,
|
||||
POWER_CTRL_ENIRQ_VDDIO_BO);
|
||||
}
|
||||
} else {
|
||||
do {
|
||||
if (cur_target - new_target > 100)
|
||||
diff = cur_target - 100;
|
||||
else
|
||||
diff = new_target;
|
||||
|
||||
diff -= 2800;
|
||||
diff /= 50;
|
||||
|
||||
clrsetbits_le32(&power_regs->hw_power_vddioctrl,
|
||||
POWER_VDDIOCTRL_TRG_MASK, diff);
|
||||
|
||||
if (powered_by_linreg ||
|
||||
(readl(&power_regs->hw_power_sts) &
|
||||
POWER_STS_VDD5V_GT_VDDIO))
|
||||
early_delay(500);
|
||||
else {
|
||||
while (!(readl(&power_regs->hw_power_sts) &
|
||||
POWER_STS_DC_OK))
|
||||
;
|
||||
|
||||
}
|
||||
|
||||
cur_target = readl(&power_regs->hw_power_vddioctrl);
|
||||
cur_target &= POWER_VDDIOCTRL_TRG_MASK;
|
||||
cur_target *= 50; /* 50 mV step*/
|
||||
cur_target += 2800; /* 2800 mV lowest */
|
||||
} while (new_target < cur_target);
|
||||
setbits_le32(cfg->reg, cfg->bo_offset_mask);
|
||||
}
|
||||
|
||||
clrsetbits_le32(&power_regs->hw_power_vddioctrl,
|
||||
POWER_VDDIOCTRL_BO_OFFSET_MASK,
|
||||
new_brownout << POWER_VDDIOCTRL_BO_OFFSET_OFFSET);
|
||||
}
|
||||
|
||||
void mxs_power_set_vddd(uint32_t new_target, uint32_t new_brownout)
|
||||
{
|
||||
struct mxs_power_regs *power_regs =
|
||||
(struct mxs_power_regs *)MXS_POWER_BASE;
|
||||
uint32_t cur_target, diff, bo_int = 0;
|
||||
uint32_t powered_by_linreg = 0;
|
||||
|
||||
new_brownout = (new_target - new_brownout + 12) / 25;
|
||||
|
||||
cur_target = readl(&power_regs->hw_power_vdddctrl);
|
||||
cur_target &= POWER_VDDDCTRL_TRG_MASK;
|
||||
cur_target *= 25; /* 25 mV step*/
|
||||
cur_target += 800; /* 800 mV lowest */
|
||||
|
||||
powered_by_linreg = mxs_get_vddd_power_source_off();
|
||||
if (new_target > cur_target) {
|
||||
if (powered_by_linreg) {
|
||||
bo_int = readl(&power_regs->hw_power_vdddctrl);
|
||||
clrbits_le32(&power_regs->hw_power_vdddctrl,
|
||||
POWER_CTRL_ENIRQ_VDDD_BO);
|
||||
}
|
||||
|
||||
setbits_le32(&power_regs->hw_power_vdddctrl,
|
||||
POWER_VDDDCTRL_BO_OFFSET_MASK);
|
||||
|
||||
do {
|
||||
if (new_target - cur_target > 100)
|
||||
do {
|
||||
if (abs(new_target - cur_target) > 100) {
|
||||
if (adjust_up)
|
||||
diff = cur_target + 100;
|
||||
else
|
||||
diff = new_target;
|
||||
|
||||
diff -= 800;
|
||||
diff /= 25;
|
||||
|
||||
clrsetbits_le32(&power_regs->hw_power_vdddctrl,
|
||||
POWER_VDDDCTRL_TRG_MASK, diff);
|
||||
|
||||
if (powered_by_linreg ||
|
||||
(readl(&power_regs->hw_power_sts) &
|
||||
POWER_STS_VDD5V_GT_VDDIO))
|
||||
early_delay(500);
|
||||
else {
|
||||
while (!(readl(&power_regs->hw_power_sts) &
|
||||
POWER_STS_DC_OK))
|
||||
;
|
||||
|
||||
}
|
||||
|
||||
cur_target = readl(&power_regs->hw_power_vdddctrl);
|
||||
cur_target &= POWER_VDDDCTRL_TRG_MASK;
|
||||
cur_target *= 25; /* 25 mV step*/
|
||||
cur_target += 800; /* 800 mV lowest */
|
||||
} while (new_target > cur_target);
|
||||
|
||||
if (powered_by_linreg) {
|
||||
writel(POWER_CTRL_VDDD_BO_IRQ,
|
||||
&power_regs->hw_power_ctrl_clr);
|
||||
if (bo_int & POWER_CTRL_ENIRQ_VDDD_BO)
|
||||
setbits_le32(&power_regs->hw_power_vdddctrl,
|
||||
POWER_CTRL_ENIRQ_VDDD_BO);
|
||||
}
|
||||
} else {
|
||||
do {
|
||||
if (cur_target - new_target > 100)
|
||||
diff = cur_target - 100;
|
||||
else
|
||||
diff = new_target;
|
||||
} else {
|
||||
diff = new_target;
|
||||
}
|
||||
|
||||
diff -= 800;
|
||||
diff /= 25;
|
||||
diff -= cfg->lowest_mV;
|
||||
diff /= cfg->step_mV;
|
||||
|
||||
clrsetbits_le32(&power_regs->hw_power_vdddctrl,
|
||||
POWER_VDDDCTRL_TRG_MASK, diff);
|
||||
|
||||
if (powered_by_linreg ||
|
||||
(readl(&power_regs->hw_power_sts) &
|
||||
POWER_STS_VDD5V_GT_VDDIO))
|
||||
early_delay(500);
|
||||
else {
|
||||
while (!(readl(&power_regs->hw_power_sts) &
|
||||
POWER_STS_DC_OK))
|
||||
;
|
||||
clrsetbits_le32(cfg->reg, cfg->trg_mask, diff);
|
||||
|
||||
if (powered_by_linreg ||
|
||||
(readl(&power_regs->hw_power_sts) &
|
||||
POWER_STS_VDD5V_GT_VDDIO))
|
||||
early_delay(500);
|
||||
else {
|
||||
for (;;) {
|
||||
tmp = readl(&power_regs->hw_power_sts);
|
||||
if (tmp & POWER_STS_DC_OK)
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
cur_target = readl(&power_regs->hw_power_vdddctrl);
|
||||
cur_target &= POWER_VDDDCTRL_TRG_MASK;
|
||||
cur_target *= 25; /* 25 mV step*/
|
||||
cur_target += 800; /* 800 mV lowest */
|
||||
} while (new_target < cur_target);
|
||||
cur_target = readl(cfg->reg);
|
||||
cur_target &= cfg->trg_mask;
|
||||
cur_target *= cfg->step_mV;
|
||||
cur_target += cfg->lowest_mV;
|
||||
} while (new_target > cur_target);
|
||||
|
||||
if (adjust_up && powered_by_linreg) {
|
||||
writel(cfg->bo_irq, &power_regs->hw_power_ctrl_clr);
|
||||
if (bo_int & cfg->bo_enirq)
|
||||
setbits_le32(cfg->reg, cfg->bo_enirq);
|
||||
}
|
||||
|
||||
clrsetbits_le32(&power_regs->hw_power_vdddctrl,
|
||||
POWER_VDDDCTRL_BO_OFFSET_MASK,
|
||||
new_brownout << POWER_VDDDCTRL_BO_OFFSET_OFFSET);
|
||||
clrsetbits_le32(cfg->reg, cfg->bo_offset_mask,
|
||||
new_brownout << cfg->bo_offset_offset);
|
||||
}
|
||||
|
||||
void mxs_setup_batt_detect(void)
|
||||
static void mxs_setup_batt_detect(void)
|
||||
{
|
||||
mxs_lradc_init();
|
||||
mxs_lradc_enable_batt_measurement();
|
||||
|
@ -982,9 +896,8 @@ void mxs_power_init(void)
|
|||
mxs_power_configure_power_source();
|
||||
mxs_enable_output_rail_protection();
|
||||
|
||||
mxs_power_set_vddio(3300, 3150);
|
||||
|
||||
mxs_power_set_vddd(1350, 1200);
|
||||
mxs_power_set_vddx(&mxs_vddio_cfg, 3300, 3150);
|
||||
mxs_power_set_vddx(&mxs_vddd_cfg, 1500, 1000);
|
||||
|
||||
writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ |
|
||||
POWER_CTRL_VDDIO_BO_IRQ | POWER_CTRL_VDD5V_DROOP_IRQ |
|
||||
|
|
|
@ -33,6 +33,11 @@
|
|||
#include <i2c.h>
|
||||
#include <miiphy.h>
|
||||
#include <cpsw.h>
|
||||
#include <asm/errno.h>
|
||||
#include <linux/usb/ch9.h>
|
||||
#include <linux/usb/gadget.h>
|
||||
#include <linux/usb/musb.h>
|
||||
#include <asm/omap_musb.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
|
@ -63,3 +68,83 @@ void setup_clocks_for_console(void)
|
|||
/* Not yet implemented */
|
||||
return;
|
||||
}
|
||||
|
||||
/* AM33XX has two MUSB controllers which can be host or gadget */
|
||||
#if (defined(CONFIG_MUSB_GADGET) || defined(CONFIG_MUSB_HOST)) && \
|
||||
(defined(CONFIG_AM335X_USB0) || defined(CONFIG_AM335X_USB1))
|
||||
static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
|
||||
|
||||
/* USB 2.0 PHY Control */
|
||||
#define CM_PHY_PWRDN (1 << 0)
|
||||
#define CM_PHY_OTG_PWRDN (1 << 1)
|
||||
#define OTGVDET_EN (1 << 19)
|
||||
#define OTGSESSENDEN (1 << 20)
|
||||
|
||||
static void am33xx_usb_set_phy_power(u8 on, u32 *reg_addr)
|
||||
{
|
||||
if (on) {
|
||||
clrsetbits_le32(reg_addr, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN,
|
||||
OTGVDET_EN | OTGSESSENDEN);
|
||||
} else {
|
||||
clrsetbits_le32(reg_addr, 0, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN);
|
||||
}
|
||||
}
|
||||
|
||||
static struct musb_hdrc_config musb_config = {
|
||||
.multipoint = 1,
|
||||
.dyn_fifo = 1,
|
||||
.num_eps = 16,
|
||||
.ram_bits = 12,
|
||||
};
|
||||
|
||||
#ifdef CONFIG_AM335X_USB0
|
||||
static void am33xx_otg0_set_phy_power(u8 on)
|
||||
{
|
||||
am33xx_usb_set_phy_power(on, &cdev->usb_ctrl0);
|
||||
}
|
||||
|
||||
struct omap_musb_board_data otg0_board_data = {
|
||||
.set_phy_power = am33xx_otg0_set_phy_power,
|
||||
};
|
||||
|
||||
static struct musb_hdrc_platform_data otg0_plat = {
|
||||
.mode = CONFIG_AM335X_USB0_MODE,
|
||||
.config = &musb_config,
|
||||
.power = 50,
|
||||
.platform_ops = &musb_dsps_ops,
|
||||
.board_data = &otg0_board_data,
|
||||
};
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_AM335X_USB1
|
||||
static void am33xx_otg1_set_phy_power(u8 on)
|
||||
{
|
||||
am33xx_usb_set_phy_power(on, &cdev->usb_ctrl1);
|
||||
}
|
||||
|
||||
struct omap_musb_board_data otg1_board_data = {
|
||||
.set_phy_power = am33xx_otg1_set_phy_power,
|
||||
};
|
||||
|
||||
static struct musb_hdrc_platform_data otg1_plat = {
|
||||
.mode = CONFIG_AM335X_USB1_MODE,
|
||||
.config = &musb_config,
|
||||
.power = 50,
|
||||
.platform_ops = &musb_dsps_ops,
|
||||
.board_data = &otg1_board_data,
|
||||
};
|
||||
#endif
|
||||
#endif
|
||||
|
||||
int arch_misc_init(void)
|
||||
{
|
||||
#ifdef CONFIG_AM335X_USB0
|
||||
musb_register(&otg0_plat, &otg0_board_data,
|
||||
(void *)AM335X_USB0_OTG_BASE);
|
||||
#endif
|
||||
#ifdef CONFIG_AM335X_USB1
|
||||
musb_register(&otg1_plat, &otg1_board_data,
|
||||
(void *)AM335X_USB1_OTG_BASE);
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
|
|
@ -40,6 +40,7 @@
|
|||
#define CLK_MODE_MASK 0xfffffff8
|
||||
#define CLK_DIV_SEL 0xFFFFFFE0
|
||||
#define CPGMAC0_IDLE 0x30000
|
||||
#define DPLL_CLKDCOLDO_GATE_CTRL 0x300
|
||||
|
||||
const struct cm_perpll *cmper = (struct cm_perpll *)CM_PER;
|
||||
const struct cm_wkuppll *cmwkup = (struct cm_wkuppll *)CM_WKUP;
|
||||
|
@ -194,6 +195,11 @@ static void enable_per_clocks(void)
|
|||
writel(PRCM_MOD_EN, &cmrtc->rtcclkctrl);
|
||||
while (readl(&cmrtc->rtcclkctrl) != PRCM_MOD_EN)
|
||||
;
|
||||
|
||||
/* MUSB */
|
||||
writel(PRCM_MOD_EN, &cmper->usb0clkctrl);
|
||||
while (readl(&cmper->usb0clkctrl) != PRCM_MOD_EN)
|
||||
;
|
||||
}
|
||||
|
||||
static void mpu_pll_config(void)
|
||||
|
@ -290,6 +296,8 @@ static void per_pll_config(void)
|
|||
|
||||
while (readl(&cmwkup->idlestdpllper) != ST_DPLL_CLK)
|
||||
;
|
||||
|
||||
writel(DPLL_CLKDCOLDO_GATE_CTRL, &cmwkup->clkdcoldodpllper);
|
||||
}
|
||||
|
||||
void ddr_pll_config(unsigned int ddrpll_m)
|
||||
|
|
|
@ -921,6 +921,21 @@ static int exynos5_set_spi_clk(enum periph_id periph_id,
|
|||
return 0;
|
||||
}
|
||||
|
||||
static unsigned long exynos4_get_i2c_clk(void)
|
||||
{
|
||||
struct exynos4_clock *clk =
|
||||
(struct exynos4_clock *)samsung_get_base_clock();
|
||||
unsigned long sclk, aclk_100;
|
||||
unsigned int ratio;
|
||||
|
||||
sclk = get_pll_clk(APLL);
|
||||
|
||||
ratio = (readl(&clk->div_top)) >> 4;
|
||||
ratio &= 0xf;
|
||||
aclk_100 = sclk / (ratio + 1);
|
||||
return aclk_100;
|
||||
}
|
||||
|
||||
unsigned long get_pll_clk(int pllreg)
|
||||
{
|
||||
if (cpu_is_exynos5())
|
||||
|
@ -941,6 +956,8 @@ unsigned long get_i2c_clk(void)
|
|||
{
|
||||
if (cpu_is_exynos5()) {
|
||||
return exynos5_get_i2c_clk();
|
||||
} else if (cpu_is_exynos4()) {
|
||||
return exynos4_get_i2c_clk();
|
||||
} else {
|
||||
debug("I2C clock is not set for this CPU\n");
|
||||
return 0;
|
||||
|
|
|
@ -329,54 +329,60 @@ static int exynos5_pinmux_config(int peripheral, int flags)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int exynos4_mmc_config(int peripheral, int flags)
|
||||
static void exynos4_i2c_config(int peripheral, int flags)
|
||||
{
|
||||
struct exynos4_gpio_part2 *gpio2 =
|
||||
(struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
|
||||
struct s5p_gpio_bank *bank, *bank_ext;
|
||||
int i;
|
||||
struct exynos4_gpio_part1 *gpio1 =
|
||||
(struct exynos4_gpio_part1 *) samsung_get_base_gpio_part1();
|
||||
|
||||
switch (peripheral) {
|
||||
case PERIPH_ID_SDMMC0:
|
||||
bank = &gpio2->k0;
|
||||
bank_ext = &gpio2->k1;
|
||||
case PERIPH_ID_I2C0:
|
||||
s5p_gpio_cfg_pin(&gpio1->d1, 0, GPIO_FUNC(0x2));
|
||||
s5p_gpio_cfg_pin(&gpio1->d1, 1, GPIO_FUNC(0x2));
|
||||
break;
|
||||
case PERIPH_ID_SDMMC2:
|
||||
bank = &gpio2->k2;
|
||||
bank_ext = &gpio2->k3;
|
||||
case PERIPH_ID_I2C1:
|
||||
s5p_gpio_cfg_pin(&gpio1->d1, 2, GPIO_FUNC(0x2));
|
||||
s5p_gpio_cfg_pin(&gpio1->d1, 3, GPIO_FUNC(0x2));
|
||||
break;
|
||||
case PERIPH_ID_I2C2:
|
||||
s5p_gpio_cfg_pin(&gpio1->a0, 6, GPIO_FUNC(0x3));
|
||||
s5p_gpio_cfg_pin(&gpio1->a0, 7, GPIO_FUNC(0x3));
|
||||
break;
|
||||
case PERIPH_ID_I2C3:
|
||||
s5p_gpio_cfg_pin(&gpio1->a1, 2, GPIO_FUNC(0x3));
|
||||
s5p_gpio_cfg_pin(&gpio1->a1, 3, GPIO_FUNC(0x3));
|
||||
break;
|
||||
case PERIPH_ID_I2C4:
|
||||
s5p_gpio_cfg_pin(&gpio1->b, 2, GPIO_FUNC(0x3));
|
||||
s5p_gpio_cfg_pin(&gpio1->b, 3, GPIO_FUNC(0x3));
|
||||
break;
|
||||
case PERIPH_ID_I2C5:
|
||||
s5p_gpio_cfg_pin(&gpio1->b, 6, GPIO_FUNC(0x3));
|
||||
s5p_gpio_cfg_pin(&gpio1->b, 7, GPIO_FUNC(0x3));
|
||||
break;
|
||||
case PERIPH_ID_I2C6:
|
||||
s5p_gpio_cfg_pin(&gpio1->c1, 3, GPIO_FUNC(0x4));
|
||||
s5p_gpio_cfg_pin(&gpio1->c1, 4, GPIO_FUNC(0x4));
|
||||
break;
|
||||
case PERIPH_ID_I2C7:
|
||||
s5p_gpio_cfg_pin(&gpio1->d0, 2, GPIO_FUNC(0x3));
|
||||
s5p_gpio_cfg_pin(&gpio1->d0, 3, GPIO_FUNC(0x3));
|
||||
break;
|
||||
default:
|
||||
return -1;
|
||||
}
|
||||
for (i = 0; i < 7; i++) {
|
||||
if (i == 2)
|
||||
continue;
|
||||
s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
|
||||
s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
|
||||
s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
|
||||
}
|
||||
if (flags & PINMUX_FLAG_8BIT_MODE) {
|
||||
for (i = 3; i < 7; i++) {
|
||||
s5p_gpio_cfg_pin(bank_ext, i, GPIO_FUNC(0x3));
|
||||
s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_NONE);
|
||||
s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X);
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int exynos4_pinmux_config(int peripheral, int flags)
|
||||
{
|
||||
switch (peripheral) {
|
||||
case PERIPH_ID_SDMMC0:
|
||||
case PERIPH_ID_SDMMC2:
|
||||
return exynos4_mmc_config(peripheral, flags);
|
||||
case PERIPH_ID_SDMMC1:
|
||||
case PERIPH_ID_SDMMC3:
|
||||
case PERIPH_ID_SDMMC4:
|
||||
printf("SDMMC device %d not implemented\n", peripheral);
|
||||
return -1;
|
||||
case PERIPH_ID_I2C0:
|
||||
case PERIPH_ID_I2C1:
|
||||
case PERIPH_ID_I2C2:
|
||||
case PERIPH_ID_I2C3:
|
||||
case PERIPH_ID_I2C4:
|
||||
case PERIPH_ID_I2C5:
|
||||
case PERIPH_ID_I2C6:
|
||||
case PERIPH_ID_I2C7:
|
||||
exynos4_i2c_config(peripheral, flags);
|
||||
break;
|
||||
default:
|
||||
debug("%s: invalid peripheral %d", __func__, peripheral);
|
||||
return -1;
|
||||
|
|
|
@ -38,6 +38,7 @@ endif
|
|||
COBJS-$(CONFIG_DRIVER_TI_EMAC) += emac.o
|
||||
COBJS-$(CONFIG_EMIF4) += emif4.o
|
||||
COBJS-$(CONFIG_SDRC) += sdrc.o
|
||||
COBJS-$(CONFIG_USB_MUSB_AM35X) += am35x_musb.o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS) $(COBJS-y) $(SOBJS))
|
||||
|
|
75
arch/arm/cpu/armv7/omap3/am35x_musb.c
Normal file
75
arch/arm/cpu/armv7/omap3/am35x_musb.c
Normal file
|
@ -0,0 +1,75 @@
|
|||
/*
|
||||
* This file configures the internal USB PHY in AM35X.
|
||||
*
|
||||
* Copyright (C) 2012 Ilya Yanok <ilya.yanok@gmail.com>
|
||||
*
|
||||
* Based on omap_phy_internal.c code from Linux by
|
||||
* Hema HK <hemahk@ti.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/am35x_def.h>
|
||||
|
||||
void am35x_musb_reset(void)
|
||||
{
|
||||
/* Reset the musb interface */
|
||||
clrsetbits_le32(&am35x_scm_general_regs->ip_sw_reset,
|
||||
0, USBOTGSS_SW_RST);
|
||||
clrsetbits_le32(&am35x_scm_general_regs->ip_sw_reset,
|
||||
USBOTGSS_SW_RST, 0);
|
||||
}
|
||||
|
||||
void am35x_musb_phy_power(u8 on)
|
||||
{
|
||||
unsigned long start = get_timer(0);
|
||||
|
||||
if (on) {
|
||||
/*
|
||||
* Start the on-chip PHY and its PLL.
|
||||
*/
|
||||
clrsetbits_le32(&am35x_scm_general_regs->devconf2,
|
||||
CONF2_RESET | CONF2_PHYPWRDN | CONF2_OTGPWRDN,
|
||||
CONF2_PHY_PLLON);
|
||||
|
||||
debug("Waiting for PHY clock good...\n");
|
||||
while (!(readl(&am35x_scm_general_regs->devconf2)
|
||||
& CONF2_PHYCLKGD)) {
|
||||
|
||||
if (get_timer(start) > CONFIG_SYS_HZ / 10) {
|
||||
printf("musb PHY clock good timed out\n");
|
||||
break;
|
||||
}
|
||||
}
|
||||
} else {
|
||||
/*
|
||||
* Power down the on-chip PHY.
|
||||
*/
|
||||
clrsetbits_le32(&am35x_scm_general_regs->devconf2,
|
||||
CONF2_PHY_PLLON,
|
||||
CONF2_PHYPWRDN | CONF2_OTGPWRDN);
|
||||
}
|
||||
}
|
||||
|
||||
void am35x_musb_clear_irq(void)
|
||||
{
|
||||
clrsetbits_le32(&am35x_scm_general_regs->lvl_intr_clr,
|
||||
0, USBOTGSS_INT_CLR);
|
||||
readl(&am35x_scm_general_regs->lvl_intr_clr);
|
||||
}
|
||||
|
|
@ -82,7 +82,8 @@ struct cm_wkuppll {
|
|||
unsigned int clkseldpllcore; /* offset 0x68 */
|
||||
unsigned int resv9[1];
|
||||
unsigned int idlestdpllper; /* offset 0x70 */
|
||||
unsigned int resv10[3];
|
||||
unsigned int resv10[2];
|
||||
unsigned int clkdcoldodpllper; /* offset 0x7c */
|
||||
unsigned int divm4dpllcore; /* offset 0x80 */
|
||||
unsigned int divm5dpllcore; /* offset 0x84 */
|
||||
unsigned int clkmoddpllmpu; /* offset 0x88 */
|
||||
|
@ -275,12 +276,16 @@ struct ctrl_stat {
|
|||
/* Control Device Register */
|
||||
struct ctrl_dev {
|
||||
unsigned int deviceid; /* offset 0x00 */
|
||||
unsigned int resv1[11];
|
||||
unsigned int resv1[7];
|
||||
unsigned int usb_ctrl0; /* offset 0x20 */
|
||||
unsigned int resv2;
|
||||
unsigned int usb_ctrl1; /* offset 0x28 */
|
||||
unsigned int resv3;
|
||||
unsigned int macid0l; /* offset 0x30 */
|
||||
unsigned int macid0h; /* offset 0x34 */
|
||||
unsigned int macid1l; /* offset 0x38 */
|
||||
unsigned int macid1h; /* offset 0x3c */
|
||||
unsigned int resv2[4];
|
||||
unsigned int resv4[4];
|
||||
unsigned int miisel; /* offset 0x50 */
|
||||
};
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
|
|
@ -87,4 +87,8 @@
|
|||
/* RTC base address */
|
||||
#define AM335X_RTC_BASE 0x44E3E000
|
||||
|
||||
/* OTG */
|
||||
#define AM335X_USB0_OTG_BASE 0x47401000
|
||||
#define AM335X_USB1_OTG_BASE 0x47401800
|
||||
|
||||
#endif /* __AM33XX_HARDWARE_H */
|
||||
|
|
|
@ -28,6 +28,8 @@
|
|||
#define EXYNOS4_ADDR_BASE 0x10000000
|
||||
|
||||
/* EXYNOS4 */
|
||||
#define EXYNOS4_I2C_SPACING 0x10000
|
||||
|
||||
#define EXYNOS4_GPIO_PART3_BASE 0x03860000
|
||||
#define EXYNOS4_PRO_ID 0x10000000
|
||||
#define EXYNOS4_SYSREG_BASE 0x10010000
|
||||
|
|
36
arch/arm/include/asm/arch-exynos/dwmmc.h
Normal file
36
arch/arm/include/asm/arch-exynos/dwmmc.h
Normal file
|
@ -0,0 +1,36 @@
|
|||
/*
|
||||
* (C) Copyright 2012 SAMSUNG Electronics
|
||||
* Jaehoon Chung <jh80.chung@samsung.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*
|
||||
*/
|
||||
|
||||
#define DWMCI_CLKSEL 0x09C
|
||||
#define DWMCI_SHIFT_0 0x0
|
||||
#define DWMCI_SHIFT_1 0x1
|
||||
#define DWMCI_SHIFT_2 0x2
|
||||
#define DWMCI_SHIFT_3 0x3
|
||||
#define DWMCI_SET_SAMPLE_CLK(x) (x)
|
||||
#define DWMCI_SET_DRV_CLK(x) ((x) << 16)
|
||||
#define DWMCI_SET_DIV_RATIO(x) ((x) << 24)
|
||||
|
||||
int exynos_dwmci_init(u32 regbase, int bus_width, int index);
|
||||
|
||||
static inline unsigned int exynos_dwmmc_init(int index, int bus_width)
|
||||
{
|
||||
unsigned int base = samsung_get_base_mmc() + (0x10000 * index);
|
||||
return exynos_dwmci_init(base, bus_width, index);
|
||||
}
|
|
@ -35,6 +35,7 @@ enum mxc_clock {
|
|||
MXC_SSP1_CLK,
|
||||
MXC_SSP2_CLK,
|
||||
MXC_SSP3_CLK,
|
||||
MXC_XTAL_CLK,
|
||||
};
|
||||
|
||||
enum mxs_ioclock {
|
||||
|
|
|
@ -26,7 +26,6 @@
|
|||
#include <asm/arch/regs-apbh.h>
|
||||
#include <asm/arch/regs-base.h>
|
||||
#include <asm/arch/regs-bch.h>
|
||||
#include <asm/arch/regs-clkctrl-mx28.h>
|
||||
#include <asm/arch/regs-digctl.h>
|
||||
#include <asm/arch/regs-gpmi.h>
|
||||
#include <asm/arch/regs-i2c.h>
|
||||
|
@ -34,9 +33,13 @@
|
|||
#include <asm/arch/regs-lradc.h>
|
||||
#include <asm/arch/regs-ocotp.h>
|
||||
#include <asm/arch/regs-pinctrl.h>
|
||||
#include <asm/arch/regs-power.h>
|
||||
#include <asm/arch/regs-rtc.h>
|
||||
#include <asm/arch/regs-ssp.h>
|
||||
#include <asm/arch/regs-timrot.h>
|
||||
|
||||
#ifdef CONFIG_MX28
|
||||
#include <asm/arch/regs-clkctrl-mx28.h>
|
||||
#include <asm/arch/regs-power-mx28.h>
|
||||
#endif
|
||||
|
||||
#endif /* __IMX_REGS_H__ */
|
||||
|
|
|
@ -31,9 +31,11 @@
|
|||
#ifndef __ASSEMBLY__
|
||||
struct mxs_clkctrl_regs {
|
||||
mxs_reg_32(hw_clkctrl_pll0ctrl0) /* 0x00 */
|
||||
mxs_reg_32(hw_clkctrl_pll0ctrl1) /* 0x10 */
|
||||
uint32_t hw_clkctrl_pll0ctrl1; /* 0x10 */
|
||||
uint32_t reserved_pll0ctrl1[3]; /* 0x14-0x1c */
|
||||
mxs_reg_32(hw_clkctrl_pll1ctrl0) /* 0x20 */
|
||||
mxs_reg_32(hw_clkctrl_pll1ctrl1) /* 0x30 */
|
||||
uint32_t hw_clkctrl_pll1ctrl1; /* 0x30 */
|
||||
uint32_t reserved_pll1ctrl1[3]; /* 0x34-0x3c */
|
||||
mxs_reg_32(hw_clkctrl_pll2ctrl0) /* 0x40 */
|
||||
mxs_reg_32(hw_clkctrl_cpu) /* 0x50 */
|
||||
mxs_reg_32(hw_clkctrl_hbus) /* 0x60 */
|
||||
|
|
|
@ -32,9 +32,34 @@
|
|||
#ifndef __KERNEL_STRICT_NAMES
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
/* LVL_INTR_CLEAR bits */
|
||||
#define USBOTGSS_INT_CLR (1 << 4)
|
||||
|
||||
/* IP_SW_RESET bits */
|
||||
#define USBOTGSS_SW_RST (1 << 0) /* reset USBOTG */
|
||||
#define CPGMACSS_SW_RST (1 << 1) /* reset CPGMAC */
|
||||
|
||||
/* DEVCONF2 bits */
|
||||
#define CONF2_PHY_GPIOMODE (1 << 23)
|
||||
#define CONF2_OTGMODE (3 << 14)
|
||||
#define CONF2_NO_OVERRIDE (0 << 14)
|
||||
#define CONF2_FORCE_HOST (1 << 14)
|
||||
#define CONF2_FORCE_DEVICE (2 << 14)
|
||||
#define CONF2_FORCE_HOST_VBUS_LOW (3 << 14)
|
||||
#define CONF2_SESENDEN (1 << 13)
|
||||
#define CONF2_VBDTCTEN (1 << 12)
|
||||
#define CONF2_REFFREQ_24MHZ (2 << 8)
|
||||
#define CONF2_REFFREQ_26MHZ (7 << 8)
|
||||
#define CONF2_REFFREQ_13MHZ (6 << 8)
|
||||
#define CONF2_REFFREQ (0xf << 8)
|
||||
#define CONF2_PHYCLKGD (1 << 7)
|
||||
#define CONF2_VBUSSENSE (1 << 6)
|
||||
#define CONF2_PHY_PLLON (1 << 5)
|
||||
#define CONF2_RESET (1 << 4)
|
||||
#define CONF2_PHYPWRDN (1 << 3)
|
||||
#define CONF2_OTGPWRDN (1 << 2)
|
||||
#define CONF2_DATPOL (1 << 1)
|
||||
|
||||
/* General register mappings of system control module */
|
||||
#define AM35X_SCM_GEN_BASE 0x48002270
|
||||
struct am35x_scm_general {
|
||||
|
@ -49,6 +74,8 @@ struct am35x_scm_general {
|
|||
};
|
||||
#define am35x_scm_general_regs ((struct am35x_scm_general *)AM35X_SCM_GEN_BASE)
|
||||
|
||||
#define AM35XX_IPSS_USBOTGSS_BASE 0x5C040000
|
||||
|
||||
#endif /*__ASSEMBLY__ */
|
||||
#endif /* __KERNEL_STRICT_NAMES */
|
||||
|
||||
|
|
|
@ -1,7 +1,6 @@
|
|||
/*
|
||||
* Copyright (c) 2011 The Chromium OS Authors.
|
||||
* (C) Copyright 2008
|
||||
* Graeme Russ, graeme.russ@gmail.com.
|
||||
* (C) Copyright 2012
|
||||
* Ilya Yanok, <ilya.yanok@gmail.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
|
@ -18,29 +17,12 @@
|
|||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
* Foundation, Inc.
|
||||
*/
|
||||
|
||||
/*
|
||||
* 16bit initialization code.
|
||||
* This code have to map the area of the boot flash
|
||||
* that is used by U-boot to its final destination.
|
||||
*/
|
||||
|
||||
.text
|
||||
.section .start16, "ax"
|
||||
.code16
|
||||
.globl board_init16
|
||||
board_init16:
|
||||
jmp board_init16_ret
|
||||
|
||||
.section .bios, "ax"
|
||||
.code16
|
||||
.globl realmode_reset
|
||||
.hidden realmode_reset
|
||||
.type realmode_reset, @function
|
||||
realmode_reset:
|
||||
|
||||
1: hlt
|
||||
jmp 1
|
||||
#ifndef __ASM_ARCH_OMAP3_MUSB_H
|
||||
#define __ASM_ARCH_OMAP3_MUSB_H
|
||||
extern void am35x_musb_reset(void);
|
||||
extern void am35x_musb_phy_power(u8 on);
|
||||
extern void am35x_musb_clear_irq(void);
|
||||
#endif
|
21
arch/arm/include/asm/imx-common/mx5_video.h
Normal file
21
arch/arm/include/asm/imx-common/mx5_video.h
Normal file
|
@ -0,0 +1,21 @@
|
|||
/*
|
||||
* Copyright (C) 2012
|
||||
* Anatolij Gustschin, DENX Software Engineering, <agust@denx.de>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*/
|
||||
#ifndef __MX5_VIDEO_H
|
||||
#define __MX5_VIDEO_H
|
||||
|
||||
#ifdef CONFIG_VIDEO
|
||||
void lcd_enable(void);
|
||||
void setup_iomux_lcd(void);
|
||||
#else
|
||||
static inline void lcd_enable(void) { }
|
||||
static inline void setup_iomux_lcd(void) { }
|
||||
#endif
|
||||
|
||||
#endif
|
32
arch/arm/include/asm/omap_musb.h
Normal file
32
arch/arm/include/asm/omap_musb.h
Normal file
|
@ -0,0 +1,32 @@
|
|||
/*
|
||||
* Board data structure for musb gadget on OMAPs
|
||||
*
|
||||
* Copyright (C) 2012, Ilya Yanok <ilya.yanok@gmail.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARM_OMAP_MUSB_H
|
||||
#define __ASM_ARM_OMAP_MUSB_H
|
||||
|
||||
extern struct musb_platform_ops musb_dsps_ops;
|
||||
extern const struct musb_platform_ops am35x_ops;
|
||||
extern const struct musb_platform_ops omap2430_ops;
|
||||
|
||||
struct omap_musb_board_data {
|
||||
u8 interface_type;
|
||||
void (*set_phy_power)(u8 on);
|
||||
void (*clear_irq)(void);
|
||||
void (*reset)(void);
|
||||
};
|
||||
|
||||
enum musb_interface {MUSB_INTERFACE_ULPI, MUSB_INTERFACE_UTMI};
|
||||
#endif /* __ASM_ARM_OMAP_MUSB_H */
|
|
@ -224,6 +224,13 @@ int __arch_cpu_init(void)
|
|||
int arch_cpu_init(void)
|
||||
__attribute__((weak, alias("__arch_cpu_init")));
|
||||
|
||||
int __power_init_board(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
int power_init_board(void)
|
||||
__attribute__((weak, alias("__power_init_board")));
|
||||
|
||||
init_fnc_t *init_sequence[] = {
|
||||
arch_cpu_init, /* basic arch cpu dependent setup */
|
||||
|
||||
|
@ -525,6 +532,7 @@ void board_init_r(gd_t *id, ulong dest_addr)
|
|||
#ifdef CONFIG_ARCH_EARLY_INIT_R
|
||||
arch_early_init_r();
|
||||
#endif
|
||||
power_init_board();
|
||||
|
||||
#if !defined(CONFIG_SYS_NO_FLASH)
|
||||
puts("Flash: ");
|
||||
|
@ -532,15 +540,13 @@ void board_init_r(gd_t *id, ulong dest_addr)
|
|||
flash_size = flash_init();
|
||||
if (flash_size > 0) {
|
||||
# ifdef CONFIG_SYS_FLASH_CHECKSUM
|
||||
char *s = getenv("flashchecksum");
|
||||
|
||||
print_size(flash_size, "");
|
||||
/*
|
||||
* Compute and print flash CRC if flashchecksum is set to 'y'
|
||||
*
|
||||
* NOTE: Maybe we should add some WATCHDOG_RESET()? XXX
|
||||
*/
|
||||
if (s && (*s == 'y')) {
|
||||
if (getenv_yesno("flashchecksum") == 1) {
|
||||
printf(" CRC: %08X", crc32(0,
|
||||
(const unsigned char *) CONFIG_SYS_FLASH_BASE,
|
||||
flash_size));
|
||||
|
|
|
@ -16,7 +16,7 @@
|
|||
#endif
|
||||
|
||||
extern int strcasecmp(const char *, const char *);
|
||||
extern int strncasecmp(const char *, const char *, int);
|
||||
extern int strncasecmp(const char *, const char *, __kernel_size_t);
|
||||
extern char * strcpy(char *,const char *);
|
||||
extern char * strncpy(char *,const char *, __kernel_size_t);
|
||||
extern __kernel_size_t strlen(const char *);
|
||||
|
|
|
@ -462,8 +462,7 @@ void board_init_r (gd_t *id, ulong dest_addr)
|
|||
*
|
||||
* NOTE: Maybe we should add some WATCHDOG_RESET()? XXX
|
||||
*/
|
||||
s = getenv ("flashchecksum");
|
||||
if (s && (*s == 'y')) {
|
||||
if (getenv_yesno("flashchecksum") == 1) {
|
||||
printf (" CRC: %08X",
|
||||
crc32 (0,
|
||||
(const unsigned char *) CONFIG_SYS_FLASH_BASE,
|
||||
|
|
|
@ -74,7 +74,6 @@ void board_init_f(ulong not_used)
|
|||
gd = (gd_t *) (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_GBL_DATA_OFFSET);
|
||||
bd = (bd_t *) (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_GBL_DATA_OFFSET \
|
||||
- GENERATED_BD_INFO_SIZE);
|
||||
__maybe_unused char *s;
|
||||
#if defined(CONFIG_CMD_FLASH)
|
||||
ulong flash_size = 0;
|
||||
#endif
|
||||
|
@ -143,8 +142,7 @@ void board_init_f(ulong not_used)
|
|||
*
|
||||
* NOTE: Maybe we should add some WATCHDOG_RESET()? XXX
|
||||
*/
|
||||
s = getenv ("flashchecksum");
|
||||
if (s && (*s == 'y')) {
|
||||
if (getenv_yesno("flashchecksum") == 1) {
|
||||
printf (" CRC: %08X",
|
||||
crc32(0, (const u8 *)bd->bi_flashstart,
|
||||
flash_size)
|
||||
|
|
|
@ -615,7 +615,7 @@ static ed_t * ep_add_ed (struct usb_device *usb_dev, unsigned long pipe)
|
|||
| usb_pipeendpoint (pipe) << 7
|
||||
| (usb_pipeisoc (pipe)? 0x8000: 0)
|
||||
| (usb_pipecontrol (pipe)? 0: (usb_pipeout (pipe)? 0x800: 0x1000))
|
||||
| usb_pipeslow (pipe) << 13
|
||||
| (usb_dev->speed == USB_SPEED_LOW) << 13
|
||||
| usb_maxpacket (usb_dev, pipe) << 16);
|
||||
|
||||
return ed_ret;
|
||||
|
|
|
@ -36,7 +36,6 @@ static unsigned long timestamp;
|
|||
int timer_init(void)
|
||||
{
|
||||
/* Set up the timer for the first expiration. */
|
||||
timestamp = 0;
|
||||
write_c0_compare(read_c0_count() + CYCLES_PER_JIFFY);
|
||||
|
||||
return 0;
|
||||
|
|
|
@ -108,7 +108,12 @@ reset:
|
|||
mtc0 t0, CP0_CONFIG
|
||||
#endif
|
||||
|
||||
/* Initialize $gp */
|
||||
/*
|
||||
* Initialize $gp, force 8 byte alignment of bal instruction to forbid
|
||||
* the compiler to put nop's between bal and _gp. This is required to
|
||||
* keep _gp and ra aligned to 8 byte.
|
||||
*/
|
||||
.align 3
|
||||
bal 1f
|
||||
nop
|
||||
.dword _gp
|
||||
|
|
|
@ -37,7 +37,6 @@ static unsigned long timestamp;
|
|||
int timer_init(void)
|
||||
{
|
||||
/* Set up the timer for the first expiration. */
|
||||
timestamp = 0;
|
||||
write_c0_compare(read_c0_count() + CYCLES_PER_JIFFY);
|
||||
|
||||
return 0;
|
||||
|
|
|
@ -566,7 +566,7 @@ static __inline__ int __test_and_change_bit(int nr, volatile void * addr)
|
|||
* @nr: bit number to test
|
||||
* @addr: Address to start counting from
|
||||
*/
|
||||
static __inline__ int test_bit(int nr, volatile void *addr)
|
||||
static __inline__ int test_bit(int nr, const volatile void *addr)
|
||||
{
|
||||
return ((1UL << (nr & 31)) & (((const unsigned int *) addr)[nr >> 5])) != 0;
|
||||
}
|
||||
|
|
|
@ -24,6 +24,7 @@
|
|||
#include <common.h>
|
||||
#include <command.h>
|
||||
#include <malloc.h>
|
||||
#include <serial.h>
|
||||
#include <stdio_dev.h>
|
||||
#include <version.h>
|
||||
#include <net.h>
|
||||
|
@ -46,7 +47,7 @@ static char *failed = "*** failed ***\n";
|
|||
* mips_io_port_base is the begin of the address space to which x86 style
|
||||
* I/O ports are mapped.
|
||||
*/
|
||||
unsigned long mips_io_port_base = -1;
|
||||
const unsigned long mips_io_port_base = -1;
|
||||
|
||||
int __board_early_init_f(void)
|
||||
{
|
||||
|
@ -262,6 +263,8 @@ void board_init_r(gd_t *id, ulong dest_addr)
|
|||
|
||||
monitor_flash_len = (ulong)&uboot_end_data - dest_addr;
|
||||
|
||||
serial_initialize();
|
||||
|
||||
#if defined(CONFIG_NEEDS_MANUAL_RELOC)
|
||||
/*
|
||||
* We have to relocate the command table manually
|
||||
|
|
|
@ -42,3 +42,8 @@ endif
|
|||
ifeq ($(CROSS_COMPILE),powerpc-openbsd-)
|
||||
PLATFORM_CPPFLAGS+= -D__PPC__
|
||||
endif
|
||||
|
||||
# Only test once
|
||||
ifneq ($(CONFIG_SPL_BUILD),y)
|
||||
ALL-y += checkgcc4
|
||||
endif
|
||||
|
|
|
@ -41,6 +41,10 @@ COBJS-y += speed.o
|
|||
COBJS-$(CONFIG_CMD_USB) += usb_ohci.o
|
||||
COBJS-$(CONFIG_CMD_USB) += usb.o
|
||||
|
||||
ifdef CONFIG_SPL_BUILD
|
||||
COBJS-y += spl_boot.o
|
||||
endif
|
||||
|
||||
SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y))
|
||||
START := $(addprefix $(obj),$(SSTART) $(CSTART))
|
||||
|
|
79
arch/powerpc/cpu/mpc5xxx/spl_boot.c
Normal file
79
arch/powerpc/cpu/mpc5xxx/spl_boot.c
Normal file
|
@ -0,0 +1,79 @@
|
|||
/*
|
||||
* Copyright (C) 2012 Stefan Roese <sr@denx.de>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <spl.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
/*
|
||||
* Needed to align size SPL image to a 4-byte length
|
||||
*/
|
||||
u32 end_align __attribute__ ((section(".end_align")));
|
||||
|
||||
/*
|
||||
* Return selected boot device. On MPC5200 its only NOR flash right now.
|
||||
*/
|
||||
u32 spl_boot_device(void)
|
||||
{
|
||||
return BOOT_DEVICE_NOR;
|
||||
}
|
||||
|
||||
/*
|
||||
* SPL version of board_init_f()
|
||||
*/
|
||||
void board_init_f(ulong bootflag)
|
||||
{
|
||||
end_align = (u32)__spl_flash_end;
|
||||
|
||||
/*
|
||||
* First we need to initialize the SDRAM, so that the real
|
||||
* U-Boot or the OS (Linux) can be loaded
|
||||
*/
|
||||
initdram(0);
|
||||
|
||||
/* Clear bss */
|
||||
memset(__bss_start, '\0', __bss_end__ - __bss_start);
|
||||
|
||||
/*
|
||||
* Init global_data pointer. Has to be done before calling
|
||||
* get_clocks(), as it stores some clock values into gd needed
|
||||
* later on in the serial driver.
|
||||
*/
|
||||
/* Pointer is writable since we allocated a register for it */
|
||||
gd = (gd_t *)(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
|
||||
/* Clear initial global data */
|
||||
memset((void *)gd, 0, sizeof(gd_t));
|
||||
|
||||
/*
|
||||
* get_clocks() needs to be called so that the serial driver
|
||||
* works correctly
|
||||
*/
|
||||
get_clocks();
|
||||
|
||||
/*
|
||||
* Do rudimental console / serial setup
|
||||
*/
|
||||
preloader_console_init();
|
||||
|
||||
/*
|
||||
* Call board_init_r() (SPL framework version) to load and boot
|
||||
* real U-Boot or OS
|
||||
*/
|
||||
board_init_r(NULL, 0);
|
||||
/* Does not return!!! */
|
||||
}
|
|
@ -50,6 +50,7 @@
|
|||
#define MSR_KERNEL (MSR_FP|MSR_ME|MSR_RI)
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_SPL_BUILD
|
||||
/*
|
||||
* Set up GOT: Global Offset Table
|
||||
*
|
||||
|
@ -68,6 +69,7 @@
|
|||
GOT_ENTRY(__bss_end__)
|
||||
GOT_ENTRY(__bss_start)
|
||||
END_GOT
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Version string
|
||||
|
@ -84,6 +86,18 @@ version_string:
|
|||
. = EXC_OFF_SYS_RESET
|
||||
.globl _start
|
||||
_start:
|
||||
|
||||
#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
|
||||
/*
|
||||
* This is the entry of the real U-Boot from a board port
|
||||
* that supports SPL booting on the MPC5200. We only need
|
||||
* to call board_init_f() here. Everything else has already
|
||||
* been done in the SPL u-boot version.
|
||||
*/
|
||||
GET_GOT /* initialize GOT access */
|
||||
bl board_init_f /* run 1st part of board init code (in Flash)*/
|
||||
/* NOTREACHED - board_init_f() does not return */
|
||||
#else
|
||||
mfmsr r5 /* save msr contents */
|
||||
|
||||
/* Move CSBoot and adjust instruction pointer */
|
||||
|
@ -152,7 +166,9 @@ lowboot_reentry:
|
|||
/* Be careful to keep code relocatable ! */
|
||||
/*--------------------------------------------------------------*/
|
||||
|
||||
#ifndef CONFIG_SPL_BUILD
|
||||
GET_GOT /* initialize GOT access */
|
||||
#endif
|
||||
|
||||
/* r3: IMMR */
|
||||
bl cpu_init_f /* run low-level CPU init code (in Flash)*/
|
||||
|
@ -160,7 +176,9 @@ lowboot_reentry:
|
|||
bl board_init_f /* run 1st part of board init code (in Flash)*/
|
||||
|
||||
/* NOTREACHED - board_init_f() does not return */
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_SPL_BUILD
|
||||
/*
|
||||
* Vector Table
|
||||
*/
|
||||
|
@ -333,6 +351,7 @@ int_return:
|
|||
lwz r1,GPR1(r1)
|
||||
SYNC
|
||||
rfi
|
||||
#endif /* CONFIG_SPL_BUILD */
|
||||
|
||||
/*
|
||||
* This code initialises the MPC5xxx processor core
|
||||
|
@ -522,6 +541,7 @@ get_pvr:
|
|||
mfspr r3, PVR
|
||||
blr
|
||||
|
||||
#ifndef CONFIG_SPL_BUILD
|
||||
/*------------------------------------------------------------------------------*/
|
||||
|
||||
/*
|
||||
|
@ -759,3 +779,5 @@ trap_init:
|
|||
|
||||
mtlr r4 /* restore link register */
|
||||
blr
|
||||
|
||||
#endif /* CONFIG_SPL_BUILD */
|
||||
|
|
57
arch/powerpc/cpu/mpc5xxx/u-boot-spl.lds
Normal file
57
arch/powerpc/cpu/mpc5xxx/u-boot-spl.lds
Normal file
|
@ -0,0 +1,57 @@
|
|||
/*
|
||||
* Copyright 2012 Stefan Roese <sr@denx.de>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
MEMORY
|
||||
{
|
||||
sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR,
|
||||
LENGTH = CONFIG_SPL_BSS_MAX_SIZE
|
||||
flash : ORIGIN = CONFIG_SPL_TEXT_BASE,
|
||||
LENGTH = CONFIG_SYS_SPL_MAX_LEN
|
||||
}
|
||||
|
||||
OUTPUT_ARCH(powerpc)
|
||||
ENTRY(_start)
|
||||
SECTIONS
|
||||
{
|
||||
.text :
|
||||
{
|
||||
__start = .;
|
||||
arch/powerpc/cpu/mpc5xxx/start.o (.text)
|
||||
*(.text*)
|
||||
} > flash
|
||||
|
||||
. = ALIGN(4);
|
||||
.data : { *(SORT_BY_ALIGNMENT(.data*)) } > flash
|
||||
|
||||
. = ALIGN(4);
|
||||
.rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } > flash
|
||||
|
||||
. = ALIGN(4);
|
||||
.end_align : { *(.end_align*) } > flash
|
||||
__spl_flash_end = .;
|
||||
|
||||
.bss :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__bss_start = .;
|
||||
*(.bss*)
|
||||
. = ALIGN(4);
|
||||
__bss_end__ = .;
|
||||
} > sdram
|
||||
}
|
|
@ -618,7 +618,7 @@ static ed_t * ep_add_ed (struct usb_device *usb_dev, unsigned long pipe)
|
|||
| usb_pipeendpoint (pipe) << 7
|
||||
| (usb_pipeisoc (pipe)? 0x8000: 0)
|
||||
| (usb_pipecontrol (pipe)? 0: (usb_pipeout (pipe)? 0x800: 0x1000))
|
||||
| usb_pipeslow (pipe) << 13
|
||||
| (usb_dev->speed == USB_SPEED_LOW) << 13
|
||||
| usb_maxpacket (usb_dev, pipe) << 16);
|
||||
|
||||
return ed_ret;
|
||||
|
|
|
@ -28,7 +28,22 @@ include $(TOPDIR)/config.mk
|
|||
|
||||
LIB = $(obj)lib$(CPU).o
|
||||
|
||||
START = start.o resetvec.o
|
||||
MINIMAL=
|
||||
|
||||
ifdef CONFIG_SPL_BUILD
|
||||
ifdef CONFIG_SPL_INIT_MINIMAL
|
||||
MINIMAL=y
|
||||
endif
|
||||
endif
|
||||
|
||||
START = start.o resetvec.o
|
||||
|
||||
ifdef MINIMAL
|
||||
|
||||
COBJS-y += cpu_init_early.o tlb.o spl_minimal.o
|
||||
|
||||
else
|
||||
|
||||
SOBJS-$(CONFIG_MP) += release.o
|
||||
SOBJS = $(SOBJS-y)
|
||||
|
||||
|
@ -121,17 +136,20 @@ COBJS-$(CONFIG_PPC_P5040) += p5040_serdes.o
|
|||
COBJS-$(CONFIG_PPC_T4240) += t4240_serdes.o
|
||||
COBJS-$(CONFIG_PPC_B4860) += b4860_serdes.o
|
||||
|
||||
COBJS = $(COBJS-y)
|
||||
COBJS += cpu.o
|
||||
COBJS += cpu_init.o
|
||||
COBJS += cpu_init_early.o
|
||||
COBJS += interrupts.o
|
||||
COBJS += speed.o
|
||||
COBJS += tlb.o
|
||||
COBJS += traps.o
|
||||
COBJS-y += cpu.o
|
||||
COBJS-y += cpu_init.o
|
||||
COBJS-y += cpu_init_early.o
|
||||
COBJS-y += interrupts.o
|
||||
COBJS-y += speed.o
|
||||
COBJS-y += tlb.o
|
||||
COBJS-y += traps.o
|
||||
|
||||
# Stub implementations of cache management functions for USB
|
||||
COBJS += cache.o
|
||||
COBJS-y += cache.o
|
||||
|
||||
endif # not minimal
|
||||
|
||||
COBJS = $(COBJS-y)
|
||||
|
||||
SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
|
||||
|
|
|
@ -24,6 +24,109 @@
|
|||
#include <command.h>
|
||||
#include <linux/compiler.h>
|
||||
#include <asm/processor.h>
|
||||
#include "fsl_corenet_serdes.h"
|
||||
|
||||
#ifdef CONFIG_SYS_FSL_ERRATUM_A004849
|
||||
/*
|
||||
* This work-around is implemented in PBI, so just check to see if the
|
||||
* work-around was actually applied. To do this, we check for specific data
|
||||
* at specific addresses in DCSR.
|
||||
*
|
||||
* Array offsets[] contains a list of offsets within DCSR. According to the
|
||||
* erratum document, the value at each offset should be 2.
|
||||
*/
|
||||
static void check_erratum_a4849(uint32_t svr)
|
||||
{
|
||||
void __iomem *dcsr = (void *)CONFIG_SYS_DCSRBAR + 0xb0000;
|
||||
unsigned int i;
|
||||
|
||||
#if defined(CONFIG_PPC_P2041) || defined(CONFIG_PPC_P3041)
|
||||
static const uint8_t offsets[] = {
|
||||
0x50, 0x54, 0x58, 0x90, 0x94, 0x98
|
||||
};
|
||||
#endif
|
||||
#ifdef CONFIG_PPC_P4080
|
||||
static const uint8_t offsets[] = {
|
||||
0x60, 0x64, 0x68, 0x6c, 0xa0, 0xa4, 0xa8, 0xac
|
||||
};
|
||||
#endif
|
||||
uint32_t x108; /* The value that should be at offset 0x108 */
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(offsets); i++) {
|
||||
if (in_be32(dcsr + offsets[i]) != 2) {
|
||||
printf("Work-around for Erratum A004849 is not enabled\n");
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
#if defined(CONFIG_PPC_P2041) || defined(CONFIG_PPC_P3041)
|
||||
x108 = 0x12;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PPC_P4080
|
||||
/*
|
||||
* For P4080, the erratum document says that the value at offset 0x108
|
||||
* should be 0x12 on rev2, or 0x1c on rev3.
|
||||
*/
|
||||
if (SVR_MAJ(svr) == 2)
|
||||
x108 = 0x12;
|
||||
if (SVR_MAJ(svr) == 3)
|
||||
x108 = 0x1c;
|
||||
#endif
|
||||
|
||||
if (in_be32(dcsr + 0x108) != x108) {
|
||||
printf("Work-around for Erratum A004849 is not enabled\n");
|
||||
return;
|
||||
}
|
||||
|
||||
/* Everything matches, so the erratum work-around was applied */
|
||||
|
||||
printf("Work-around for Erratum A004849 enabled\n");
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_FSL_ERRATUM_A004580
|
||||
/*
|
||||
* This work-around is implemented in PBI, so just check to see if the
|
||||
* work-around was actually applied. To do this, we check for specific data
|
||||
* at specific addresses in the SerDes register block.
|
||||
*
|
||||
* The work-around says that for each SerDes lane, write BnTTLCRy0 =
|
||||
* 0x1B00_0001, Register 2 = 0x0088_0000, and Register 3 = 0x4000_0000.
|
||||
|
||||
*/
|
||||
static void check_erratum_a4580(uint32_t svr)
|
||||
{
|
||||
const serdes_corenet_t __iomem *srds_regs =
|
||||
(void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
|
||||
unsigned int lane;
|
||||
|
||||
for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
|
||||
if (serdes_lane_enabled(lane)) {
|
||||
const struct serdes_lane __iomem *srds_lane =
|
||||
&srds_regs->lane[serdes_get_lane_idx(lane)];
|
||||
|
||||
/*
|
||||
* Verify that the values we were supposed to write in
|
||||
* the PBI are actually there. Also, the lower 15
|
||||
* bits of res4[3] should be the same as the upper 15
|
||||
* bits of res4[1].
|
||||
*/
|
||||
if ((in_be32(&srds_lane->ttlcr0) != 0x1b000001) ||
|
||||
(in_be32(&srds_lane->res4[1]) != 0x880000) ||
|
||||
(in_be32(&srds_lane->res4[3]) != 0x40000044)) {
|
||||
printf("Work-around for Erratum A004580 is "
|
||||
"not enabled\n");
|
||||
return;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Everything matches, so the erratum work-around was applied */
|
||||
|
||||
printf("Work-around for Erratum A004580 enabled\n");
|
||||
}
|
||||
#endif
|
||||
|
||||
static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
|
||||
{
|
||||
|
@ -136,6 +239,17 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
|
|||
#endif
|
||||
#ifdef CONFIG_SYS_FSL_ERRATUM_A_004934
|
||||
puts("Work-around for Erratum A004934 enabled\n");
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_FSL_ERRATUM_A004849
|
||||
/* This work-around is implemented in PBI, so just check for it */
|
||||
check_erratum_a4849(svr);
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_FSL_ERRATUM_A004580
|
||||
/* This work-around is implemented in PBI, so just check for it */
|
||||
check_erratum_a4580(svr);
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_P4080_ERRATUM_PCIE_A003
|
||||
puts("Work-around for Erratum PCIe-A003 enabled\n");
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
|
|
@ -332,7 +332,8 @@ void mpc85xx_reginfo(void)
|
|||
|
||||
/* Common ddr init for non-corenet fsl 85xx platforms */
|
||||
#ifndef CONFIG_FSL_CORENET
|
||||
#if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SYS_INIT_L2_ADDR)
|
||||
#if (defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)) && \
|
||||
!defined(CONFIG_SYS_INIT_L2_ADDR)
|
||||
phys_size_t initdram(int board_type)
|
||||
{
|
||||
#if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD)
|
||||
|
@ -450,21 +451,21 @@ static void dump_spd_ddr_reg(void)
|
|||
for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
|
||||
switch (i) {
|
||||
case 0:
|
||||
ddr[i] = (void *)CONFIG_SYS_MPC85xx_DDR_ADDR;
|
||||
ddr[i] = (void *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
|
||||
break;
|
||||
#if defined(CONFIG_SYS_MPC85xx_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
|
||||
#if defined(CONFIG_SYS_MPC8xxx_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
|
||||
case 1:
|
||||
ddr[i] = (void *)CONFIG_SYS_MPC85xx_DDR2_ADDR;
|
||||
ddr[i] = (void *)CONFIG_SYS_MPC8xxx_DDR2_ADDR;
|
||||
break;
|
||||
#endif
|
||||
#if defined(CONFIG_SYS_MPC85xx_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
|
||||
#if defined(CONFIG_SYS_MPC8xxx_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
|
||||
case 2:
|
||||
ddr[i] = (void *)CONFIG_SYS_MPC85xx_DDR3_ADDR;
|
||||
ddr[i] = (void *)CONFIG_SYS_MPC8xxx_DDR3_ADDR;
|
||||
break;
|
||||
#endif
|
||||
#if defined(CONFIG_SYS_MPC85xx_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
|
||||
#if defined(CONFIG_SYS_MPC8xxx_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
|
||||
case 3:
|
||||
ddr[i] = (void *)CONFIG_SYS_MPC85xx_DDR4_ADDR;
|
||||
ddr[i] = (void *)CONFIG_SYS_MPC8xxx_DDR4_ADDR;
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
|
|
|
@ -350,6 +350,10 @@ int cpu_init_r(void)
|
|||
#elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2)
|
||||
struct ccsr_cluster_l2 * l2cache = (void __iomem *)CONFIG_SYS_FSL_CLUSTER_1_L2;
|
||||
#endif
|
||||
#if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP)
|
||||
extern int spin_table_compat;
|
||||
const char *spin;
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
|
||||
defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011)
|
||||
|
@ -395,6 +399,14 @@ int cpu_init_r(void)
|
|||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP)
|
||||
spin = getenv("spin_table_compat");
|
||||
if (spin && (*spin == 'n'))
|
||||
spin_table_compat = 0;
|
||||
else
|
||||
spin_table_compat = 1;
|
||||
#endif
|
||||
|
||||
puts ("L2: ");
|
||||
|
||||
#if defined(CONFIG_L2_CACHE)
|
||||
|
@ -470,7 +482,7 @@ int cpu_init_r(void)
|
|||
&& l2srbar >= CONFIG_SYS_FLASH_BASE) {
|
||||
l2srbar = CONFIG_SYS_INIT_L2_ADDR;
|
||||
l2cache->l2srbar0 = l2srbar;
|
||||
printf("moving to 0x%08x", CONFIG_SYS_INIT_L2_ADDR);
|
||||
printf(", moving to 0x%08x", CONFIG_SYS_INIT_L2_ADDR);
|
||||
}
|
||||
#endif /* CONFIG_SYS_INIT_L2_ADDR */
|
||||
puts("\n");
|
||||
|
|
|
@ -18,7 +18,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
|
|||
unsigned int ctrl_num)
|
||||
{
|
||||
unsigned int i;
|
||||
volatile ccsr_ddr_t *ddr = (void *)CONFIG_SYS_MPC85xx_DDR_ADDR;
|
||||
volatile ccsr_ddr_t *ddr = (void *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
|
||||
|
||||
if (ctrl_num != 0) {
|
||||
printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
|
||||
|
@ -73,7 +73,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
|
|||
void
|
||||
ddr_enable_ecc(unsigned int dram_size)
|
||||
{
|
||||
volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
|
||||
volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC8xxx_DDR_ADDR);
|
||||
|
||||
dma_meminit(CONFIG_MEM_INIT_VALUE, dram_size);
|
||||
|
||||
|
|
|
@ -19,14 +19,11 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
|
|||
unsigned int ctrl_num)
|
||||
{
|
||||
unsigned int i;
|
||||
#ifdef CONFIG_MPC83xx
|
||||
ccsr_ddr_t *ddr = (void *)CONFIG_SYS_MPC83xx_DDR_ADDR;
|
||||
#else
|
||||
ccsr_ddr_t *ddr = (void *)CONFIG_SYS_MPC85xx_DDR_ADDR;
|
||||
#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
|
||||
ccsr_ddr_t *ddr = (void *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
|
||||
|
||||
#if defined(CONFIG_SYS_FSL_ERRATUM_NMG_DDR120) && defined(CONFIG_MPC85xx)
|
||||
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
|
||||
uint svr;
|
||||
#endif
|
||||
#endif
|
||||
|
||||
if (ctrl_num) {
|
||||
|
|
|
@ -32,21 +32,21 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
|
|||
|
||||
switch (ctrl_num) {
|
||||
case 0:
|
||||
ddr = (void *)CONFIG_SYS_MPC85xx_DDR_ADDR;
|
||||
ddr = (void *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
|
||||
break;
|
||||
#if defined(CONFIG_SYS_MPC85xx_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
|
||||
#if defined(CONFIG_SYS_MPC8xxx_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
|
||||
case 1:
|
||||
ddr = (void *)CONFIG_SYS_MPC85xx_DDR2_ADDR;
|
||||
ddr = (void *)CONFIG_SYS_MPC8xxx_DDR2_ADDR;
|
||||
break;
|
||||
#endif
|
||||
#if defined(CONFIG_SYS_MPC85xx_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
|
||||
#if defined(CONFIG_SYS_MPC8xxx_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
|
||||
case 2:
|
||||
ddr = (void *)CONFIG_SYS_MPC85xx_DDR3_ADDR;
|
||||
ddr = (void *)CONFIG_SYS_MPC8xxx_DDR3_ADDR;
|
||||
break;
|
||||
#endif
|
||||
#if defined(CONFIG_SYS_MPC85xx_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
|
||||
#if defined(CONFIG_SYS_MPC8xxx_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
|
||||
case 3:
|
||||
ddr = (void *)CONFIG_SYS_MPC85xx_DDR4_ADDR;
|
||||
ddr = (void *)CONFIG_SYS_MPC8xxx_DDR4_ADDR;
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
|
|
|
@ -714,9 +714,13 @@ void fsl_serdes_init(void)
|
|||
|
||||
#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9
|
||||
/*
|
||||
* Set BnTTLCRy0[FLT_SEL] = 000011 and set BnTTLCRy0[17] = 1 for
|
||||
* each of the SerDes lanes selected as SGMII, XAUI, SRIO, or
|
||||
* AURORA before the device is initialized.
|
||||
* Set BnTTLCRy0[FLT_SEL] = 011011 and set BnTTLCRy0[31] = 1
|
||||
* for each of the SerDes lanes selected as SGMII, XAUI, SRIO,
|
||||
* or AURORA before the device is initialized.
|
||||
*
|
||||
* Note that this part of the SERDES-9 work-around is
|
||||
* redundant if the work-around for A-4580 has already been
|
||||
* applied via PBI.
|
||||
*/
|
||||
switch (lane_prtcl) {
|
||||
case SGMII_FM1_DTSEC1:
|
||||
|
@ -733,10 +737,12 @@ void fsl_serdes_init(void)
|
|||
case SRIO1:
|
||||
case SRIO2:
|
||||
case AURORA:
|
||||
clrsetbits_be32(&srds_regs->lane[idx].ttlcr0,
|
||||
SRDS_TTLCR0_FLT_SEL_MASK,
|
||||
SRDS_TTLCR0_FLT_SEL_750PPM |
|
||||
SRDS_TTLCR0_PM_DIS);
|
||||
out_be32(&srds_regs->lane[idx].ttlcr0,
|
||||
SRDS_TTLCR0_FLT_SEL_KFR_26 |
|
||||
SRDS_TTLCR0_FLT_SEL_KPH_28 |
|
||||
SRDS_TTLCR0_FLT_SEL_750PPM |
|
||||
SRDS_TTLCR0_FREQOVD_EN);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
|
|
@ -46,10 +46,8 @@ u32 get_my_id()
|
|||
*/
|
||||
int hold_cores_in_reset(int verbose)
|
||||
{
|
||||
const char *s = getenv("mp_holdoff");
|
||||
|
||||
/* Default to no, overriden by 'y', 'yes', 'Y', 'Yes', or '1' */
|
||||
if (s && (*s == 'y' || *s == 'Y' || *s == '1')) {
|
||||
if (getenv_yesno("mp_holdoff") == 1) {
|
||||
if (verbose) {
|
||||
puts("Secondary cores are being held in reset.\n");
|
||||
puts("See 'mp_holdoff' environment variable\n");
|
||||
|
|
|
@ -351,7 +351,13 @@ __secondary_reset_vector:
|
|||
.align L1_CACHE_SHIFT
|
||||
.global __second_half_boot_page
|
||||
__second_half_boot_page:
|
||||
#define EPAPR_MAGIC 0x45504150
|
||||
#ifdef CONFIG_PPC_SPINTABLE_COMPATIBLE
|
||||
lis r3,(spin_table_compat - __second_half_boot_page)@h
|
||||
ori r3,r3,(spin_table_compat - __second_half_boot_page)@l
|
||||
add r3,r3,r11 /* r11 has the address of __second_half_boot_page */
|
||||
lwz r14,0(r3)
|
||||
#endif
|
||||
|
||||
#define ENTRY_ADDR_UPPER 0
|
||||
#define ENTRY_ADDR_LOWER 4
|
||||
#define ENTRY_R3_UPPER 8
|
||||
|
@ -383,7 +389,24 @@ __second_half_boot_page:
|
|||
stw r8,ENTRY_ADDR_LOWER(r10)
|
||||
|
||||
/* spin waiting for addr */
|
||||
3: lwz r4,ENTRY_ADDR_LOWER(r10)
|
||||
3:
|
||||
/*
|
||||
* To comply with ePAPR 1.1, the spin table has been moved to cache-enabled
|
||||
* memory. Old OS may not work with this change. A patch is waiting to be
|
||||
* accepted for Linux kernel. Other OS needs similar fix to spin table.
|
||||
* For OSes with old spin table code, we can enable this temporary fix by
|
||||
* setting environmental variable "spin_table_compat". For new OSes, set
|
||||
* "spin_table_compat=no". After Linux is fixed, we can remove this macro
|
||||
* and related code. For now, it is enabled by default.
|
||||
*/
|
||||
#ifdef CONFIG_PPC_SPINTABLE_COMPATIBLE
|
||||
cmpwi r14,0
|
||||
beq 4f
|
||||
dcbf 0, r10
|
||||
sync
|
||||
4:
|
||||
#endif
|
||||
lwz r4,ENTRY_ADDR_LOWER(r10)
|
||||
andi. r11,r4,1
|
||||
bne 3b
|
||||
isync
|
||||
|
@ -460,5 +483,14 @@ __second_half_boot_page:
|
|||
.globl __spin_table
|
||||
__spin_table:
|
||||
.space CONFIG_MAX_CPUS*ENTRY_SIZE
|
||||
|
||||
#ifdef CONFIG_PPC_SPINTABLE_COMPATIBLE
|
||||
.align L1_CACHE_SHIFT
|
||||
.global spin_table_compat
|
||||
spin_table_compat:
|
||||
.long 1
|
||||
|
||||
#endif
|
||||
|
||||
__spin_table_end:
|
||||
.space 4096 - (__spin_table_end - __spin_table)
|
||||
|
|
|
@ -21,12 +21,16 @@
|
|||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/global_data.h>
|
||||
#include <asm/fsl_ifc.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
void cpu_init_f(void)
|
||||
{
|
||||
#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
|
||||
#ifdef CONFIG_SYS_INIT_L2_ADDR
|
||||
ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
|
||||
|
||||
out_be32(&l2cache->l2srbar0, CONFIG_SYS_INIT_L2_ADDR);
|
||||
|
@ -40,3 +44,16 @@ void cpu_init_f(void)
|
|||
(MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2SRAM_ENTIRE));
|
||||
#endif
|
||||
}
|
||||
|
||||
#ifndef CONFIG_SYS_FSL_TBCLK_DIV
|
||||
#define CONFIG_SYS_FSL_TBCLK_DIV 8
|
||||
#endif
|
||||
|
||||
void udelay(unsigned long usec)
|
||||
{
|
||||
u32 ticks_per_usec = gd->bus_clk / (CONFIG_SYS_FSL_TBCLK_DIV * 1000000);
|
||||
u32 ticks = ticks_per_usec * usec;
|
||||
u32 s = mfspr(SPRN_TBRL);
|
||||
|
||||
while ((mfspr(SPRN_TBRL) - s) < ticks);
|
||||
}
|
|
@ -44,6 +44,15 @@
|
|||
#undef MSR_KERNEL
|
||||
#define MSR_KERNEL ( MSR_ME ) /* Machine Check */
|
||||
|
||||
#if defined(CONFIG_NAND_SPL) || \
|
||||
(defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL))
|
||||
#define MINIMAL_SPL
|
||||
#endif
|
||||
|
||||
#if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SECURE_BOOT)
|
||||
#define NOR_BOOT
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Set up GOT: Global Offset Table
|
||||
*
|
||||
|
@ -53,7 +62,7 @@
|
|||
GOT_ENTRY(_GOT2_TABLE_)
|
||||
GOT_ENTRY(_FIXUP_TABLE_)
|
||||
|
||||
#ifndef CONFIG_NAND_SPL
|
||||
#ifndef MINIMAL_SPL
|
||||
GOT_ENTRY(_start)
|
||||
GOT_ENTRY(_start_of_vectors)
|
||||
GOT_ENTRY(_end_of_vectors)
|
||||
|
@ -282,51 +291,8 @@ l2_disabled:
|
|||
isync
|
||||
.endm
|
||||
|
||||
#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(CONFIG_NAND_SPL)
|
||||
/*
|
||||
* TLB entry for debuggging in AS1
|
||||
* Create temporary TLB entry in AS0 to handle debug exception
|
||||
* As on debug exception MSR is cleared i.e. Address space is changed
|
||||
* to 0. A TLB entry (in AS0) is required to handle debug exception generated
|
||||
* in AS1.
|
||||
*/
|
||||
|
||||
#if !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SECURE_BOOT)
|
||||
/*
|
||||
* TLB entry is created for IVPR + IVOR15 to map on valid OP code address
|
||||
* bacause flash's virtual address maps to 0xff800000 - 0xffffffff.
|
||||
* and this window is outside of 4K boot window.
|
||||
*/
|
||||
create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \
|
||||
0, BOOKE_PAGESZ_4M, \
|
||||
CONFIG_SYS_MONITOR_BASE & 0xffc00000, MAS2_I|MAS2_G, \
|
||||
0xffc00000, MAS3_SX|MAS3_SW|MAS3_SR, \
|
||||
0, r6
|
||||
|
||||
#elif !defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT)
|
||||
create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \
|
||||
0, BOOKE_PAGESZ_1M, \
|
||||
CONFIG_SYS_MONITOR_BASE, MAS2_I|MAS2_G, \
|
||||
CONFIG_SYS_PBI_FLASH_WINDOW, MAS3_SX|MAS3_SW|MAS3_SR, \
|
||||
0, r6
|
||||
#else
|
||||
/*
|
||||
* TLB entry is created for IVPR + IVOR15 to map on valid OP code address
|
||||
* because "nexti" will resize TLB to 4K
|
||||
*/
|
||||
create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \
|
||||
0, BOOKE_PAGESZ_256K, \
|
||||
CONFIG_SYS_MONITOR_BASE, MAS2_I, \
|
||||
CONFIG_SYS_MONITOR_BASE, MAS3_SX|MAS3_SW|MAS3_SR, \
|
||||
0, r6
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Ne need to setup interrupt vector for NAND SPL
|
||||
* because NAND SPL never compiles it.
|
||||
*/
|
||||
#if !defined(CONFIG_NAND_SPL)
|
||||
/* Interrupt vectors do not fit in minimal SPL. */
|
||||
#if !defined(MINIMAL_SPL)
|
||||
/* Setup interrupt vectors */
|
||||
lis r1,CONFIG_SYS_MONITOR_BASE@h
|
||||
mtspr IVPR,r1
|
||||
|
@ -534,10 +500,6 @@ nexti: mflr r1 /* R1 = our PC */
|
|||
li r3, 0
|
||||
mtspr MAS1, r3
|
||||
1: cmpw r3, r14
|
||||
#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(CONFIG_NAND_SPL)
|
||||
cmpwi cr1, r3, CONFIG_SYS_PPC_E500_DEBUG_TLB
|
||||
cror cr0*4+eq, cr0*4+eq, cr1*4+eq
|
||||
#endif
|
||||
rlwinm r5, r3, 16, MAS0_ESEL_MSK
|
||||
addi r3, r3, 1
|
||||
beq 2f /* skip the entry we're executing from */
|
||||
|
@ -553,6 +515,46 @@ nexti: mflr r1 /* R1 = our PC */
|
|||
2: cmpw r3, r4
|
||||
blt 1b
|
||||
|
||||
#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(MINIMAL_SPL)
|
||||
/*
|
||||
* TLB entry for debuggging in AS1
|
||||
* Create temporary TLB entry in AS0 to handle debug exception
|
||||
* As on debug exception MSR is cleared i.e. Address space is changed
|
||||
* to 0. A TLB entry (in AS0) is required to handle debug exception generated
|
||||
* in AS1.
|
||||
*/
|
||||
|
||||
#ifdef NOR_BOOT
|
||||
/*
|
||||
* TLB entry is created for IVPR + IVOR15 to map on valid OP code address
|
||||
* bacause flash's virtual address maps to 0xff800000 - 0xffffffff.
|
||||
* and this window is outside of 4K boot window.
|
||||
*/
|
||||
create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \
|
||||
0, BOOKE_PAGESZ_4M, \
|
||||
CONFIG_SYS_MONITOR_BASE & 0xffc00000, MAS2_I|MAS2_G, \
|
||||
0xffc00000, MAS3_SX|MAS3_SW|MAS3_SR, \
|
||||
0, r6
|
||||
|
||||
#elif !defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT)
|
||||
create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \
|
||||
0, BOOKE_PAGESZ_1M, \
|
||||
CONFIG_SYS_MONITOR_BASE, MAS2_I|MAS2_G, \
|
||||
CONFIG_SYS_PBI_FLASH_WINDOW, MAS3_SX|MAS3_SW|MAS3_SR, \
|
||||
0, r6
|
||||
#else
|
||||
/*
|
||||
* TLB entry is created for IVPR + IVOR15 to map on valid OP code address
|
||||
* because "nexti" will resize TLB to 4K
|
||||
*/
|
||||
create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \
|
||||
0, BOOKE_PAGESZ_256K, \
|
||||
CONFIG_SYS_MONITOR_BASE & 0xfffc0000, MAS2_I, \
|
||||
CONFIG_SYS_MONITOR_BASE & 0xfffc0000, MAS3_SX|MAS3_SW|MAS3_SR, \
|
||||
0, r6
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Relocate CCSR, if necessary. We relocate CCSR if (obviously) the default
|
||||
* location is not where we want it. This typically happens on a 36-bit
|
||||
|
@ -1036,7 +1038,7 @@ create_init_ram_area:
|
|||
lis r6,FSL_BOOKE_MAS0(1, 15, 0)@h
|
||||
ori r6,r6,FSL_BOOKE_MAS0(1, 15, 0)@l
|
||||
|
||||
#if !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SECURE_BOOT)
|
||||
#ifdef NOR_BOOT
|
||||
/* create a temp mapping in AS=1 to the 4M boot window */
|
||||
create_tlb1_entry 15, \
|
||||
1, BOOKE_PAGESZ_4M, \
|
||||
|
@ -1050,8 +1052,8 @@ create_init_ram_area:
|
|||
*/
|
||||
create_tlb1_entry 15, \
|
||||
1, BOOKE_PAGESZ_1M, \
|
||||
CONFIG_SYS_MONITOR_BASE, MAS2_I|MAS2_G, \
|
||||
CONFIG_SYS_PBI_FLASH_WINDOW, MAS3_SX|MAS3_SW|MAS3_SR, \
|
||||
CONFIG_SYS_MONITOR_BASE & 0xfff00000, MAS2_I|MAS2_G, \
|
||||
CONFIG_SYS_PBI_FLASH_WINDOW & 0xfff00000, MAS3_SX|MAS3_SW|MAS3_SR, \
|
||||
0, r6
|
||||
#else
|
||||
/*
|
||||
|
@ -1060,8 +1062,8 @@ create_init_ram_area:
|
|||
*/
|
||||
create_tlb1_entry 15, \
|
||||
1, BOOKE_PAGESZ_1M, \
|
||||
CONFIG_SYS_MONITOR_BASE, MAS2_I|MAS2_G, \
|
||||
CONFIG_SYS_MONITOR_BASE, MAS3_SX|MAS3_SW|MAS3_SR, \
|
||||
CONFIG_SYS_MONITOR_BASE & 0xfff00000, MAS2_I|MAS2_G, \
|
||||
CONFIG_SYS_MONITOR_BASE & 0xfff00000, MAS3_SX|MAS3_SW|MAS3_SR, \
|
||||
0, r6
|
||||
#endif
|
||||
|
||||
|
@ -1111,7 +1113,8 @@ switch_as:
|
|||
bdnz 1b
|
||||
|
||||
/* Jump out the last 4K page and continue to 'normal' start */
|
||||
#ifdef CONFIG_SYS_RAMBOOT
|
||||
#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)
|
||||
/* We assume that we're already running at the address we're linked at */
|
||||
b _start_cont
|
||||
#else
|
||||
/* Calculate absolute address in FLASH and jump there */
|
||||
|
@ -1157,7 +1160,7 @@ _start_cont:
|
|||
|
||||
/* NOTREACHED - board_init_f() does not return */
|
||||
|
||||
#ifndef CONFIG_NAND_SPL
|
||||
#ifndef MINIMAL_SPL
|
||||
. = EXC_OFF_SYS_RESET
|
||||
.globl _start_of_vectors
|
||||
_start_of_vectors:
|
||||
|
@ -1601,7 +1604,7 @@ in32:
|
|||
in32r:
|
||||
lwbrx r3,r0,r3
|
||||
blr
|
||||
#endif /* !CONFIG_NAND_SPL */
|
||||
#endif /* !MINIMAL_SPL */
|
||||
|
||||
/*------------------------------------------------------------------------------*/
|
||||
|
||||
|
@ -1798,7 +1801,7 @@ clear_bss:
|
|||
mr r4,r10 /* Destination Address */
|
||||
bl board_init_r
|
||||
|
||||
#ifndef CONFIG_NAND_SPL
|
||||
#ifndef MINIMAL_SPL
|
||||
/*
|
||||
* Copy exception vector code to low memory
|
||||
*
|
||||
|
@ -1971,4 +1974,4 @@ setup_ivors:
|
|||
|
||||
#include "fixed_ivor.S"
|
||||
blr
|
||||
#endif /* !CONFIG_NAND_SPL */
|
||||
#endif /* !MINIMAL_SPL */
|
||||
|
|
|
@ -55,7 +55,7 @@ void init_tlbs(void)
|
|||
return ;
|
||||
}
|
||||
|
||||
#ifndef CONFIG_NAND_SPL
|
||||
#if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SPL_BUILD)
|
||||
void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn,
|
||||
phys_addr_t *rpn)
|
||||
{
|
||||
|
@ -332,4 +332,4 @@ void clear_ddr_tlbs(unsigned int memsize_in_meg)
|
|||
}
|
||||
|
||||
|
||||
#endif /* !CONFIG_NAND_SPL */
|
||||
#endif /* not SPL */
|
||||
|
|
87
arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
Normal file
87
arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
Normal file
|
@ -0,0 +1,87 @@
|
|||
/*
|
||||
* (C) Copyright 2006
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de
|
||||
*
|
||||
* Copyright 2009 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include "config.h" /* CONFIG_BOARDDIR */
|
||||
|
||||
OUTPUT_ARCH(powerpc)
|
||||
SECTIONS
|
||||
{
|
||||
. = CONFIG_SPL_TEXT_BASE;
|
||||
.text : {
|
||||
*(.text*)
|
||||
}
|
||||
_etext = .;
|
||||
|
||||
.reloc : {
|
||||
_GOT2_TABLE_ = .;
|
||||
KEEP(*(.got2))
|
||||
KEEP(*(.got))
|
||||
PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
|
||||
_FIXUP_TABLE_ = .;
|
||||
KEEP(*(.fixup))
|
||||
}
|
||||
__got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
|
||||
__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
|
||||
|
||||
. = ALIGN(8);
|
||||
.data : {
|
||||
*(.rodata*)
|
||||
*(.data*)
|
||||
*(.sdata*)
|
||||
}
|
||||
_edata = .;
|
||||
|
||||
. = ALIGN(8);
|
||||
__init_begin = .;
|
||||
__init_end = .;
|
||||
/* FIXME for non-NAND SPL */
|
||||
#if defined(CONFIG_FSL_IFC) /* Restrict bootpg at 4K boundry for IFC */
|
||||
.bootpg ADDR(.text) + 0x1000 :
|
||||
{
|
||||
start.o (.bootpg)
|
||||
}
|
||||
#define RESET_VECTOR_OFFSET 0x1ffc /* IFC has 8K sram */
|
||||
#elif defined(CONFIG_FSL_ELBC)
|
||||
#define RESET_VECTOR_OFFSET 0xffc /* LBC has 4k sram */
|
||||
#else
|
||||
#error unknown NAND controller
|
||||
#endif
|
||||
.resetvec ADDR(.text) + RESET_VECTOR_OFFSET : {
|
||||
KEEP(*(.resetvec))
|
||||
} = 0xffff
|
||||
|
||||
/*
|
||||
* Make sure that the bss segment isn't linked at 0x0, otherwise its
|
||||
* address won't be updated during relocation fixups.
|
||||
*/
|
||||
. |= 0x10;
|
||||
|
||||
__bss_start = .;
|
||||
.bss : {
|
||||
*(.sbss*)
|
||||
*(.bss*)
|
||||
}
|
||||
__bss_end__ = .;
|
||||
}
|
|
@ -22,10 +22,10 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
|
|||
|
||||
switch (ctrl_num) {
|
||||
case 0:
|
||||
ddr = (void *)CONFIG_SYS_MPC86xx_DDR_ADDR;
|
||||
ddr = (void *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
|
||||
break;
|
||||
case 1:
|
||||
ddr = (void *)CONFIG_SYS_MPC86xx_DDR2_ADDR;
|
||||
ddr = (void *)CONFIG_SYS_MPC8xxx_DDR2_ADDR;
|
||||
break;
|
||||
default:
|
||||
printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
|
||||
|
|
|
@ -10,6 +10,20 @@ include $(TOPDIR)/config.mk
|
|||
|
||||
LIB = $(obj)lib8xxx.o
|
||||
|
||||
MINIMAL=
|
||||
|
||||
ifdef CONFIG_SPL_BUILD
|
||||
ifdef CONFIG_SPL_INIT_MINIMAL
|
||||
MINIMAL=y
|
||||
endif
|
||||
endif
|
||||
|
||||
ifdef MINIMAL
|
||||
|
||||
COBJS-$(CONFIG_FSL_LAW) += law.o
|
||||
|
||||
else
|
||||
|
||||
ifneq ($(CPU),mpc83xx)
|
||||
COBJS-y += cpu.o
|
||||
endif
|
||||
|
@ -18,6 +32,9 @@ COBJS-$(CONFIG_OF_LIBFDT) += fdt.o
|
|||
COBJS-$(CONFIG_FSL_IFC) += fsl_ifc.o
|
||||
COBJS-$(CONFIG_FSL_LBC) += fsl_lbc.o
|
||||
COBJS-$(CONFIG_SYS_SRIO) += srio.o
|
||||
COBJS-$(CONFIG_FSL_LAW) += law.o
|
||||
|
||||
endif
|
||||
|
||||
SRCS := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
|
||||
|
|
|
@ -18,15 +18,7 @@
|
|||
|
||||
#include "ddr.h"
|
||||
|
||||
#ifdef CONFIG_MPC83xx
|
||||
#define _DDR_ADDR CONFIG_SYS_MPC83xx_DDR_ADDR
|
||||
#elif defined(CONFIG_MPC85xx)
|
||||
#define _DDR_ADDR CONFIG_SYS_MPC85xx_DDR_ADDR
|
||||
#elif defined(CONFIG_MPC86xx)
|
||||
#define _DDR_ADDR CONFIG_SYS_MPC86xx_DDR_ADDR
|
||||
#else
|
||||
#error "Undefined _DDR_ADDR"
|
||||
#endif
|
||||
#define _DDR_ADDR CONFIG_SYS_MPC8xxx_DDR_ADDR
|
||||
|
||||
static u32 fsl_ddr_get_version(void)
|
||||
{
|
||||
|
|
|
@ -133,14 +133,8 @@ u32 fsl_ddr_get_intl3r(void)
|
|||
|
||||
void board_add_ram_info(int use_default)
|
||||
{
|
||||
#if defined(CONFIG_MPC83xx)
|
||||
immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
|
||||
ccsr_ddr_t *ddr = (void *)&immap->ddr;
|
||||
#elif defined(CONFIG_MPC85xx)
|
||||
ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
|
||||
#elif defined(CONFIG_MPC86xx)
|
||||
ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC86xx_DDR_ADDR);
|
||||
#endif
|
||||
ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC8xxx_DDR_ADDR);
|
||||
|
||||
#if defined(CONFIG_E6500) && (CONFIG_NUM_DDR_CONTROLLERS == 3)
|
||||
u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004);
|
||||
#endif
|
||||
|
@ -152,13 +146,13 @@ void board_add_ram_info(int use_default)
|
|||
|
||||
#if CONFIG_NUM_DDR_CONTROLLERS >= 2
|
||||
if (!(sdram_cfg & SDRAM_CFG_MEM_EN)) {
|
||||
ddr = (void __iomem *)CONFIG_SYS_MPC85xx_DDR2_ADDR;
|
||||
ddr = (void __iomem *)CONFIG_SYS_MPC8xxx_DDR2_ADDR;
|
||||
sdram_cfg = in_be32(&ddr->sdram_cfg);
|
||||
}
|
||||
#endif
|
||||
#if CONFIG_NUM_DDR_CONTROLLERS >= 3
|
||||
if (!(sdram_cfg & SDRAM_CFG_MEM_EN)) {
|
||||
ddr = (void __iomem *)CONFIG_SYS_MPC85xx_DDR3_ADDR;
|
||||
ddr = (void __iomem *)CONFIG_SYS_MPC8xxx_DDR3_ADDR;
|
||||
sdram_cfg = in_be32(&ddr->sdram_cfg);
|
||||
}
|
||||
#endif
|
||||
|
|
|
@ -217,7 +217,7 @@ void fdt_fixup_dr_usb(void *blob, bd_t *bd)
|
|||
#if CONFIG_SYS_FSL_SEC_COMPAT == 2 /* SEC 2.x/3.x */
|
||||
void fdt_fixup_crypto_node(void *blob, int sec_rev)
|
||||
{
|
||||
const struct sec_rev_prop {
|
||||
static const struct sec_rev_prop {
|
||||
u32 sec_rev;
|
||||
u32 num_channels;
|
||||
u32 channel_fifo_len;
|
||||
|
@ -232,8 +232,8 @@ void fdt_fixup_crypto_node(void *blob, int sec_rev)
|
|||
{ 0x0301, 4, 24, 0xbfe, 0x03ab0ebf }, /* SEC 3.1 */
|
||||
{ 0x0303, 4, 24, 0x97c, 0x03a30abf }, /* SEC 3.3 */
|
||||
};
|
||||
char compat_strlist[ARRAY_SIZE(sec_rev_prop_list) *
|
||||
sizeof("fsl,secX.Y")];
|
||||
static char compat_strlist[ARRAY_SIZE(sec_rev_prop_list) *
|
||||
sizeof("fsl,secX.Y")];
|
||||
int crypto_node, sec_idx, err;
|
||||
char *p;
|
||||
u32 val;
|
||||
|
|
|
@ -92,7 +92,7 @@ void disable_law(u8 idx)
|
|||
return;
|
||||
}
|
||||
|
||||
#ifndef CONFIG_NAND_SPL
|
||||
#if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SPL_BUILD)
|
||||
static int get_law_entry(u8 i, struct law_entry *e)
|
||||
{
|
||||
u32 lawar;
|
||||
|
@ -122,7 +122,7 @@ int set_next_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id)
|
|||
return idx;
|
||||
}
|
||||
|
||||
#ifndef CONFIG_NAND_SPL
|
||||
#if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SPL_BUILD)
|
||||
int set_last_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id)
|
||||
{
|
||||
u32 idx;
|
||||
|
@ -233,7 +233,7 @@ int set_ddr_laws(u64 start, u64 sz, enum law_trgt_if id)
|
|||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
#endif /* not SPL */
|
||||
|
||||
void init_laws(void)
|
||||
{
|
||||
|
@ -258,9 +258,10 @@ void init_laws(void)
|
|||
gd->used_laws |= (1 << i);
|
||||
}
|
||||
|
||||
#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
|
||||
#if (defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)) || \
|
||||
(defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD))
|
||||
/*
|
||||
* in NAND boot we've already parsed the law_table and setup those LAWs
|
||||
* in SPL boot we've already parsed the law_table and setup those LAWs
|
||||
* so don't do it again.
|
||||
*/
|
||||
return;
|
|
@ -621,7 +621,7 @@ static ed_t * ep_add_ed (struct usb_device *usb_dev, unsigned long pipe)
|
|||
| usb_pipeendpoint (pipe) << 7
|
||||
| (usb_pipeisoc (pipe)? 0x8000: 0)
|
||||
| (usb_pipecontrol (pipe)? 0: (usb_pipeout (pipe)? 0x800: 0x1000))
|
||||
| usb_pipeslow (pipe) << 13
|
||||
| (usb_dev->speed == USB_SPEED_LOW) << 13
|
||||
| usb_maxpacket (usb_dev, pipe) << 16);
|
||||
|
||||
return ed_ret;
|
||||
|
|
|
@ -27,6 +27,12 @@
|
|||
#error "Do not define CONFIG_SYS_CCSRBAR_DEFAULT in the board header file."
|
||||
#endif
|
||||
|
||||
/*
|
||||
* This macro should be removed when we no longer care about backwards
|
||||
* compatibility with older operating systems.
|
||||
*/
|
||||
#define CONFIG_PPC_SPINTABLE_COMPATIBLE
|
||||
|
||||
#define FSL_DDR_VER_4_7 47
|
||||
|
||||
/* Number of TLB CAM entries we have on FSL Book-E chips */
|
||||
|
@ -131,7 +137,6 @@
|
|||
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
|
||||
#define CONFIG_TSECV2
|
||||
#define CONFIG_SYS_FSL_SEC_COMPAT 4
|
||||
#define CONFIG_FSL_SATA_V2
|
||||
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
|
||||
#define CONFIG_NUM_DDR_CONTROLLERS 1
|
||||
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
|
||||
|
@ -175,7 +180,6 @@
|
|||
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
|
||||
#define CONFIG_TSECV2
|
||||
#define CONFIG_SYS_FSL_SEC_COMPAT 2
|
||||
#define CONFIG_FSL_SATA_V2
|
||||
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
|
||||
#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
|
||||
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
|
||||
|
@ -188,7 +192,6 @@
|
|||
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
|
||||
#define CONFIG_TSECV2
|
||||
#define CONFIG_SYS_FSL_SEC_COMPAT 4
|
||||
#define CONFIG_FSL_SATA_V2
|
||||
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
|
||||
#define CONFIG_NUM_DDR_CONTROLLERS 1
|
||||
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
|
||||
|
@ -242,7 +245,6 @@
|
|||
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
|
||||
#define CONFIG_TSECV2
|
||||
#define CONFIG_SYS_FSL_SEC_COMPAT 2
|
||||
#define CONFIG_FSL_SATA_V2
|
||||
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
|
||||
#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
|
||||
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
|
||||
|
@ -318,7 +320,6 @@
|
|||
#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
|
||||
#define CONFIG_SYS_FSL_NUM_LAWS 32
|
||||
#define CONFIG_SYS_FSL_SEC_COMPAT 4
|
||||
#define CONFIG_FSL_SATA_V2
|
||||
#define CONFIG_SYS_NUM_FMAN 1
|
||||
#define CONFIG_SYS_NUM_FM1_DTSEC 5
|
||||
#define CONFIG_SYS_NUM_FM1_10GEC 1
|
||||
|
@ -343,6 +344,7 @@
|
|||
#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11
|
||||
#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
|
||||
#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A004849
|
||||
|
||||
#elif defined(CONFIG_PPC_P3041)
|
||||
#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
|
||||
|
@ -350,7 +352,6 @@
|
|||
#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
|
||||
#define CONFIG_SYS_FSL_NUM_LAWS 32
|
||||
#define CONFIG_SYS_FSL_SEC_COMPAT 4
|
||||
#define CONFIG_FSL_SATA_V2
|
||||
#define CONFIG_SYS_NUM_FMAN 1
|
||||
#define CONFIG_SYS_NUM_FM1_DTSEC 5
|
||||
#define CONFIG_SYS_NUM_FM1_10GEC 1
|
||||
|
@ -375,6 +376,7 @@
|
|||
#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11
|
||||
#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
|
||||
#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A004849
|
||||
|
||||
#elif defined(CONFIG_PPC_P4080) /* also supports P4040 */
|
||||
#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
|
||||
|
@ -417,6 +419,9 @@
|
|||
#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x20
|
||||
#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000
|
||||
#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A004849
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A004580
|
||||
#define CONFIG_SYS_P4080_ERRATUM_PCIE_A003
|
||||
|
||||
#elif defined(CONFIG_PPC_P5020) /* also supports P5010 */
|
||||
#define CONFIG_SYS_PPC64 /* 64-bit core */
|
||||
|
@ -425,7 +430,6 @@
|
|||
#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
|
||||
#define CONFIG_SYS_FSL_NUM_LAWS 32
|
||||
#define CONFIG_SYS_FSL_SEC_COMPAT 4
|
||||
#define CONFIG_FSL_SATA_V2
|
||||
#define CONFIG_SYS_NUM_FMAN 1
|
||||
#define CONFIG_SYS_NUM_FM1_DTSEC 5
|
||||
#define CONFIG_SYS_NUM_FM1_10GEC 1
|
||||
|
@ -449,6 +453,7 @@
|
|||
#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
|
||||
|
||||
#elif defined(CONFIG_PPC_P5040)
|
||||
#define CONFIG_SYS_PPC64
|
||||
#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
|
||||
#define CONFIG_MAX_CPUS 4
|
||||
#define CONFIG_SYS_FSL_NUM_CC_PLLS 3
|
||||
|
@ -472,7 +477,6 @@
|
|||
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
|
||||
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A004699
|
||||
#define CONFIG_SYS_FSL_ELBC_MULTIBIT_ECC
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A004510
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
|
||||
#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
|
||||
|
|
|
@ -1035,9 +1035,9 @@ typedef struct immap {
|
|||
} immap_t;
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_MPC83xx_DDR_OFFSET (0x2000)
|
||||
#define CONFIG_SYS_MPC83xx_DDR_ADDR \
|
||||
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_DDR_OFFSET)
|
||||
#define CONFIG_SYS_MPC8xxx_DDR_OFFSET (0x2000)
|
||||
#define CONFIG_SYS_MPC8xxx_DDR_ADDR \
|
||||
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR_OFFSET)
|
||||
#define CONFIG_SYS_MPC83xx_DMA_OFFSET (0x8000)
|
||||
#define CONFIG_SYS_MPC83xx_DMA_ADDR \
|
||||
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_DMA_OFFSET)
|
||||
|
|
|
@ -2619,7 +2619,7 @@ typedef struct serdes_corenet {
|
|||
#define SRDS_PCCR2_RST_XGMII1 0x00800000
|
||||
#define SRDS_PCCR2_RST_XGMII2 0x00400000
|
||||
u32 res5[197];
|
||||
struct {
|
||||
struct serdes_lane {
|
||||
u32 gcr0; /* General Control Register 0 */
|
||||
#define SRDS_GCR0_RRST 0x00400000
|
||||
#define SRDS_GCR0_1STLANE 0x00010000
|
||||
|
@ -2637,8 +2637,11 @@ typedef struct serdes_corenet {
|
|||
u32 res3;
|
||||
u32 ttlcr0; /* Transition Tracking Loop Ctrl 0 */
|
||||
#define SRDS_TTLCR0_FLT_SEL_MASK 0x3f000000
|
||||
#define SRDS_TTLCR0_FLT_SEL_KFR_26 0x10000000
|
||||
#define SRDS_TTLCR0_FLT_SEL_KPH_28 0x08000000
|
||||
#define SRDS_TTLCR0_FLT_SEL_750PPM 0x03000000
|
||||
#define SRDS_TTLCR0_PM_DIS 0x00004000
|
||||
#define SRDS_TTLCR0_FREQOVD_EN 0x00000001
|
||||
u32 res4[7];
|
||||
} lane[24];
|
||||
u32 res6[384];
|
||||
|
@ -2867,9 +2870,9 @@ struct ccsr_pman {
|
|||
#define CONFIG_SYS_FSL_CORENET_PMAN2_OFFSET 0x5000
|
||||
#define CONFIG_SYS_FSL_CORENET_PMAN3_OFFSET 0x6000
|
||||
#endif
|
||||
#define CONFIG_SYS_MPC85xx_DDR_OFFSET 0x8000
|
||||
#define CONFIG_SYS_MPC85xx_DDR2_OFFSET 0x9000
|
||||
#define CONFIG_SYS_MPC85xx_DDR3_OFFSET 0xA000
|
||||
#define CONFIG_SYS_MPC8xxx_DDR_OFFSET 0x8000
|
||||
#define CONFIG_SYS_MPC8xxx_DDR2_OFFSET 0x9000
|
||||
#define CONFIG_SYS_MPC8xxx_DDR3_OFFSET 0xA000
|
||||
#define CONFIG_SYS_FSL_CORENET_CLK_OFFSET 0xE1000
|
||||
#define CONFIG_SYS_FSL_CORENET_RCPM_OFFSET 0xE2000
|
||||
#define CONFIG_SYS_FSL_CORENET_SERDES_OFFSET 0xEA000
|
||||
|
@ -2929,9 +2932,9 @@ struct ccsr_pman {
|
|||
#define CONFIG_SYS_FSL_CLUSTER_1_L2_OFFSET 0xC20000
|
||||
#else
|
||||
#define CONFIG_SYS_MPC85xx_ECM_OFFSET 0x0000
|
||||
#define CONFIG_SYS_MPC85xx_DDR_OFFSET 0x2000
|
||||
#define CONFIG_SYS_MPC8xxx_DDR_OFFSET 0x2000
|
||||
#define CONFIG_SYS_MPC85xx_LBC_OFFSET 0x5000
|
||||
#define CONFIG_SYS_MPC85xx_DDR2_OFFSET 0x6000
|
||||
#define CONFIG_SYS_MPC8xxx_DDR2_OFFSET 0x6000
|
||||
#define CONFIG_SYS_MPC85xx_ESPI_OFFSET 0x7000
|
||||
#define CONFIG_SYS_MPC85xx_PCI1_OFFSET 0x8000
|
||||
#define CONFIG_SYS_MPC85xx_PCIX_OFFSET 0x8000
|
||||
|
@ -2998,12 +3001,12 @@ struct ccsr_pman {
|
|||
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_RCPM_OFFSET)
|
||||
#define CONFIG_SYS_MPC85xx_ECM_ADDR \
|
||||
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ECM_OFFSET)
|
||||
#define CONFIG_SYS_MPC85xx_DDR_ADDR \
|
||||
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DDR_OFFSET)
|
||||
#define CONFIG_SYS_MPC85xx_DDR2_ADDR \
|
||||
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DDR2_OFFSET)
|
||||
#define CONFIG_SYS_MPC85xx_DDR3_ADDR \
|
||||
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DDR3_OFFSET)
|
||||
#define CONFIG_SYS_MPC8xxx_DDR_ADDR \
|
||||
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR_OFFSET)
|
||||
#define CONFIG_SYS_MPC8xxx_DDR2_ADDR \
|
||||
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR2_OFFSET)
|
||||
#define CONFIG_SYS_MPC8xxx_DDR3_ADDR \
|
||||
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR3_OFFSET)
|
||||
#define CONFIG_SYS_LBC_ADDR \
|
||||
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_LBC_OFFSET)
|
||||
#define CONFIG_SYS_IFC_ADDR \
|
||||
|
|
|
@ -1252,10 +1252,10 @@ typedef struct immap {
|
|||
|
||||
extern immap_t *immr;
|
||||
|
||||
#define CONFIG_SYS_MPC86xx_DDR_OFFSET 0x2000
|
||||
#define CONFIG_SYS_MPC86xx_DDR_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_DDR_OFFSET)
|
||||
#define CONFIG_SYS_MPC86xx_DDR2_OFFSET 0x6000
|
||||
#define CONFIG_SYS_MPC86xx_DDR2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_DDR2_OFFSET)
|
||||
#define CONFIG_SYS_MPC8xxx_DDR_OFFSET 0x2000
|
||||
#define CONFIG_SYS_MPC8xxx_DDR_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR_OFFSET)
|
||||
#define CONFIG_SYS_MPC8xxx_DDR2_OFFSET 0x6000
|
||||
#define CONFIG_SYS_MPC8xxx_DDR2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR2_OFFSET)
|
||||
#define CONFIG_SYS_MPC86xx_DMA_OFFSET 0x21000
|
||||
#define CONFIG_SYS_MPC86xx_DMA_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_DMA_OFFSET)
|
||||
#define CONFIG_SYS_MPC86xx_PIC_OFFSET 0x40000
|
||||
|
|
|
@ -1342,4 +1342,10 @@ void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val);
|
|||
#endif
|
||||
#endif /* CONFIG_MACH_SPECIFIC */
|
||||
|
||||
#if defined(CONFIG_MPC85xx) || defined(CONFIG_440)
|
||||
#define EPAPR_MAGIC (0x45504150)
|
||||
#else
|
||||
#define EPAPR_MAGIC (0x65504150)
|
||||
#endif
|
||||
|
||||
#endif /* __ASM_PPC_PROCESSOR_H */
|
||||
|
|
|
@ -1,10 +1,6 @@
|
|||
/*
|
||||
* Copyright (c) 2011 The Chromium OS Authors.
|
||||
* (C) Copyright 2008,2009
|
||||
* Graeme Russ, <graeme.russ@gmail.com>
|
||||
*
|
||||
* (C) Copyright 2002
|
||||
* Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
|
||||
* (C) Copyright 2012
|
||||
* Texas Instruments, <www.ti.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
|
@ -16,7 +12,7 @@
|
|||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
|
@ -24,7 +20,12 @@
|
|||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
#ifndef _ASM_SPL_H_
|
||||
#define _ASM_SPL_H_
|
||||
|
||||
void pci_init_board(void)
|
||||
{
|
||||
}
|
||||
#define BOOT_DEVICE_NOR 1
|
||||
|
||||
/* Linker symbols */
|
||||
extern char __bss_start[], __bss_end__[];
|
||||
|
||||
#endif
|
|
@ -14,7 +14,7 @@
|
|||
#define __HAVE_ARCH_MEMCHR
|
||||
|
||||
extern int strcasecmp(const char *, const char *);
|
||||
extern int strncasecmp(const char *, const char *, int);
|
||||
extern int strncasecmp(const char *, const char *, __kernel_size_t);
|
||||
extern char * strcpy(char *,const char *);
|
||||
extern char * strncpy(char *,const char *, __kernel_size_t);
|
||||
extern __kernel_size_t strlen(const char *);
|
||||
|
|
|
@ -38,13 +38,28 @@ endif
|
|||
|
||||
LIB = $(obj)lib$(ARCH).o
|
||||
|
||||
SOBJS-y += ppccache.o
|
||||
MINIMAL=
|
||||
|
||||
ifdef CONFIG_SPL_BUILD
|
||||
ifdef CONFIG_SPL_INIT_MINIMAL
|
||||
MINIMAL=y
|
||||
endif
|
||||
endif
|
||||
|
||||
ifdef MINIMAL
|
||||
COBJS-y += cache.o
|
||||
else
|
||||
|
||||
SOBJS-y += ppcstring.o
|
||||
|
||||
SOBJS-y += ppccache.o
|
||||
SOBJS-y += ticks.o
|
||||
SOBJS-y += reloc.o
|
||||
|
||||
COBJS-$(CONFIG_BAT_RW) += bat_rw.o
|
||||
ifndef CONFIG_SPL_BUILD
|
||||
COBJS-y += board.o
|
||||
endif
|
||||
COBJS-y += bootm.o
|
||||
COBJS-y += cache.o
|
||||
COBJS-y += extable.o
|
||||
|
@ -53,6 +68,11 @@ COBJS-$(CONFIG_CMD_KGDB) += kgdb.o
|
|||
COBJS-${CONFIG_CMD_IDE} += ide.o
|
||||
COBJS-y += time.o
|
||||
|
||||
# Don't include the MPC5xxx special memcpy into the
|
||||
# SPL U-Boot image. memcpy is used in the SPL NOR
|
||||
# flash driver. And we need the real, fast memcpy
|
||||
# here. We have no problems with unaligned access.
|
||||
ifndef CONFIG_SPL_BUILD
|
||||
# Workaround for local bus unaligned access problems
|
||||
# on MPC512x and MPC5200
|
||||
ifdef CONFIG_MPC512X
|
||||
|
@ -63,6 +83,13 @@ ifdef CONFIG_MPC5200
|
|||
$(obj)ppcstring.o: AFLAGS += -Dmemcpy=__memcpy
|
||||
COBJS-y += memcpy_mpc5200.o
|
||||
endif
|
||||
endif
|
||||
|
||||
endif # not minimal
|
||||
|
||||
ifdef CONFIG_SPL_BUILD
|
||||
COBJS-$(CONFIG_SPL_FRAMEWORK) += spl.o
|
||||
endif
|
||||
|
||||
COBJS += $(sort $(COBJS-y))
|
||||
|
||||
|
@ -75,12 +102,6 @@ TARGETS += $(LIB)
|
|||
all: $(TARGETS)
|
||||
|
||||
$(LIB): $(obj).depend $(OBJS)
|
||||
@if ! $(CROSS_COMPILE)readelf -S $(OBJS) | grep -q '\.fixup.*PROGBITS';\
|
||||
then \
|
||||
echo "ERROR: Your compiler doesn't generate .fixup sections!";\
|
||||
echo " Upgrade to a recent toolchain."; \
|
||||
exit 1; \
|
||||
fi;
|
||||
$(call cmd_link_o_target, $(OBJS))
|
||||
|
||||
$(LIBGCC): $(obj).depend $(LGOBJS)
|
||||
|
|
|
@ -739,16 +739,13 @@ void board_init_r(gd_t *id, ulong dest_addr)
|
|||
flash_size = 0;
|
||||
} else if ((flash_size = flash_init()) > 0) {
|
||||
#ifdef CONFIG_SYS_FLASH_CHECKSUM
|
||||
char *s;
|
||||
|
||||
print_size(flash_size, "");
|
||||
/*
|
||||
* Compute and print flash CRC if flashchecksum is set to 'y'
|
||||
*
|
||||
* NOTE: Maybe we should add some WATCHDOG_RESET()? XXX
|
||||
*/
|
||||
s = getenv("flashchecksum");
|
||||
if (s && (*s == 'y')) {
|
||||
if (getenv_yesno("flashchecksum") == 1) {
|
||||
printf(" CRC: %08X",
|
||||
crc32(0,
|
||||
(const unsigned char *)
|
||||
|
@ -841,9 +838,7 @@ void board_init_r(gd_t *id, ulong dest_addr)
|
|||
* "i2cfast" into account
|
||||
*/
|
||||
{
|
||||
char *s = getenv("i2cfast");
|
||||
|
||||
if (s && ((*s == 'y') || (*s == 'Y'))) {
|
||||
if (getenv_yesno("i2cfast") == 1) {
|
||||
bd->bi_iic_fast[0] = 1;
|
||||
bd->bi_iic_fast[1] = 1;
|
||||
}
|
||||
|
|
|
@ -87,12 +87,6 @@ static void boot_jump_linux(bootm_headers_t *images)
|
|||
* r8: 0
|
||||
* r9: 0
|
||||
*/
|
||||
#if defined(CONFIG_MPC85xx) || defined(CONFIG_440)
|
||||
#define EPAPR_MAGIC (0x45504150)
|
||||
#else
|
||||
#define EPAPR_MAGIC (0x65504150)
|
||||
#endif
|
||||
|
||||
debug (" Booting using OF flat tree...\n");
|
||||
WATCHDOG_RESET ();
|
||||
(*kernel) ((bd_t *)of_flat_tree, 0, 0, EPAPR_MAGIC,
|
||||
|
|
42
arch/powerpc/lib/spl.c
Normal file
42
arch/powerpc/lib/spl.c
Normal file
|
@ -0,0 +1,42 @@
|
|||
/*
|
||||
* Copyright 2012 Stefan Roese <sr@denx.de>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
#include <common.h>
|
||||
#include <config.h>
|
||||
#include <spl.h>
|
||||
#include <image.h>
|
||||
#include <linux/compiler.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
/*
|
||||
* This function jumps to an image with argument. Normally an FDT or ATAGS
|
||||
* image.
|
||||
* arg: Pointer to paramter image in RAM
|
||||
*/
|
||||
#ifdef CONFIG_SPL_OS_BOOT
|
||||
void __noreturn jump_to_image_linux(void *arg)
|
||||
{
|
||||
debug("Entering kernel arg pointer: 0x%p\n", arg);
|
||||
typedef void (*image_entry_arg_t)(void *, ulong r4, ulong r5, ulong r6,
|
||||
ulong r7, ulong r8, ulong r9)
|
||||
__attribute__ ((noreturn));
|
||||
image_entry_arg_t image_entry =
|
||||
(image_entry_arg_t)spl_image.entry_point;
|
||||
|
||||
image_entry(arg, 0, 0, EPAPR_MAGIC, CONFIG_SYS_BOOTMAPSZ, 0, 0);
|
||||
}
|
||||
#endif /* CONFIG_SPL_OS_BOOT */
|
|
@ -274,8 +274,8 @@ void enable_hlt(void);
|
|||
|
||||
static inline void trigger_address_error(void)
|
||||
{
|
||||
set_bl_bit();
|
||||
__asm__ __volatile__ (
|
||||
"ldc %0, sr\n\t"
|
||||
"mov.l @%1, %0"
|
||||
:
|
||||
: "r" (0x10000000), "r" (0x80000001)
|
||||
|
|
|
@ -40,7 +40,7 @@
|
|||
*/
|
||||
|
||||
extern int strcasecmp(const char *, const char *);
|
||||
extern int strncasecmp(const char *, const char *, int);
|
||||
extern int strncasecmp(const char *, const char *, __kernel_size_t);
|
||||
extern char *strcpy(char *, const char *);
|
||||
extern char *strncpy(char *, const char *, __kernel_size_t);
|
||||
extern __kernel_size_t strlen(const char *);
|
||||
|
|
|
@ -284,8 +284,7 @@ void board_init_f(ulong bootflag)
|
|||
*
|
||||
* NOTE: Maybe we should add some WATCHDOG_RESET()? XXX
|
||||
*/
|
||||
s = getenv("flashchecksum");
|
||||
if (s && (*s == 'y')) {
|
||||
if (getenv_yesno("flashchecksum") == 1) {
|
||||
printf(" CRC: %08lX",
|
||||
crc32(0, (const unsigned char *)CONFIG_SYS_FLASH_BASE,
|
||||
flash_size)
|
||||
|
|
|
@ -28,12 +28,13 @@ include $(TOPDIR)/config.mk
|
|||
|
||||
LIB = $(obj)lib$(CPU).o
|
||||
|
||||
START = start.o start16.o resetvec.o
|
||||
COBJS = interrupts.o cpu.o
|
||||
START-y = start.o
|
||||
RESET_OBJS-$(CONFIG_X86_NO_RESET_VECTOR) += resetvec.o start16.o
|
||||
COBJS = interrupts.o cpu.o timer.o
|
||||
|
||||
SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
|
||||
START := $(addprefix $(obj),$(START))
|
||||
START := $(addprefix $(obj),$(START-y) $(RESET_OBJS-))
|
||||
|
||||
all: $(obj).depend $(START) $(LIB)
|
||||
|
||||
|
|
|
@ -33,12 +33,13 @@ include $(TOPDIR)/config.mk
|
|||
|
||||
LIB := $(obj)lib$(SOC).o
|
||||
|
||||
SOBJS-$(CONFIG_SYS_COREBOOT) += car.o
|
||||
COBJS-$(CONFIG_SYS_COREBOOT) += coreboot.o
|
||||
COBJS-$(CONFIG_SYS_COREBOOT) += tables.o
|
||||
COBJS-$(CONFIG_SYS_COREBOOT) += ipchecksum.o
|
||||
COBJS-$(CONFIG_SYS_COREBOOT) += sdram.o
|
||||
COBJS-$(CONFIG_SYS_COREBOOT) += sysinfo.o
|
||||
|
||||
SOBJS-$(CONFIG_SYS_COREBOOT) += coreboot_car.o
|
||||
COBJS-$(CONFIG_SYS_COREBOOT) += timestamp.o
|
||||
COBJS-$(CONFIG_PCI) += pci.o
|
||||
|
||||
SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
|
||||
|
|
|
@ -1,7 +1,5 @@
|
|||
#
|
||||
# (C) Copyright 2000-2003
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
|
||||
# Copyright (c) 2012 The Chromium OS Authors.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
|
@ -22,6 +20,4 @@
|
|||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
ifndef CONFIG_SYS_TEXT_BASE
|
||||
CONFIG_SYS_TEXT_BASE = 0xFE000000
|
||||
endif
|
||||
CONFIG_ARCH_DEVICE_TREE := coreboot
|
|
@ -26,13 +26,15 @@
|
|||
#include <asm/u-boot-x86.h>
|
||||
#include <flash.h>
|
||||
#include <netdev.h>
|
||||
#include <asm/msr.h>
|
||||
#include <asm/cache.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch-coreboot/tables.h>
|
||||
#include <asm/arch-coreboot/sysinfo.h>
|
||||
#include <asm/arch/timestamp.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
unsigned long monitor_flash_len = CONFIG_SYS_MONITOR_LEN;
|
||||
|
||||
/*
|
||||
* Miscellaneous platform dependent initializations
|
||||
*/
|
||||
|
@ -41,6 +43,9 @@ int cpu_init_f(void)
|
|||
int ret = get_coreboot_info(&lib_sysinfo);
|
||||
if (ret != 0)
|
||||
printf("Failed to parse coreboot tables.\n");
|
||||
|
||||
timestamp_init();
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
@ -62,8 +67,29 @@ int board_early_init_r(void)
|
|||
|
||||
void show_boot_progress(int val)
|
||||
{
|
||||
}
|
||||
#if MIN_PORT80_KCLOCKS_DELAY
|
||||
static uint32_t prev_stamp;
|
||||
static uint32_t base;
|
||||
|
||||
/*
|
||||
* Scale the time counter reading to avoid using 64 bit arithmetics.
|
||||
* Can't use get_timer() here becuase it could be not yet
|
||||
* initialized or even implemented.
|
||||
*/
|
||||
if (!prev_stamp) {
|
||||
base = rdtsc() / 1000;
|
||||
prev_stamp = 0;
|
||||
} else {
|
||||
uint32_t now;
|
||||
|
||||
do {
|
||||
now = rdtsc() / 1000 - base;
|
||||
} while (now < (prev_stamp + MIN_PORT80_KCLOCKS_DELAY));
|
||||
prev_stamp = now;
|
||||
}
|
||||
#endif
|
||||
outb(val, 0x80);
|
||||
}
|
||||
|
||||
int last_stage_init(void)
|
||||
{
|
||||
|
@ -82,6 +108,33 @@ int board_eth_init(bd_t *bis)
|
|||
return pci_eth_init(bis);
|
||||
}
|
||||
|
||||
void setup_pcat_compatibility()
|
||||
#define MTRR_TYPE_WP 5
|
||||
#define MTRRcap_MSR 0xfe
|
||||
#define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg))
|
||||
#define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1)
|
||||
|
||||
int board_final_cleanup(void)
|
||||
{
|
||||
/* Un-cache the ROM so the kernel has one
|
||||
* more MTRR available.
|
||||
*
|
||||
* Coreboot should have assigned this to the
|
||||
* top available variable MTRR.
|
||||
*/
|
||||
u8 top_mtrr = (native_read_msr(MTRRcap_MSR) & 0xff) - 1;
|
||||
u8 top_type = native_read_msr(MTRRphysBase_MSR(top_mtrr)) & 0xff;
|
||||
|
||||
/* Make sure this MTRR is the correct Write-Protected type */
|
||||
if (top_type == MTRR_TYPE_WP) {
|
||||
disable_caches();
|
||||
wrmsrl(MTRRphysBase_MSR(top_mtrr), 0);
|
||||
wrmsrl(MTRRphysMask_MSR(top_mtrr), 0);
|
||||
enable_caches();
|
||||
}
|
||||
|
||||
/* Issue SMI to Coreboot to lock down ME and registers */
|
||||
printf("Finalizing Coreboot\n");
|
||||
outb(0xcb, 0xb2);
|
||||
|
||||
return 0;
|
||||
}
|
65
arch/x86/cpu/coreboot/pci.c
Normal file
65
arch/x86/cpu/coreboot/pci.c
Normal file
|
@ -0,0 +1,65 @@
|
|||
/*
|
||||
* Copyright (c) 2011 The Chromium OS Authors.
|
||||
* (C) Copyright 2008,2009
|
||||
* Graeme Russ, <graeme.russ@gmail.com>
|
||||
*
|
||||
* (C) Copyright 2002
|
||||
* Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <pci.h>
|
||||
#include <asm/pci.h>
|
||||
|
||||
static struct pci_controller coreboot_hose;
|
||||
|
||||
static void config_pci_bridge(struct pci_controller *hose, pci_dev_t dev,
|
||||
struct pci_config_table *table)
|
||||
{
|
||||
u8 secondary;
|
||||
hose->read_byte(hose, dev, PCI_SECONDARY_BUS, &secondary);
|
||||
hose->last_busno = max(hose->last_busno, secondary);
|
||||
pci_hose_scan_bus(hose, secondary);
|
||||
}
|
||||
|
||||
static struct pci_config_table pci_coreboot_config_table[] = {
|
||||
/* vendor, device, class, bus, dev, func */
|
||||
{ PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_BRIDGE_PCI,
|
||||
PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, &config_pci_bridge },
|
||||
{}
|
||||
};
|
||||
|
||||
void pci_init_board(void)
|
||||
{
|
||||
coreboot_hose.config_table = pci_coreboot_config_table;
|
||||
coreboot_hose.first_busno = 0;
|
||||
coreboot_hose.last_busno = 0;
|
||||
|
||||
pci_set_region(coreboot_hose.regions + 0, 0x0, 0x0, 0xffffffff,
|
||||
PCI_REGION_MEM);
|
||||
coreboot_hose.region_count = 1;
|
||||
|
||||
pci_setup_type1(&coreboot_hose);
|
||||
|
||||
pci_register_hose(&coreboot_hose);
|
||||
|
||||
pci_hose_scan(&coreboot_hose);
|
||||
}
|
|
@ -27,8 +27,9 @@
|
|||
#include <asm/e820.h>
|
||||
#include <asm/u-boot-x86.h>
|
||||
#include <asm/global_data.h>
|
||||
#include <asm/arch-coreboot/sysinfo.h>
|
||||
#include <asm/arch-coreboot/tables.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/arch/sysinfo.h>
|
||||
#include <asm/arch/tables.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
|
@ -51,6 +52,58 @@ unsigned install_e820_map(unsigned max_entries, struct e820entry *entries)
|
|||
return num_entries;
|
||||
}
|
||||
|
||||
/*
|
||||
* This function looks for the highest region of memory lower than 4GB which
|
||||
* has enough space for U-Boot where U-Boot is aligned on a page boundary. It
|
||||
* overrides the default implementation found elsewhere which simply picks the
|
||||
* end of ram, wherever that may be. The location of the stack, the relocation
|
||||
* address, and how far U-Boot is moved by relocation are set in the global
|
||||
* data structure.
|
||||
*/
|
||||
int calculate_relocation_address(void)
|
||||
{
|
||||
const uint64_t uboot_size = (uintptr_t)&__bss_end -
|
||||
(uintptr_t)&__text_start;
|
||||
const uint64_t total_size = uboot_size + CONFIG_SYS_MALLOC_LEN +
|
||||
CONFIG_SYS_STACK_SIZE;
|
||||
uintptr_t dest_addr = 0;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < lib_sysinfo.n_memranges; i++) {
|
||||
struct memrange *memrange = &lib_sysinfo.memrange[i];
|
||||
/* Force U-Boot to relocate to a page aligned address. */
|
||||
uint64_t start = roundup(memrange->base, 1 << 12);
|
||||
uint64_t end = memrange->base + memrange->size;
|
||||
|
||||
/* Ignore non-memory regions. */
|
||||
if (memrange->type != CB_MEM_RAM)
|
||||
continue;
|
||||
|
||||
/* Filter memory over 4GB. */
|
||||
if (end > 0xffffffffULL)
|
||||
end = 0x100000000ULL;
|
||||
/* Skip this region if it's too small. */
|
||||
if (end - start < total_size)
|
||||
continue;
|
||||
|
||||
/* Use this address if it's the largest so far. */
|
||||
if (end - uboot_size > dest_addr)
|
||||
dest_addr = end;
|
||||
}
|
||||
|
||||
/* If no suitable area was found, return an error. */
|
||||
if (!dest_addr)
|
||||
return 1;
|
||||
|
||||
dest_addr -= uboot_size;
|
||||
dest_addr &= ~((1 << 12) - 1);
|
||||
gd->relocaddr = dest_addr;
|
||||
gd->reloc_off = dest_addr - (uintptr_t)&__text_start;
|
||||
gd->start_addr_sp = dest_addr - CONFIG_SYS_MALLOC_LEN;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int dram_init_f(void)
|
||||
{
|
||||
int i;
|
||||
|
@ -71,5 +124,20 @@ int dram_init_f(void)
|
|||
|
||||
int dram_init(void)
|
||||
{
|
||||
int i, j;
|
||||
|
||||
if (CONFIG_NR_DRAM_BANKS) {
|
||||
for (i = 0, j = 0; i < lib_sysinfo.n_memranges; i++) {
|
||||
struct memrange *memrange = &lib_sysinfo.memrange[i];
|
||||
|
||||
if (memrange->type == CB_MEM_RAM) {
|
||||
gd->bd->bi_dram[j].start = memrange->base;
|
||||
gd->bd->bi_dram[j].size = memrange->size;
|
||||
j++;
|
||||
if (j >= CONFIG_NR_DRAM_BANKS)
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
|
|
@ -1,39 +0,0 @@
|
|||
/*
|
||||
* This file is part of the libpayload project.
|
||||
*
|
||||
* Copyright (C) 2008 Advanced Micro Devices, Inc.
|
||||
* Copyright (C) 2009 coresystems GmbH
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. The name of the author may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <asm/arch-coreboot/sysinfo.h>
|
||||
|
||||
/*
|
||||
* This needs to be in the .data section so that it's copied over during
|
||||
* relocation. By default it's put in the .bss section which is simply filled
|
||||
* with zeroes when transitioning from "ROM", which is really RAM, to other
|
||||
* RAM.
|
||||
*/
|
||||
struct sysinfo_t lib_sysinfo __attribute__((section(".data")));
|
|
@ -28,10 +28,19 @@
|
|||
* SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/arch-coreboot/ipchecksum.h>
|
||||
#include <asm/arch-coreboot/sysinfo.h>
|
||||
#include <asm/arch-coreboot/tables.h>
|
||||
|
||||
/*
|
||||
* This needs to be in the .data section so that it's copied over during
|
||||
* relocation. By default it's put in the .bss section which is simply filled
|
||||
* with zeroes when transitioning from "ROM", which is really RAM, to other
|
||||
* RAM.
|
||||
*/
|
||||
struct sysinfo_t lib_sysinfo __attribute__((section(".data")));
|
||||
|
||||
/*
|
||||
* Some of this is x86 specific, and the rest of it is generic. Right now,
|
||||
* since we only support x86, we'll avoid trying to make lots of infrastructure
|
||||
|
@ -72,22 +81,45 @@ static void cb_parse_memory(unsigned char *ptr, struct sysinfo_t *info)
|
|||
static void cb_parse_serial(unsigned char *ptr, struct sysinfo_t *info)
|
||||
{
|
||||
struct cb_serial *ser = (struct cb_serial *)ptr;
|
||||
if (ser->type != CB_SERIAL_TYPE_IO_MAPPED)
|
||||
return;
|
||||
info->ser_ioport = ser->baseaddr;
|
||||
info->serial = ser;
|
||||
}
|
||||
|
||||
static void cb_parse_optiontable(unsigned char *ptr, struct sysinfo_t *info)
|
||||
static void cb_parse_vbnv(unsigned char *ptr, struct sysinfo_t *info)
|
||||
{
|
||||
info->option_table = (struct cb_cmos_option_table *)ptr;
|
||||
struct cb_vbnv *vbnv = (struct cb_vbnv *)ptr;
|
||||
|
||||
info->vbnv_start = vbnv->vbnv_start;
|
||||
info->vbnv_size = vbnv->vbnv_size;
|
||||
}
|
||||
|
||||
static void cb_parse_checksum(unsigned char *ptr, struct sysinfo_t *info)
|
||||
static void cb_parse_gpios(unsigned char *ptr, struct sysinfo_t *info)
|
||||
{
|
||||
struct cb_cmos_checksum *cmos_cksum = (struct cb_cmos_checksum *)ptr;
|
||||
info->cmos_range_start = cmos_cksum->range_start;
|
||||
info->cmos_range_end = cmos_cksum->range_end;
|
||||
info->cmos_checksum_location = cmos_cksum->location;
|
||||
int i;
|
||||
struct cb_gpios *gpios = (struct cb_gpios *)ptr;
|
||||
|
||||
info->num_gpios = (gpios->count < SYSINFO_MAX_GPIOS) ?
|
||||
(gpios->count) : SYSINFO_MAX_GPIOS;
|
||||
|
||||
for (i = 0; i < info->num_gpios; i++)
|
||||
info->gpios[i] = gpios->gpios[i];
|
||||
}
|
||||
|
||||
static void cb_parse_vdat(unsigned char *ptr, struct sysinfo_t *info)
|
||||
{
|
||||
struct cb_vdat *vdat = (struct cb_vdat *) ptr;
|
||||
|
||||
info->vdat_addr = vdat->vdat_addr;
|
||||
info->vdat_size = vdat->vdat_size;
|
||||
}
|
||||
|
||||
static void cb_parse_tstamp(unsigned char *ptr, struct sysinfo_t *info)
|
||||
{
|
||||
info->tstamp_table = ((struct cb_cbmem_tab *)ptr)->cbmem_tab;
|
||||
}
|
||||
|
||||
static void cb_parse_cbmem_cons(unsigned char *ptr, struct sysinfo_t *info)
|
||||
{
|
||||
info->cbmem_cons = ((struct cb_cbmem_tab *)ptr)->cbmem_tab;
|
||||
}
|
||||
|
||||
static void cb_parse_framebuffer(unsigned char *ptr, struct sysinfo_t *info)
|
||||
|
@ -95,6 +127,11 @@ static void cb_parse_framebuffer(unsigned char *ptr, struct sysinfo_t *info)
|
|||
info->framebuffer = (struct cb_framebuffer *)ptr;
|
||||
}
|
||||
|
||||
static void cb_parse_string(unsigned char *ptr, char **info)
|
||||
{
|
||||
*info = (char *)((struct cb_string *)ptr)->string;
|
||||
}
|
||||
|
||||
static int cb_parse_header(void *addr, int len, struct sysinfo_t *info)
|
||||
{
|
||||
struct cb_header *header;
|
||||
|
@ -125,6 +162,9 @@ static int cb_parse_header(void *addr, int len, struct sysinfo_t *info)
|
|||
/* Now, walk the tables. */
|
||||
ptr += header->header_bytes;
|
||||
|
||||
/* Inintialize some fields to sentinel values. */
|
||||
info->vbnv_start = info->vbnv_size = (uint32_t)(-1);
|
||||
|
||||
for (i = 0; i < header->table_entries; i++) {
|
||||
struct cb_record *rec = (struct cb_record *)ptr;
|
||||
|
||||
|
@ -142,11 +182,35 @@ static int cb_parse_header(void *addr, int len, struct sysinfo_t *info)
|
|||
case CB_TAG_SERIAL:
|
||||
cb_parse_serial(ptr, info);
|
||||
break;
|
||||
case CB_TAG_CMOS_OPTION_TABLE:
|
||||
cb_parse_optiontable(ptr, info);
|
||||
case CB_TAG_VERSION:
|
||||
cb_parse_string(ptr, &info->version);
|
||||
break;
|
||||
case CB_TAG_OPTION_CHECKSUM:
|
||||
cb_parse_checksum(ptr, info);
|
||||
case CB_TAG_EXTRA_VERSION:
|
||||
cb_parse_string(ptr, &info->extra_version);
|
||||
break;
|
||||
case CB_TAG_BUILD:
|
||||
cb_parse_string(ptr, &info->build);
|
||||
break;
|
||||
case CB_TAG_COMPILE_TIME:
|
||||
cb_parse_string(ptr, &info->compile_time);
|
||||
break;
|
||||
case CB_TAG_COMPILE_BY:
|
||||
cb_parse_string(ptr, &info->compile_by);
|
||||
break;
|
||||
case CB_TAG_COMPILE_HOST:
|
||||
cb_parse_string(ptr, &info->compile_host);
|
||||
break;
|
||||
case CB_TAG_COMPILE_DOMAIN:
|
||||
cb_parse_string(ptr, &info->compile_domain);
|
||||
break;
|
||||
case CB_TAG_COMPILER:
|
||||
cb_parse_string(ptr, &info->compiler);
|
||||
break;
|
||||
case CB_TAG_LINKER:
|
||||
cb_parse_string(ptr, &info->linker);
|
||||
break;
|
||||
case CB_TAG_ASSEMBLER:
|
||||
cb_parse_string(ptr, &info->assembler);
|
||||
break;
|
||||
/*
|
||||
* FIXME we should warn on serial if coreboot set up a
|
||||
|
@ -155,6 +219,21 @@ static int cb_parse_header(void *addr, int len, struct sysinfo_t *info)
|
|||
case CB_TAG_FRAMEBUFFER:
|
||||
cb_parse_framebuffer(ptr, info);
|
||||
break;
|
||||
case CB_TAG_GPIO:
|
||||
cb_parse_gpios(ptr, info);
|
||||
break;
|
||||
case CB_TAG_VDAT:
|
||||
cb_parse_vdat(ptr, info);
|
||||
break;
|
||||
case CB_TAG_TIMESTAMPS:
|
||||
cb_parse_tstamp(ptr, info);
|
||||
break;
|
||||
case CB_TAG_CBMEM_CONSOLE:
|
||||
cb_parse_cbmem_cons(ptr, info);
|
||||
break;
|
||||
case CB_TAG_VBNV:
|
||||
cb_parse_vbnv(ptr, info);
|
||||
break;
|
||||
}
|
||||
|
||||
ptr += rec->size;
|
||||
|
@ -166,18 +245,12 @@ static int cb_parse_header(void *addr, int len, struct sysinfo_t *info)
|
|||
/* == Architecture specific == */
|
||||
/* This is the x86 specific stuff. */
|
||||
|
||||
/* Assume no translation or that memory is identity mapped. */
|
||||
static void *phys_to_virt(unsigned long virt)
|
||||
{
|
||||
return (void *)(uintptr_t)virt;
|
||||
}
|
||||
|
||||
int get_coreboot_info(struct sysinfo_t *info)
|
||||
{
|
||||
int ret = cb_parse_header(phys_to_virt(0x00000000), 0x1000, info);
|
||||
int ret = cb_parse_header((void *)0x00000000, 0x1000, info);
|
||||
|
||||
if (ret != 1)
|
||||
ret = cb_parse_header(phys_to_virt(0x000f0000), 0x1000, info);
|
||||
ret = cb_parse_header((void *)0x000f0000, 0x1000, info);
|
||||
|
||||
return (ret == 1) ? 0 : -1;
|
||||
}
|
||||
|
|
61
arch/x86/cpu/coreboot/timestamp.c
Normal file
61
arch/x86/cpu/coreboot/timestamp.c
Normal file
|
@ -0,0 +1,61 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/arch/timestamp.h>
|
||||
#include <asm/arch/sysinfo.h>
|
||||
#include <linux/compiler.h>
|
||||
|
||||
struct timestamp_entry {
|
||||
uint32_t entry_id;
|
||||
uint64_t entry_stamp;
|
||||
} __packed;
|
||||
|
||||
struct timestamp_table {
|
||||
uint64_t base_time;
|
||||
uint32_t max_entries;
|
||||
uint32_t num_entries;
|
||||
struct timestamp_entry entries[0]; /* Variable number of entries */
|
||||
} __packed;
|
||||
|
||||
static struct timestamp_table *ts_table __attribute__((section(".data")));
|
||||
|
||||
void timestamp_init(void)
|
||||
{
|
||||
ts_table = lib_sysinfo.tstamp_table;
|
||||
timer_set_tsc_base(ts_table->base_time);
|
||||
timestamp_add_now(TS_U_BOOT_INITTED);
|
||||
}
|
||||
|
||||
void timestamp_add(enum timestamp_id id, uint64_t ts_time)
|
||||
{
|
||||
struct timestamp_entry *tse;
|
||||
|
||||
if (!ts_table || (ts_table->num_entries == ts_table->max_entries))
|
||||
return;
|
||||
|
||||
tse = &ts_table->entries[ts_table->num_entries++];
|
||||
tse->entry_id = id;
|
||||
tse->entry_stamp = ts_time - ts_table->base_time;
|
||||
}
|
||||
|
||||
void timestamp_add_now(enum timestamp_id id)
|
||||
{
|
||||
timestamp_add(id, rdtsc());
|
||||
}
|
|
@ -34,6 +34,7 @@
|
|||
|
||||
#include <common.h>
|
||||
#include <command.h>
|
||||
#include <asm/control_regs.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/processor-flags.h>
|
||||
#include <asm/interrupt.h>
|
||||
|
@ -90,12 +91,6 @@ static void load_gdt(const u64 *boot_gdt, u16 num_entries)
|
|||
asm volatile("lgdtl %0\n" : : "m" (gdt));
|
||||
}
|
||||
|
||||
void init_gd(gd_t *id, u64 *gdt_addr)
|
||||
{
|
||||
id->gd_addr = (ulong)id;
|
||||
setup_gdt(id, gdt_addr);
|
||||
}
|
||||
|
||||
void setup_gdt(gd_t *id, u64 *gdt_addr)
|
||||
{
|
||||
/* CS: code, read/execute, 4 GB, base 0 */
|
||||
|
@ -121,6 +116,11 @@ void setup_gdt(gd_t *id, u64 *gdt_addr)
|
|||
load_fs(X86_GDT_ENTRY_32BIT_FS);
|
||||
}
|
||||
|
||||
int __weak x86_cleanup_before_linux(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
int x86_cpu_init_f(void)
|
||||
{
|
||||
const u32 em_rst = ~X86_CR0_EM;
|
||||
|
@ -148,16 +148,27 @@ int cpu_init_r(void) __attribute__((weak, alias("x86_cpu_init_r")));
|
|||
|
||||
void x86_enable_caches(void)
|
||||
{
|
||||
const u32 nw_cd_rst = ~(X86_CR0_NW | X86_CR0_CD);
|
||||
unsigned long cr0;
|
||||
|
||||
/* turn on the cache and disable write through */
|
||||
asm("movl %%cr0, %%eax\n"
|
||||
"andl %0, %%eax\n"
|
||||
"movl %%eax, %%cr0\n"
|
||||
"wbinvd\n" : : "i" (nw_cd_rst) : "eax");
|
||||
cr0 = read_cr0();
|
||||
cr0 &= ~(X86_CR0_NW | X86_CR0_CD);
|
||||
write_cr0(cr0);
|
||||
wbinvd();
|
||||
}
|
||||
void enable_caches(void) __attribute__((weak, alias("x86_enable_caches")));
|
||||
|
||||
void x86_disable_caches(void)
|
||||
{
|
||||
unsigned long cr0;
|
||||
|
||||
cr0 = read_cr0();
|
||||
cr0 |= X86_CR0_NW | X86_CR0_CD;
|
||||
wbinvd();
|
||||
write_cr0(cr0);
|
||||
wbinvd();
|
||||
}
|
||||
void disable_caches(void) __attribute__((weak, alias("x86_disable_caches")));
|
||||
|
||||
int x86_init_cache(void)
|
||||
{
|
||||
enable_caches();
|
||||
|
@ -201,3 +212,17 @@ void __reset_cpu(ulong addr)
|
|||
generate_gpf(); /* start the show */
|
||||
}
|
||||
void reset_cpu(ulong addr) __attribute__((weak, alias("__reset_cpu")));
|
||||
|
||||
int dcache_status(void)
|
||||
{
|
||||
return !(read_cr0() & 0x40000000);
|
||||
}
|
||||
|
||||
/* Define these functions to allow ehch-hcd to function */
|
||||
void flush_dcache_range(unsigned long start, unsigned long stop)
|
||||
{
|
||||
}
|
||||
|
||||
void invalidate_dcache_range(unsigned long start, unsigned long stop)
|
||||
{
|
||||
}
|
||||
|
|
|
@ -28,10 +28,14 @@
|
|||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/cache.h>
|
||||
#include <asm/control_regs.h>
|
||||
#include <asm/interrupt.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/processor-flags.h>
|
||||
#include <linux/compiler.h>
|
||||
#include <asm/msr.h>
|
||||
#include <asm/u-boot-x86.h>
|
||||
|
||||
#define DECLARE_INTERRUPT(x) \
|
||||
".globl irq_"#x"\n" \
|
||||
|
@ -41,72 +45,6 @@
|
|||
"pushl $"#x"\n" \
|
||||
"jmp irq_common_entry\n"
|
||||
|
||||
/*
|
||||
* Volatile isn't enough to prevent the compiler from reordering the
|
||||
* read/write functions for the control registers and messing everything up.
|
||||
* A memory clobber would solve the problem, but would prevent reordering of
|
||||
* all loads stores around it, which can hurt performance. Solution is to
|
||||
* use a variable and mimic reads and writes to it to enforce serialisation
|
||||
*/
|
||||
static unsigned long __force_order;
|
||||
|
||||
static inline unsigned long read_cr0(void)
|
||||
{
|
||||
unsigned long val;
|
||||
asm volatile("mov %%cr0,%0\n\t" : "=r" (val), "=m" (__force_order));
|
||||
return val;
|
||||
}
|
||||
|
||||
static inline unsigned long read_cr2(void)
|
||||
{
|
||||
unsigned long val;
|
||||
asm volatile("mov %%cr2,%0\n\t" : "=r" (val), "=m" (__force_order));
|
||||
return val;
|
||||
}
|
||||
|
||||
static inline unsigned long read_cr3(void)
|
||||
{
|
||||
unsigned long val;
|
||||
asm volatile("mov %%cr3,%0\n\t" : "=r" (val), "=m" (__force_order));
|
||||
return val;
|
||||
}
|
||||
|
||||
static inline unsigned long read_cr4(void)
|
||||
{
|
||||
unsigned long val;
|
||||
asm volatile("mov %%cr4,%0\n\t" : "=r" (val), "=m" (__force_order));
|
||||
return val;
|
||||
}
|
||||
|
||||
static inline unsigned long get_debugreg(int regno)
|
||||
{
|
||||
unsigned long val = 0; /* Damn you, gcc! */
|
||||
|
||||
switch (regno) {
|
||||
case 0:
|
||||
asm("mov %%db0, %0" : "=r" (val));
|
||||
break;
|
||||
case 1:
|
||||
asm("mov %%db1, %0" : "=r" (val));
|
||||
break;
|
||||
case 2:
|
||||
asm("mov %%db2, %0" : "=r" (val));
|
||||
break;
|
||||
case 3:
|
||||
asm("mov %%db3, %0" : "=r" (val));
|
||||
break;
|
||||
case 6:
|
||||
asm("mov %%db6, %0" : "=r" (val));
|
||||
break;
|
||||
case 7:
|
||||
asm("mov %%db7, %0" : "=r" (val));
|
||||
break;
|
||||
default:
|
||||
val = 0;
|
||||
}
|
||||
return val;
|
||||
}
|
||||
|
||||
void dump_regs(struct irq_regs *regs)
|
||||
{
|
||||
unsigned long cr0 = 0L, cr2 = 0L, cr3 = 0L, cr4 = 0L;
|
||||
|
@ -679,3 +617,32 @@ asm(".globl irq_common_entry\n" \
|
|||
DECLARE_INTERRUPT(253) \
|
||||
DECLARE_INTERRUPT(254) \
|
||||
DECLARE_INTERRUPT(255));
|
||||
|
||||
#if defined(CONFIG_INTEL_CORE_ARCH)
|
||||
/*
|
||||
* Get the number of CPU time counter ticks since it was read first time after
|
||||
* restart. This yields a free running counter guaranteed to take almost 6
|
||||
* years to wrap around even at 100GHz clock rate.
|
||||
*/
|
||||
u64 get_ticks(void)
|
||||
{
|
||||
static u64 tick_base;
|
||||
u64 now_tick = rdtsc();
|
||||
|
||||
if (!tick_base)
|
||||
tick_base = now_tick;
|
||||
|
||||
return now_tick - tick_base;
|
||||
}
|
||||
|
||||
#define PLATFORM_INFO_MSR 0xce
|
||||
|
||||
unsigned long get_tbclk(void)
|
||||
{
|
||||
u32 ratio;
|
||||
u64 platform_info = native_read_msr(PLATFORM_INFO_MSR);
|
||||
|
||||
ratio = (platform_info >> 8) & 0xff;
|
||||
return 100 * 1000 * 1000 * ratio; /* 100MHz times Max Non Turbo ratio */
|
||||
}
|
||||
#endif
|
||||
|
|
|
@ -55,8 +55,16 @@ _x86boot_start:
|
|||
movl %eax, %cr0
|
||||
wbinvd
|
||||
|
||||
/* Tell 32-bit code it is being entered from an in-RAM copy */
|
||||
movw $GD_FLG_WARM_BOOT, %bx
|
||||
jmp 1f
|
||||
_start:
|
||||
/* This is the 32-bit cold-reset entry point */
|
||||
/*
|
||||
* This is the 32-bit cold-reset entry point. Initialize %bx to 0
|
||||
* in case we're preceeded by some sort of boot stub.
|
||||
*/
|
||||
movw $GD_FLG_COLD_BOOT, %bx
|
||||
1:
|
||||
|
||||
/* Load the segement registes to match the gdt loaded in start16.S */
|
||||
movl $(X86_GDT_ENTRY_32BIT_DS * X86_GDT_ENTRY_SIZE), %eax
|
||||
|
@ -83,13 +91,33 @@ car_init_ret:
|
|||
* or fully initialised SDRAM - we really don't care which)
|
||||
* starting at CONFIG_SYS_CAR_ADDR to be used as a temporary stack
|
||||
*/
|
||||
movl $CONFIG_SYS_INIT_SP_ADDR, %esp
|
||||
|
||||
/* Initialise the Global Data Pointer */
|
||||
movl $CONFIG_SYS_INIT_GD_ADDR, %eax
|
||||
movl %eax, %edx
|
||||
addl $GENERATED_GBL_DATA_SIZE, %edx
|
||||
call init_gd;
|
||||
/* Stack grows down from top of CAR */
|
||||
movl $(CONFIG_SYS_CAR_ADDR + CONFIG_SYS_CAR_SIZE), %esp
|
||||
|
||||
/* Reserve space on stack for global data */
|
||||
subl $GENERATED_GBL_DATA_SIZE, %esp
|
||||
|
||||
/* Align global data to 16-byte boundary */
|
||||
andl $0xfffffff0, %esp
|
||||
|
||||
/* Setup first parameter to setup_gdt */
|
||||
movl %esp, %eax
|
||||
|
||||
/* Reserve space for global descriptor table */
|
||||
subl $X86_GDT_SIZE, %esp
|
||||
|
||||
/* Align temporary global descriptor table to 16-byte boundary */
|
||||
andl $0xfffffff0, %esp
|
||||
|
||||
/* Set second parameter to setup_gdt */
|
||||
movl %esp, %edx
|
||||
|
||||
/* gd->gd_addr = gd (Required to allow gd->xyz to work) */
|
||||
movl %eax, (%eax)
|
||||
|
||||
/* Setup global descriptor table so gd->xyz works */
|
||||
call setup_gdt
|
||||
|
||||
/* Set parameter to board_init_f() to boot flags */
|
||||
xorl %eax, %eax
|
||||
|
@ -113,9 +141,42 @@ board_init_f_r_trampoline:
|
|||
* %eax = Address of top of new stack
|
||||
*/
|
||||
|
||||
/* Setup stack in RAM */
|
||||
/* Stack grows down from top of SDRAM */
|
||||
movl %eax, %esp
|
||||
|
||||
/* Reserve space on stack for global data */
|
||||
subl $GENERATED_GBL_DATA_SIZE, %esp
|
||||
|
||||
/* Align global data to 16-byte boundary */
|
||||
andl $0xfffffff0, %esp
|
||||
|
||||
/* Setup first parameter to memcpy (and setup_gdt) */
|
||||
movl %esp, %eax
|
||||
|
||||
/* Setup second parameter to memcpy */
|
||||
fs movl 0, %edx
|
||||
|
||||
/* Set third parameter to memcpy */
|
||||
movl $GENERATED_GBL_DATA_SIZE, %ecx
|
||||
|
||||
/* Copy global data from CAR to SDRAM stack */
|
||||
call memcpy
|
||||
|
||||
/* Reserve space for global descriptor table */
|
||||
subl $X86_GDT_SIZE, %esp
|
||||
|
||||
/* Align global descriptor table to 16-byte boundary */
|
||||
andl $0xfffffff0, %esp
|
||||
|
||||
/* Set second parameter to setup_gdt */
|
||||
movl %esp, %edx
|
||||
|
||||
/* gd->gd_addr = gd (Required to allow gd->xyz to work) */
|
||||
movl %eax, (%eax)
|
||||
|
||||
/* Setup global descriptor table so gd->xyz works */
|
||||
call setup_gdt
|
||||
|
||||
/* Re-enter U-Boot by calling board_init_f_r */
|
||||
call board_init_f_r
|
||||
|
||||
|
|
|
@ -37,6 +37,9 @@
|
|||
.code16
|
||||
.globl start16
|
||||
start16:
|
||||
/* Set the Cold Boot / Hard Reset flag */
|
||||
movl $GD_FLG_COLD_BOOT, %ebx
|
||||
|
||||
/*
|
||||
* First we let the BSP do some early initialization
|
||||
* this code have to map the flash to its final position
|
||||
|
|
17
arch/x86/cpu/timer.c
Normal file
17
arch/x86/cpu/timer.c
Normal file
|
@ -0,0 +1,17 @@
|
|||
/*
|
||||
* Copyright (c) 2011 The Chromium OS Authors. All rights reserved.
|
||||
* Use of this source code is governed by a BSD-style license that can be
|
||||
* found in the LICENSE file.
|
||||
*
|
||||
* Alternatively, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") version 2 as published by the Free
|
||||
* Software Foundation.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
|
||||
unsigned long timer_get_us(void)
|
||||
{
|
||||
printf("timer_get_us used but not implemented.\n");
|
||||
return 0;
|
||||
}
|
|
@ -86,6 +86,8 @@ SECTIONS
|
|||
__bios_start = LOADADDR(.bios);
|
||||
__bios_size = SIZEOF(.bios);
|
||||
|
||||
#ifndef CONFIG_X86_NO_RESET_VECTOR
|
||||
|
||||
/*
|
||||
* The following expressions place the 16-bit Real-Mode code and
|
||||
* Reset Vector at the end of the Flash ROM
|
||||
|
@ -95,4 +97,5 @@ SECTIONS
|
|||
|
||||
. = RESET_VEC_LOC;
|
||||
.resetvec : AT (CONFIG_SYS_TEXT_BASE + (CONFIG_SYS_MONITOR_LEN - RESET_SEG_SIZE + RESET_VEC_LOC)) { KEEP(*(.resetvec)); }
|
||||
#endif
|
||||
}
|
||||
|
|
16
arch/x86/dts/coreboot.dtsi
Normal file
16
arch/x86/dts/coreboot.dtsi
Normal file
|
@ -0,0 +1,16 @@
|
|||
/include/ "skeleton.dtsi"
|
||||
|
||||
/ {
|
||||
aliases {
|
||||
console = "/serial";
|
||||
};
|
||||
|
||||
serial {
|
||||
compatible = "ns16550";
|
||||
reg-shift = <1>;
|
||||
io-mapped = <1>;
|
||||
multiplier = <1>;
|
||||
baudrate = <115200>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
13
arch/x86/dts/skeleton.dtsi
Normal file
13
arch/x86/dts/skeleton.dtsi
Normal file
|
@ -0,0 +1,13 @@
|
|||
/*
|
||||
* Skeleton device tree; the bare minimum needed to boot; just include and
|
||||
* add a compatible value. The bootloader will typically populate the memory
|
||||
* node.
|
||||
*/
|
||||
|
||||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
chosen { };
|
||||
aliases { };
|
||||
memory { device_type = "memory"; reg = <0 0>; };
|
||||
};
|
|
@ -30,32 +30,52 @@
|
|||
#ifndef _COREBOOT_SYSINFO_H
|
||||
#define _COREBOOT_SYSINFO_H
|
||||
|
||||
#include <common.h>
|
||||
#include <compiler.h>
|
||||
#include <fdt.h>
|
||||
#include <asm/arch/tables.h>
|
||||
|
||||
/* Allow a maximum of 16 memory range definitions. */
|
||||
#define SYSINFO_MAX_MEM_RANGES 16
|
||||
/* Allow a maximum of 8 GPIOs */
|
||||
#define SYSINFO_MAX_GPIOS 8
|
||||
|
||||
struct sysinfo_t {
|
||||
unsigned int cpu_khz;
|
||||
unsigned short ser_ioport;
|
||||
unsigned long ser_base; /* for mmapped serial */
|
||||
|
||||
int n_memranges;
|
||||
|
||||
struct memrange {
|
||||
unsigned long long base;
|
||||
unsigned long long size;
|
||||
unsigned int type;
|
||||
} memrange[SYSINFO_MAX_MEM_RANGES];
|
||||
|
||||
struct cb_cmos_option_table *option_table;
|
||||
u32 cmos_range_start;
|
||||
u32 cmos_range_end;
|
||||
u32 cmos_checksum_location;
|
||||
u32 vbnv_start;
|
||||
u32 vbnv_size;
|
||||
|
||||
char *version;
|
||||
char *extra_version;
|
||||
char *build;
|
||||
char *compile_time;
|
||||
char *compile_by;
|
||||
char *compile_host;
|
||||
char *compile_domain;
|
||||
char *compiler;
|
||||
char *linker;
|
||||
char *assembler;
|
||||
|
||||
struct cb_framebuffer *framebuffer;
|
||||
|
||||
unsigned long *mbtable; /** Pointer to the multiboot table */
|
||||
int num_gpios;
|
||||
struct cb_gpio gpios[SYSINFO_MAX_GPIOS];
|
||||
|
||||
void *vdat_addr;
|
||||
u32 vdat_size;
|
||||
void *tstamp_table;
|
||||
void *cbmem_cons;
|
||||
|
||||
struct cb_serial *serial;
|
||||
};
|
||||
|
||||
extern struct sysinfo_t lib_sysinfo;
|
||||
|
|
|
@ -164,6 +164,55 @@ struct cb_framebuffer {
|
|||
u8 reserved_mask_size;
|
||||
};
|
||||
|
||||
#define CB_TAG_GPIO 0x0013
|
||||
#define GPIO_MAX_NAME_LENGTH 16
|
||||
struct cb_gpio {
|
||||
u32 port;
|
||||
u32 polarity;
|
||||
u32 value;
|
||||
u8 name[GPIO_MAX_NAME_LENGTH];
|
||||
};
|
||||
|
||||
struct cb_gpios {
|
||||
u32 tag;
|
||||
u32 size;
|
||||
|
||||
u32 count;
|
||||
struct cb_gpio gpios[0];
|
||||
};
|
||||
|
||||
#define CB_TAG_FDT 0x0014
|
||||
struct cb_fdt {
|
||||
uint32_t tag;
|
||||
uint32_t size; /* size of the entire entry */
|
||||
/* the actual FDT gets placed here */
|
||||
};
|
||||
|
||||
#define CB_TAG_VDAT 0x0015
|
||||
struct cb_vdat {
|
||||
uint32_t tag;
|
||||
uint32_t size; /* size of the entire entry */
|
||||
void *vdat_addr;
|
||||
uint32_t vdat_size;
|
||||
};
|
||||
|
||||
#define CB_TAG_TIMESTAMPS 0x0016
|
||||
#define CB_TAG_CBMEM_CONSOLE 0x0017
|
||||
#define CB_TAG_MRC_CACHE 0x0018
|
||||
struct cb_cbmem_tab {
|
||||
uint32_t tag;
|
||||
uint32_t size;
|
||||
void *cbmem_tab;
|
||||
};
|
||||
|
||||
#define CB_TAG_VBNV 0x0019
|
||||
struct cb_vbnv {
|
||||
uint32_t tag;
|
||||
uint32_t size;
|
||||
uint32_t vbnv_start;
|
||||
uint32_t vbnv_size;
|
||||
};
|
||||
|
||||
#define CB_TAG_CMOS_OPTION_TABLE 0x00c8
|
||||
struct cb_cmos_option_table {
|
||||
u32 tag;
|
||||
|
@ -238,4 +287,29 @@ struct sysinfo_t;
|
|||
|
||||
int get_coreboot_info(struct sysinfo_t *info);
|
||||
|
||||
#define CBMEM_TOC_RESERVED 512
|
||||
#define MAX_CBMEM_ENTRIES 16
|
||||
#define CBMEM_MAGIC 0x434f5245
|
||||
|
||||
struct cbmem_entry {
|
||||
u32 magic;
|
||||
u32 id;
|
||||
u64 base;
|
||||
u64 size;
|
||||
} __packed;
|
||||
|
||||
#define CBMEM_ID_FREESPACE 0x46524545
|
||||
#define CBMEM_ID_GDT 0x4c474454
|
||||
#define CBMEM_ID_ACPI 0x41435049
|
||||
#define CBMEM_ID_CBTABLE 0x43425442
|
||||
#define CBMEM_ID_PIRQ 0x49525154
|
||||
#define CBMEM_ID_MPTABLE 0x534d5054
|
||||
#define CBMEM_ID_RESUME 0x5245534d
|
||||
#define CBMEM_ID_RESUME_SCRATCH 0x52455343
|
||||
#define CBMEM_ID_SMBIOS 0x534d4254
|
||||
#define CBMEM_ID_TIMESTAMP 0x54494d45
|
||||
#define CBMEM_ID_MRCDATA 0x4d524344
|
||||
#define CBMEM_ID_CONSOLE 0x434f4e53
|
||||
#define CBMEM_ID_NONE 0x00000000
|
||||
|
||||
#endif
|
||||
|
|
52
arch/x86/include/asm/arch-coreboot/timestamp.h
Normal file
52
arch/x86/include/asm/arch-coreboot/timestamp.h
Normal file
|
@ -0,0 +1,52 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
|
||||
*/
|
||||
|
||||
#ifndef __COREBOOT_TIMESTAMP_H__
|
||||
#define __COREBOOT_TIMESTAMP_H__
|
||||
|
||||
enum timestamp_id {
|
||||
/* coreboot specific timestamp IDs */
|
||||
TS_START_ROMSTAGE = 1,
|
||||
TS_BEFORE_INITRAM = 2,
|
||||
TS_AFTER_INITRAM = 3,
|
||||
TS_END_ROMSTAGE = 4,
|
||||
TS_START_COPYRAM = 8,
|
||||
TS_END_COPYRAM = 9,
|
||||
TS_START_RAMSTAGE = 10,
|
||||
TS_DEVICE_ENUMERATE = 30,
|
||||
TS_DEVICE_CONFIGURE = 40,
|
||||
TS_DEVICE_ENABLE = 50,
|
||||
TS_DEVICE_INITIALIZE = 60,
|
||||
TS_DEVICE_DONE = 70,
|
||||
TS_CBMEM_POST = 75,
|
||||
TS_WRITE_TABLES = 80,
|
||||
TS_LOAD_PAYLOAD = 90,
|
||||
TS_ACPI_WAKE_JUMP = 98,
|
||||
TS_SELFBOOT_JUMP = 99,
|
||||
|
||||
/* U-Boot entry IDs start at 1000 */
|
||||
TS_U_BOOT_INITTED = 1000, /* This is where u-boot starts */
|
||||
TS_U_BOOT_START_KERNEL = 1100, /* Right before jumping to kernel. */
|
||||
};
|
||||
|
||||
void timestamp_init(void);
|
||||
void timestamp_add(enum timestamp_id id, uint64_t ts_time);
|
||||
void timestamp_add_now(enum timestamp_id id);
|
||||
|
||||
#endif
|
|
@ -351,6 +351,11 @@ static __inline__ int ffs(int x)
|
|||
}
|
||||
#define PLATFORM_FFS
|
||||
|
||||
static inline int __ilog2(unsigned int x)
|
||||
{
|
||||
return generic_fls(x) - 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* hweightN - returns the hamming weight of a N-bit word
|
||||
* @x: the word to weigh
|
||||
|
|
Some files were not shown because too many files have changed in this diff Show more
Loading…
Add table
Reference in a new issue