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ns16550: unify serial_rockchip

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Unify serial_rockchip, and use the generic binding.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Reviewed-by: Tom Rini <trini@konsulko.com>
Tested-by: Ariel D'Alessandro <ariel@vanguardiasur.com.ar>
Acked-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Thomas Chou 2015-11-19 21:48:08 +08:00 • committed by Tom Rini
parent f27445cbdc
commit 98a51fc3d7
5 changed files with 6 additions and 57 deletions
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5
arch/arm/dts/rk3288.dtsi
View file

@ -324,6 +324,7 @@
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>; reg-shift = <2>;
reg-io-width = <4>; reg-io-width = <4>;
clock-frequency = <24000000>;
clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
clock-names = "baudclk", "apb_pclk"; clock-names = "baudclk", "apb_pclk";
pinctrl-names = "default"; pinctrl-names = "default";
@ -337,6 +338,7 @@
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>; reg-shift = <2>;
reg-io-width = <4>; reg-io-width = <4>;
clock-frequency = <24000000>;
clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
clock-names = "baudclk", "apb_pclk"; clock-names = "baudclk", "apb_pclk";
pinctrl-names = "default"; pinctrl-names = "default";
@ -350,6 +352,7 @@
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>; reg-shift = <2>;
reg-io-width = <4>; reg-io-width = <4>;
clock-frequency = <24000000>;
clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
clock-names = "baudclk", "apb_pclk"; clock-names = "baudclk", "apb_pclk";
pinctrl-names = "default"; pinctrl-names = "default";
@ -362,6 +365,7 @@
interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>; reg-shift = <2>;
reg-io-width = <4>; reg-io-width = <4>;
clock-frequency = <24000000>;
clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
clock-names = "baudclk", "apb_pclk"; clock-names = "baudclk", "apb_pclk";
pinctrl-names = "default"; pinctrl-names = "default";
@ -375,6 +379,7 @@
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>; reg-shift = <2>;
reg-io-width = <4>; reg-io-width = <4>;
clock-frequency = <24000000>;
clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
clock-names = "baudclk", "apb_pclk"; clock-names = "baudclk", "apb_pclk";
pinctrl-names = "default"; pinctrl-names = "default";

3
arch/arm/mach-rockchip/Kconfig
View file

@ -33,9 +33,6 @@ config DM_I2C
config DM_GPIO config DM_GPIO
default y default y
config ROCKCHIP_SERIAL
default y
source "arch/arm/mach-rockchip/rk3288/Kconfig" source "arch/arm/mach-rockchip/rk3288/Kconfig"
endif endif

11
drivers/serial/Kconfig
View file

@ -186,19 +186,10 @@ config ALTERA_UART
Select this to enable an UART for Altera devices. Please find Select this to enable an UART for Altera devices. Please find
details on the "Embedded Peripherals IP User Guide" of Altera. details on the "Embedded Peripherals IP User Guide" of Altera.
config ROCKCHIP_SERIAL
bool "Rockchip on-chip UART support"
depends on ARCH_ROCKCHIP && DM_SERIAL
help
Select this to enable a debug UART for Rockchip devices. This uses
the ns16550 driver. You will need to #define CONFIG_SYS_NS16550 in
your board config header. The clock input is automatically set to
use the oscillator (24MHz).
config NS16550_SERIAL config NS16550_SERIAL
bool "NS16550 UART or compatible" bool "NS16550 UART or compatible"
depends on DM_SERIAL depends on DM_SERIAL
default y if X86 || PPC default y if X86 || PPC || ARCH_ROCKCHIP
help help
Support NS16550 UART or compatible with driver model. This can be Support NS16550 UART or compatible with driver model. This can be
enabled in the device tree with the correct input clock frequency. enabled in the device tree with the correct input clock frequency.

1
drivers/serial/Makefile
View file

@ -40,7 +40,6 @@ obj-$(CONFIG_ZYNQ_SERIAL) += serial_zynq.o
obj-$(CONFIG_BFIN_SERIAL) += serial_bfin.o obj-$(CONFIG_BFIN_SERIAL) += serial_bfin.o
obj-$(CONFIG_FSL_LPUART) += serial_lpuart.o obj-$(CONFIG_FSL_LPUART) += serial_lpuart.o
obj-$(CONFIG_MXS_AUART) += mxs_auart.o obj-$(CONFIG_MXS_AUART) += mxs_auart.o
obj-$(CONFIG_ROCKCHIP_SERIAL) += serial_rockchip.o
obj-$(CONFIG_ARC_SERIAL) += serial_arc.o obj-$(CONFIG_ARC_SERIAL) += serial_arc.o
obj-$(CONFIG_TEGRA_SERIAL) += serial_tegra.o obj-$(CONFIG_TEGRA_SERIAL) += serial_tegra.o
obj-$(CONFIG_UNIPHIER_SERIAL) += serial_uniphier.o obj-$(CONFIG_UNIPHIER_SERIAL) += serial_uniphier.o

43
drivers/serial/serial_rockchip.c
View file

@ -1,43 +0,0 @@
/*
* Copyright (c) 2015 Google, Inc
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <dm.h>
#include <ns16550.h>
#include <serial.h>
#include <asm/arch/clock.h>
static const struct udevice_id rockchip_serial_ids[] = {
{ .compatible = "rockchip,rk3288-uart" },
{ }
};
static int rockchip_serial_ofdata_to_platdata(struct udevice *dev)
{
struct ns16550_platdata *plat = dev_get_platdata(dev);
int ret;
ret = ns16550_serial_ofdata_to_platdata(dev);
if (ret)
return ret;
/* Do all Rockchip parts use 24MHz? */
plat->clock = 24 * 1000000;
return 0;
}
U_BOOT_DRIVER(serial_ns16550) = {
.name = "serial_rockchip",
.id = UCLASS_SERIAL,
.of_match = rockchip_serial_ids,
.ofdata_to_platdata = rockchip_serial_ofdata_to_platdata,
.platdata_auto_alloc_size = sizeof(struct ns16550_platdata),
.priv_auto_alloc_size = sizeof(struct NS16550),
.probe = ns16550_serial_probe,
.ops = &ns16550_serial_ops,
.flags = DM_FLAG_PRE_RELOC,
};