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ddr: altera: sequencer: Zap VFIFO_SIZE
Just use READ_VALID_FIFO_SIZE directly, no need for this macro obfuscation. Signed-off-by: Marek Vasut <marex@denx.de> Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
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2 changed files with 4 additions and 7 deletions
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@ -1507,7 +1507,7 @@ static void rw_mgr_decr_vfifo(const u32 grp)
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{
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u32 i;
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for (i = 0; i < VFIFO_SIZE - 1; i++)
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for (i = 0; i < READ_VALID_FIFO_SIZE - 1; i++)
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rw_mgr_incr_vfifo(grp);
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}
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@ -1521,7 +1521,7 @@ static int find_vfifo_failing_read(const u32 grp)
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{
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u32 v, ret, fail_cnt = 0;
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for (v = 0; v < VFIFO_SIZE; v++) {
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for (v = 0; v < READ_VALID_FIFO_SIZE; v++) {
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debug_cond(DLEVEL == 2, "%s:%d: vfifo %u\n",
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__func__, __LINE__, v);
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ret = rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
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@ -1592,7 +1592,7 @@ static int sdr_find_phase_delay(int working, int delay, const u32 grp,
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static int sdr_find_phase(int working, const u32 grp, u32 *work,
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u32 *i, u32 *p)
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{
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const u32 end = VFIFO_SIZE + (working ? 0 : 1);
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const u32 end = READ_VALID_FIFO_SIZE + (working ? 0 : 1);
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int ret;
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for (; *i < end; (*i)++) {
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@ -1773,7 +1773,7 @@ static int sdr_find_window_center(const u32 grp, const u32 work_bgn,
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* push vfifo until we can successfully calibrate. We can do this
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* because the largest possible margin in 1 VFIFO cycle.
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*/
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for (i = 0; i < VFIFO_SIZE; i++) {
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for (i = 0; i < READ_VALID_FIFO_SIZE; i++) {
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debug_cond(DLEVEL == 2, "find_dqs_en_phase: center\n");
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if (rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
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PASS_ONE_BIT,
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@ -65,9 +65,6 @@
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#define CAL_SUBSTAGE_READ_LATENCY 1
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#define CAL_SUBSTAGE_REFRESH 1
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/* length of VFIFO, from SW_MACROS */
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#define VFIFO_SIZE (READ_VALID_FIFO_SIZE)
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#define SCC_MGR_GROUP_COUNTER_OFFSET 0x0000
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#define SCC_MGR_DQS_IN_DELAY_OFFSET 0x0100
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#define SCC_MGR_DQS_EN_PHASE_OFFSET 0x0200
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