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Minor code cleanup.

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This commit is contained in:
Wolfgang Denk 2006-12-24 01:42:57 +01:00 • committed by Wolfgang Denk
parent de8404441b
commit 9c0f42ecfe
2 changed files with 292 additions and 298 deletions
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14
board/tqm8272/tqm8272.c
View file

@ -216,7 +216,7 @@ const iop_conf_t iop_conf_tab[4][32] = {
/* UPM pattern for bus clock = 66.7 MHz */ /* UPM pattern for bus clock = 66.7 MHz */
static const uint upmTable67[] = static const uint upmTable67[] =
{ {
/* Offset */ /* UPM Read Single RAM array entry -> NAND Read Data */ /* Offset UPM Read Single RAM array entry -> NAND Read Data */
/* 0x00 */ 0x0fa3f100, 0x0fa3b000, 0x0fa33100, 0x0fa33000, /* 0x00 */ 0x0fa3f100, 0x0fa3b000, 0x0fa33100, 0x0fa33000,
/* 0x04 */ 0x0fa33000, 0x0fa33004, 0xfffffc01, 0xfffffc00, /* 0x04 */ 0x0fa33000, 0x0fa33004, 0xfffffc01, 0xfffffc00,
@ -250,7 +250,7 @@ static const uint upmTable67[] =
/* UPM pattern for bus clock = 100 MHz */ /* UPM pattern for bus clock = 100 MHz */
static const uint upmTable100[] = static const uint upmTable100[] =
{ {
/* Offset */ /* UPM Read Single RAM array entry -> NAND Read Data */ /* Offset UPM Read Single RAM array entry -> NAND Read Data */
/* 0x00 */ 0x0fa3f200, 0x0fa3b000, 0x0fa33300, 0x0fa33000, /* 0x00 */ 0x0fa3f200, 0x0fa3b000, 0x0fa33300, 0x0fa33000,
/* 0x04 */ 0x0fa33000, 0x0fa33004, 0xfffffc01, 0xfffffc00, /* 0x04 */ 0x0fa33000, 0x0fa33004, 0xfffffc01, 0xfffffc00,
@ -284,7 +284,7 @@ static const uint upmTable100[] =
/* UPM pattern for bus clock = 133.3 MHz */ /* UPM pattern for bus clock = 133.3 MHz */
static const uint upmTable133[] = static const uint upmTable133[] =
{ {
/* Offset */ /* UPM Read Single RAM array entry -> NAND Read Data */ /* Offset UPM Read Single RAM array entry -> NAND Read Data */
/* 0x00 */ 0x0fa3f300, 0x0fa3b000, 0x0fa33300, 0x0fa33000, /* 0x00 */ 0x0fa3f300, 0x0fa3b000, 0x0fa33300, 0x0fa33000,
/* 0x04 */ 0x0fa33200, 0x0fa33004, 0xfffffc01, 0xfffffc00, /* 0x04 */ 0x0fa33200, 0x0fa33004, 0xfffffc01, 0xfffffc00,
@ -320,7 +320,7 @@ static int chipsel = 0;
/* UPM pattern for slow init */ /* UPM pattern for slow init */
static const uint upmTableSlow[] = static const uint upmTableSlow[] =
{ {
/* Offset */ /* UPM Read Single RAM array entry */ /* Offset UPM Read Single RAM array entry */
/* 0x00 */ 0xffffee00, 0x00ffcc80, 0x00ffcf00, 0x00ffdc00, /* 0x00 */ 0xffffee00, 0x00ffcc80, 0x00ffcf00, 0x00ffdc00,
/* 0x04 */ 0x00ffce80, 0x00ffcc00, 0x00ffee00, 0x3fffcc07, /* 0x04 */ 0x00ffce80, 0x00ffcc00, 0x00ffee00, 0x3fffcc07,
@ -354,7 +354,7 @@ static const uint upmTableSlow[] =
/* UPM pattern for fast init */ /* UPM pattern for fast init */
static const uint upmTableFast[] = static const uint upmTableFast[] =
{ {
/* Offset */ /* UPM Read Single RAM array entry */ /* Offset UPM Read Single RAM array entry */
/* 0x00 */ 0xffffee00, 0x00ffcc80, 0x00ffcd80, 0x00ffdc00, /* 0x00 */ 0xffffee00, 0x00ffcc80, 0x00ffcd80, 0x00ffdc00,
/* 0x04 */ 0x00ffdc00, 0x00ffcf00, 0x00ffec00, 0x3fffcc07, /* 0x04 */ 0x00ffdc00, 0x00ffcf00, 0x00ffec00, 0x3fffcc07,
@ -605,8 +605,7 @@ static inline int scanChar (char *p, int len, unsigned long *number)
int akt = 0; int akt = 0;
*number = 0; *number = 0;
while (akt < len) while (akt < len) {
{
if ((*p >= '0') && (*p <= '9')) { if ((*p >= '0') && (*p <= '9')) {
*number *= 10; *number *= 10;
*number += *p - '0'; *number += *p - '0';
@ -1233,4 +1232,3 @@ void pci_init_board(void)
pci_mpc8250_init(&hose); pci_mpc8250_init(&hose);
} }
#endif #endif

4
include/configs/TQM8272.h
View file

@ -262,7 +262,6 @@
#define MIIDELAY udelay(1) #define MIIDELAY udelay(1)
/* system clock rate (CLKIN) - equal to the 60x and local bus speed */ /* system clock rate (CLKIN) - equal to the 60x and local bus speed */
#define CONFIG_8260_CLKIN 66666666 /* in Hz */ #define CONFIG_8260_CLKIN 66666666 /* in Hz */
@ -499,7 +498,6 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/
#define BOOTFLAG_WARM 0x02 /* Software reboot */ #define BOOTFLAG_WARM 0x02 /* Software reboot */
/*----------------------------------------------------------------------- /*-----------------------------------------------------------------------
* Cache Configuration * Cache Configuration
*/ */
@ -634,7 +632,6 @@
*/ */
#define CFG_MRS_OFFS 0x00000110 #define CFG_MRS_OFFS 0x00000110
/* Bank 0 - FLASH /* Bank 0 - FLASH
*/ */
#define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\ #define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\
@ -724,7 +721,6 @@
PSDMR_BUFCMD |\ PSDMR_BUFCMD |\
PSDMR_CL_2) PSDMR_CL_2)
#define PSDMR_RFRC_66MHZ_SINGLE 0x00028000 /* PSDMR[RFRC] at 66 MHz single mode */ #define PSDMR_RFRC_66MHZ_SINGLE 0x00028000 /* PSDMR[RFRC] at 66 MHz single mode */
#define PSDMR_RFRC_100MHZ_SINGLE 0x00030000 /* PSDMR[RFRC] at 100 MHz single mode */ #define PSDMR_RFRC_100MHZ_SINGLE 0x00030000 /* PSDMR[RFRC] at 100 MHz single mode */
#define PSDMR_RFRC_133MHZ_SINGLE 0x00030000 /* PSDMR[RFRC] at 133 MHz single mode */ #define PSDMR_RFRC_133MHZ_SINGLE 0x00030000 /* PSDMR[RFRC] at 133 MHz single mode */