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Minor code cleanup.
This commit is contained in:
parent
de8404441b
commit
9c0f42ecfe
2 changed files with 292 additions and 298 deletions
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@ -216,7 +216,7 @@ const iop_conf_t iop_conf_tab[4][32] = {
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/* UPM pattern for bus clock = 66.7 MHz */
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static const uint upmTable67[] =
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{
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/* Offset */ /* UPM Read Single RAM array entry -> NAND Read Data */
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/* Offset UPM Read Single RAM array entry -> NAND Read Data */
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/* 0x00 */ 0x0fa3f100, 0x0fa3b000, 0x0fa33100, 0x0fa33000,
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/* 0x04 */ 0x0fa33000, 0x0fa33004, 0xfffffc01, 0xfffffc00,
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@ -250,7 +250,7 @@ static const uint upmTable67[] =
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/* UPM pattern for bus clock = 100 MHz */
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static const uint upmTable100[] =
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{
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/* Offset */ /* UPM Read Single RAM array entry -> NAND Read Data */
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/* Offset UPM Read Single RAM array entry -> NAND Read Data */
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/* 0x00 */ 0x0fa3f200, 0x0fa3b000, 0x0fa33300, 0x0fa33000,
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/* 0x04 */ 0x0fa33000, 0x0fa33004, 0xfffffc01, 0xfffffc00,
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@ -284,7 +284,7 @@ static const uint upmTable100[] =
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/* UPM pattern for bus clock = 133.3 MHz */
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static const uint upmTable133[] =
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{
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/* Offset */ /* UPM Read Single RAM array entry -> NAND Read Data */
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/* Offset UPM Read Single RAM array entry -> NAND Read Data */
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/* 0x00 */ 0x0fa3f300, 0x0fa3b000, 0x0fa33300, 0x0fa33000,
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/* 0x04 */ 0x0fa33200, 0x0fa33004, 0xfffffc01, 0xfffffc00,
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@ -320,7 +320,7 @@ static int chipsel = 0;
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/* UPM pattern for slow init */
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static const uint upmTableSlow[] =
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{
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/* Offset */ /* UPM Read Single RAM array entry */
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/* Offset UPM Read Single RAM array entry */
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/* 0x00 */ 0xffffee00, 0x00ffcc80, 0x00ffcf00, 0x00ffdc00,
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/* 0x04 */ 0x00ffce80, 0x00ffcc00, 0x00ffee00, 0x3fffcc07,
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@ -354,7 +354,7 @@ static const uint upmTableSlow[] =
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/* UPM pattern for fast init */
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static const uint upmTableFast[] =
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{
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/* Offset */ /* UPM Read Single RAM array entry */
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/* Offset UPM Read Single RAM array entry */
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/* 0x00 */ 0xffffee00, 0x00ffcc80, 0x00ffcd80, 0x00ffdc00,
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/* 0x04 */ 0x00ffdc00, 0x00ffcf00, 0x00ffec00, 0x3fffcc07,
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@ -605,8 +605,7 @@ static inline int scanChar (char *p, int len, unsigned long *number)
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int akt = 0;
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*number = 0;
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while (akt < len)
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{
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while (akt < len) {
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if ((*p >= '0') && (*p <= '9')) {
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*number *= 10;
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*number += *p - '0';
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@ -1233,4 +1232,3 @@ void pci_init_board(void)
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pci_mpc8250_init(&hose);
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}
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#endif
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@ -262,7 +262,6 @@
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#define MIIDELAY udelay(1)
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/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
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#define CONFIG_8260_CLKIN 66666666 /* in Hz */
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@ -499,7 +498,6 @@
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#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/
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#define BOOTFLAG_WARM 0x02 /* Software reboot */
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/*-----------------------------------------------------------------------
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* Cache Configuration
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*/
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@ -634,7 +632,6 @@
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*/
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#define CFG_MRS_OFFS 0x00000110
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/* Bank 0 - FLASH
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*/
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#define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\
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@ -724,7 +721,6 @@
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PSDMR_BUFCMD |\
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PSDMR_CL_2)
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#define PSDMR_RFRC_66MHZ_SINGLE 0x00028000 /* PSDMR[RFRC] at 66 MHz single mode */
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#define PSDMR_RFRC_100MHZ_SINGLE 0x00030000 /* PSDMR[RFRC] at 100 MHz single mode */
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#define PSDMR_RFRC_133MHZ_SINGLE 0x00030000 /* PSDMR[RFRC] at 133 MHz single mode */
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