mirror of
https://github.com/Fishwaldo/u-boot.git
synced 2025-03-18 13:11:31 +00:00
Merge branch 'master' of git://www.denx.de/git/u-boot-microblaze
This commit is contained in:
commit
9c1d0e9f16
10 changed files with 231 additions and 3 deletions
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@ -8,3 +8,4 @@
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extra-y = start.o
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obj-y = irq.o
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obj-y += cpu.o interrupts.o cache.o exception.o timer.o
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obj-$(CONFIG_SPL_BUILD) += spl.o
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@ -35,6 +35,9 @@ void _hw_exception_handler (void)
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puts ("Divide by zero exception\n");
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break;
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#ifdef MICROBLAZE_V5
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case 0x7:
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puts("Priviledged or stack protection violation exception\n");
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break;
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case 0x1000:
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puts ("Exception in delay slot\n");
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break;
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55
arch/microblaze/cpu/spl.c
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55
arch/microblaze/cpu/spl.c
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@ -0,0 +1,55 @@
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/*
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* (C) Copyright 2013 - 2014 Xilinx, Inc
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*
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* Michal Simek <michal.simek@xilinx.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <image.h>
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#include <spl.h>
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#include <version.h>
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#include <asm/io.h>
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#include <asm/u-boot.h>
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DECLARE_GLOBAL_DATA_PTR;
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bool boot_linux;
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u32 spl_boot_device(void)
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{
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return BOOT_DEVICE_NOR;
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}
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/* Board initialization after bss clearance */
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void spl_board_init(void)
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{
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gd = (gd_t *)CONFIG_SPL_STACK_ADDR;
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/* enable console uart printing */
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preloader_console_init();
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}
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#ifdef CONFIG_SPL_OS_BOOT
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void __noreturn jump_to_image_linux(void *arg)
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{
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debug("Entering kernel arg pointer: 0x%p\n", arg);
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typedef void (*image_entry_arg_t)(char *, ulong, ulong)
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__attribute__ ((noreturn));
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image_entry_arg_t image_entry =
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(image_entry_arg_t)spl_image.entry_point;
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image_entry(NULL, 0, (ulong)arg);
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}
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#endif /* CONFIG_SPL_OS_BOOT */
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int spl_start_uboot(void)
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{
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#ifdef CONFIG_SPL_OS_BOOT
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if (boot_linux)
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return 0;
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#endif
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return 1;
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}
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@ -22,6 +22,11 @@ _start:
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*/
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mts rmsr, r0 /* disable cache */
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#if defined(CONFIG_SPL_BUILD)
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addi r1, r0, CONFIG_SPL_STACK_ADDR
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addi r1, r1, -4 /* Decrement SP to top of memory */
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#else
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addi r1, r0, CONFIG_SYS_INIT_SP_OFFSET
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addi r1, r1, -4 /* Decrement SP to top of memory */
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@ -115,6 +120,7 @@ _start:
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sh r7, r0, r8
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rsubi r8, r10, 0x26
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sh r6, r0, r8
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#endif /* BUILD_SPL */
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/* Flush cache before enable cache */
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addik r5, r0, 0
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@ -139,9 +145,14 @@ clear_bss:
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cmp r6, r5, r4 /* check if we have reach the end */
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bnei r6, 2b
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3: /* jumping to board_init */
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#ifndef CONFIG_SPL_BUILD
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brai board_init_f
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#else
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brai board_init_r
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#endif
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1: bri 1b
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#ifndef CONFIG_SPL_BUILD
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/*
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* Read 16bit little endian
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*/
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@ -174,3 +185,4 @@ out16: bslli r3, r6, 8
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rtsd r15, 8
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or r0, r0, r0
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.end out16
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#endif
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@ -34,6 +34,7 @@ void __udelay(unsigned long usec)
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}
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}
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#ifndef CONFIG_SPL_BUILD
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static void timer_isr(void *arg)
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{
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timestamp++;
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@ -62,10 +63,15 @@ int timer_init (void)
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if (ret)
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tmr = NULL;
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}
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/* No problem if timer is not found/initialized */
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return 0;
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}
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#else
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int timer_init(void)
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{
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return 0;
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}
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#endif
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/*
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* This function is derived from PowerPC code (read timebase as long long).
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57
arch/microblaze/cpu/u-boot-spl.lds
Normal file
57
arch/microblaze/cpu/u-boot-spl.lds
Normal file
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@ -0,0 +1,57 @@
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/*
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* (C) Copyright 2013 - 2014 Xilinx, Inc
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*
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* Michal Simek <michal.simek@xilinx.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <asm-offsets.h>
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OUTPUT_ARCH(microblaze)
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ENTRY(_start)
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SECTIONS
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{
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.text ALIGN(0x4):
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{
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__text_start = .;
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arch/microblaze/cpu/start.o (.text)
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*(.text)
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*(.text.*)
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__text_end = .;
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}
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.rodata ALIGN(0x4):
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{
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__rodata_start = .;
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*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
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__rodata_end = .;
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}
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.data ALIGN(0x4):
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{
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__data_start = .;
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*(.data)
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*(.data.*)
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__data_end = .;
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}
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.bss ALIGN(0x4):
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{
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__bss_start = .;
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*(.sbss)
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*(.scommon)
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*(.bss)
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*(.bss.*)
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*(COMMON)
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. = ALIGN(4);
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__bss_end = .;
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}
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__end = . ;
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}
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#if defined(CONFIG_SPL_MAX_FOOTPRINT)
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ASSERT(__end - _start < (CONFIG_SPL_MAX_FOOTPRINT), \
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"SPL image plus BSS too big");
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#endif
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16
arch/microblaze/include/asm/spl.h
Normal file
16
arch/microblaze/include/asm/spl.h
Normal file
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@ -0,0 +1,16 @@
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/*
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* (C) Copyright 2013 - 2014 Xilinx, Inc
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*
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* Michal Simek <michal.simek@xilinx.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _ASM_MICROBLAZE_SPL_H_
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#define _ASM_MICROBLAZE_SPL_H_
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#define BOOT_DEVICE_RAM 1
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#define BOOT_DEVICE_NOR 2
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#define BOOT_DEVICE_SPI 3
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#endif
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@ -25,6 +25,7 @@ typedef struct bd_info {
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unsigned long bi_sramstart; /* start of SRAM memory */
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unsigned long bi_sramsize; /* size of SRAM memory */
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unsigned int bi_baudrate; /* Console Baudrate */
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ulong bi_boot_params; /* where this board expects params */
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} bd_t;
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/* For image.h:image_check_target_arch() */
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@ -24,6 +24,12 @@
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DECLARE_GLOBAL_DATA_PTR;
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static int display_banner(void)
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{
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printf("\n\n%s\n\n", version_string);
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return 0;
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}
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/*
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* All attempts to come up with a "common" initialization sequence
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* that works for all boards and architectures failed: some of the
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fdtdec_check_fdt,
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#endif
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serial_init,
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#ifndef CONFIG_SPL_BUILD
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console_init_f,
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#endif
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display_banner,
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#ifndef CONFIG_SPL_BUILD
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interrupts_init,
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timer_init,
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#endif
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NULL,
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};
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gd = (gd_t *)(CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_GBL_DATA_OFFSET);
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bd = (bd_t *)(CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_GBL_DATA_OFFSET
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- GENERATED_BD_INFO_SIZE);
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#if defined(CONFIG_CMD_FLASH)
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#if defined(CONFIG_CMD_FLASH) && !defined(CONFIG_SPL_BUILD)
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ulong flash_size = 0;
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#endif
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asm ("nop"); /* FIXME gd is not initialize - wait */
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/* FDT is at end of image */
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gd->fdt_blob = (void *)__end;
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#endif
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#ifndef CONFIG_SPL_BUILD
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/* Allow the early environment to override the fdt address */
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gd->fdt_blob = (void *)getenv_ulong("fdtcontroladdr", 16,
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(uintptr_t)gd->fdt_blob);
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#endif
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/*
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* The Malloc area is immediately below the monitor copy in DRAM
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hang();
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}
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#ifndef CONFIG_SPL_BUILD
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#ifdef CONFIG_OF_CONTROL
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/* For now, put this check after the console is ready */
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if (fdtdec_prepare_fdt())
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WATCHDOG_RESET();
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main_loop();
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}
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#endif /* CONFIG_SPL_BUILD */
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}
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@ -200,7 +200,8 @@
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# define CONFIG_SYS_MAX_FLASH_SECT 512
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/* hardware flash protection */
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# define CONFIG_SYS_FLASH_PROTECTION
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/* use buffered writes (20x faster) */
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# define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
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# ifdef RAMENV
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# define CONFIG_ENV_IS_NOWHERE 1
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# define CONFIG_ENV_SIZE 0x1000
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# undef CONFIG_PHYLIB
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#endif
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/* SPL part */
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#define CONFIG_SPL
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#define CONFIG_CMD_SPL
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#define CONFIG_SPL_FRAMEWORK
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#define CONFIG_SPL_LIBCOMMON_SUPPORT
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#define CONFIG_SPL_LIBGENERIC_SUPPORT
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#define CONFIG_SPL_SERIAL_SUPPORT
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#define CONFIG_SPL_BOARD_INIT
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#define CONFIG_SPL_LDSCRIPT "arch/microblaze/cpu/u-boot-spl.lds"
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#define CONFIG_SPL_RAM_DEVICE
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#define CONFIG_SPL_NOR_SUPPORT
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/* for booting directly linux */
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#define CONFIG_SPL_OS_BOOT
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#define CONFIG_SYS_OS_BASE (CONFIG_SYS_FLASH_BASE + \
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0x60000)
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#define CONFIG_SYS_FDT_BASE (CONFIG_SYS_FLASH_BASE + \
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0x40000)
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#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_TEXT_BASE + \
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0x1000000)
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/* SP location before relocation, must use scratch RAM */
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/* BRAM start */
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#define CONFIG_SYS_INIT_RAM_ADDR 0x0
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/* BRAM size - will be generated */
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#define CONFIG_SYS_INIT_RAM_SIZE 0x10000
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/* Stack pointer prior relocation, must situated at on-chip RAM */
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#define CONFIG_SYS_SPL_MALLOC_END (CONFIG_SYS_INIT_RAM_ADDR + \
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CONFIG_SYS_INIT_RAM_SIZE - \
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GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100
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/*
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* The main reason to do it in this way is that MALLOC_START
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* can't be defined - common/spl/spl.c
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*/
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#if (CONFIG_SYS_SPL_MALLOC_SIZE != 0)
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# define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_SPL_MALLOC_END - \
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CONFIG_SYS_SPL_MALLOC_SIZE)
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# define CONFIG_SPL_STACK_ADDR CONFIG_SYS_SPL_MALLOC_START
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#else
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# define CONFIG_SPL_STACK_ADDR CONFIG_SYS_SPL_MALLOC_END
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#endif
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/* Just for sure that there is a space for stack */
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#define CONFIG_SPL_STACK_SIZE 0x100
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#define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_FLASH_BASE
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#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
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#define CONFIG_SPL_MAX_FOOTPRINT (CONFIG_SYS_INIT_RAM_SIZE - \
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CONFIG_SYS_INIT_RAM_ADDR - \
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GENERATED_GBL_DATA_SIZE - \
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CONFIG_SYS_SPL_MALLOC_SIZE - \
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CONFIG_SPL_STACK_SIZE)
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#endif /* __CONFIG_H */
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