mirror of
https://github.com/Fishwaldo/u-boot.git
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Coding style cleanup. Update CHANGELOG.
Signed-off-by: Wolfgang Denk <wd@denx.de>
This commit is contained in:
Wolfgang Denk
parent
221838cc7e
commit
9c7e4b0621
16 changed files with 6441 additions and 6403 deletions
61
CHANGELOG
61
CHANGELOG
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@ -1,3 +1,64 @@
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commit 221838cc7eb178370ff62aa05920a582e12ac322
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Author: Jason Jin <Jason.jin@freescale.com>
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Date: Tue Jul 10 09:03:22 2007 +0800
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Remove the bios emulator from MAI board.
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The bios emulator in the MAI board can not pass compile
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and have a lot of crap in it. remove it and will have a
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clean and small bios emulator in the drivers directory
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which can be uesed for every board.
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Signed-off-by: Jason Jin <Jason.jin@freescale.com>
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commit 5618332409bb96f4448d1712899369fc80c0b489
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Author: Jason Jin <Jason.jin@freescale.com>
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Date: Fri Jul 13 12:14:59 2007 +0800
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Fix some compile issues for MAI board.
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Signed-off-by: Jason Jin <Jason.jin@freescale.com>
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commit 0f460a1ee148b648ee242c3157650287d4296260
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Author: Jason Jin <Jason.jin@freescale.com>
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Date: Fri Jul 13 12:14:58 2007 +0800
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Configurations for ATI video card BIOS emulator
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This patch add definition of the BIOS emulator and the ATI framebuffer
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driver for MPC8641HPCN board.
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Signed-off-by: Jason Jin <Jason.jin@freescale.com>
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Signed-off-by: Zhang Wei <wei.zhang@freescale.com>
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commit ece92f85053b8df613edcf05b26a416cbc3d629c
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Author: Jason Jin <Jason.jin@freescale.com>
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Date: Fri Jul 6 08:34:56 2007 +0800
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This is a BIOS emulator, porting from SciTech for u-boot, mainly for
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ATI video card BIOS. and can be used for x86 code emulation by some
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modifications.
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Signed-off-by: Jason Jin <Jason.jin@freescale.com>
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commit 5072188acabde3178fac7f5a597150e6e74fd40c
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Author: Jason Jin <Jason.jin@freescale.com>
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Date: Fri Jul 6 08:33:33 2007 +0800
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This is a framebuffer driver for ATI video card, can work for PCI9200,
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X300, X700, X800 ATI video cards.
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Signed-off-by: Zhang Wei <wei.zhang@freescale.com>
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Signed-off-by: Jason Jin <Jason.jin@freescale.com>
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commit 5728be389e65fd47f34b33c2596271eb4db751ae
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Author: Wolfgang Denk <wd@denx.de>
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Date: Mon Aug 6 01:01:49 2007 +0200
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Coding style cleanup. Update CHANGELOG.
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Signed-off-by: Wolfgang Denk <wd@denx.de>
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commit 8092fef4c29b395958bb649647da7e3775731517
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Author: Martin Krause <Martin.Krause@tqs.de>
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Date: Tue Dec 12 14:26:01 2006 +0100
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@ -209,4 +209,3 @@
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#define PCI_CHIP_R423_5D57 0x5D57
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#define PCI_CHIP_RS350_7834 0x7834
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#define PCI_CHIP_RS350_7835 0x7835
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@ -5,7 +5,6 @@
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* Most of the definitions here are adapted right from XFree86 *
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***************************************************************/
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/*
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* Chip families. Must fit in the low 16 bits of a long word
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*/
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@ -38,14 +37,12 @@ enum radeon_family {
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((rinfo)->family == CHIP_FAMILY_RV280) || \
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((rinfo)->family == CHIP_FAMILY_RS300))
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#define IS_R300_VARIANT(rinfo) (((rinfo)->family == CHIP_FAMILY_R300) || \
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((rinfo)->family == CHIP_FAMILY_RV350) || \
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((rinfo)->family == CHIP_FAMILY_R350) || \
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((rinfo)->family == CHIP_FAMILY_RV380) || \
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((rinfo)->family == CHIP_FAMILY_R420))
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struct radeonfb_info {
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char name[20];
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@ -86,7 +83,6 @@ static inline void _OUTREGP(struct radeonfb_info *rinfo, u32 addr,
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#define OUTREGP(addr,val,mask) _OUTREGP(rinfo, addr, val,mask)
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/*
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* 2D Engine helper routines
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*/
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@ -106,7 +102,6 @@ static inline void radeon_engine_flush (struct radeonfb_info *rinfo)
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printf("radeonfb: Flush Timeout !\n");
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}
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static inline void _radeon_fifo_wait(struct radeonfb_info *rinfo, int entries)
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{
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int i;
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@ -119,7 +114,6 @@ static inline void _radeon_fifo_wait(struct radeonfb_info *rinfo, int entries)
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printf("radeonfb: FIFO Timeout !\n");
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}
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static inline void _radeon_engine_idle(struct radeonfb_info *rinfo)
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{
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int i;
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@ -137,7 +131,6 @@ static inline void _radeon_engine_idle(struct radeonfb_info *rinfo)
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printf("radeonfb: Idle Timeout !\n");
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}
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#define radeon_engine_idle() _radeon_engine_idle(rinfo)
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#define radeon_fifo_wait(entries) _radeon_fifo_wait(rinfo,entries)
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#define radeon_msleep(ms) _radeon_msleep(rinfo,ms)
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@ -255,9 +248,9 @@ static inline u32 __INPLL(struct radeonfb_info *rinfo, u32 addr)
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u32 data;
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OUTREG8(CLOCK_CNTL_INDEX, addr & 0x0000003f);
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//radeon_pll_errata_after_index(rinfo);
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/* radeon_pll_errata_after_index(rinfo); */
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data = INREG(CLOCK_CNTL_DATA);
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//radeon_pll_errata_after_data(rinfo);
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/* radeon_pll_errata_after_data(rinfo); */
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return data;
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}
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@ -266,12 +259,11 @@ static inline void __OUTPLL(struct radeonfb_info *rinfo, unsigned int index,
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{
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OUTREG8(CLOCK_CNTL_INDEX, (index & 0x0000003f) | 0x00000080);
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//radeon_pll_errata_after_index(rinfo);
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/* radeon_pll_errata_after_index(rinfo); */
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OUTREG(CLOCK_CNTL_DATA, val);
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//radeon_pll_errata_after_data(rinfo);
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/* radeon_pll_errata_after_data(rinfo); */
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}
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static inline void __OUTPLLP(struct radeonfb_info *rinfo, unsigned int index,
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u32 val, u32 mask)
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{
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@ -283,11 +275,8 @@ static inline void __OUTPLLP(struct radeonfb_info *rinfo, unsigned int index,
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__OUTPLL(rinfo, index, tmp);
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}
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#define INPLL(addr) __INPLL(rinfo, addr)
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#define OUTPLL(index, val) __OUTPLL(rinfo, index, val)
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#define OUTPLLP(index, val, mask) __OUTPLLP(rinfo, index, val, mask)
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#endif
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@ -251,8 +251,7 @@ hardware does not support mapping the VGA I/O and memory (such as some
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PowerPC systems), we emulate the VGA so that the BIOS will still be able to
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set NonVGA display modes such as on ATI hardware.
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****************************************************************************/
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static u8 VGA_inpb(
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const int port)
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static u8 VGA_inpb (const int port)
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{
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u8 val = 0xff;
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@ -263,11 +262,10 @@ static u8 VGA_inpb(
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of an internal flip flop in the hardware. Hence we have
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to emulate that functionality in here. */
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if (_BE_env.flipFlop3C0 == 0) {
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/* Access 3C0 as index register*/
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/* Access 3C0 as index register */
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val = _BE_env.emu3C0;
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}
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else {
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/* Access 3C0 as data register*/
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} else {
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/* Access 3C0 as data register */
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if (_BE_env.emu3C0 < ATT_C)
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val = _BE_env.emu3C1[_BE_env.emu3C0];
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}
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@ -328,22 +326,19 @@ Performs an emulated write to one of the 8253 timer registers. For now
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we only emulate timer 0 which is the only timer that the BIOS code appears
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to use.
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****************************************************************************/
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static void VGA_outpb(
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int port,
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u8 val)
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static void VGA_outpb (int port, u8 val)
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{
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switch (port) {
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case 0x3C0:
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/* 3C0 has funky characteristics because it can act as either
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a data register or index register depending on the state
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of an internal flip flop in the hardware. Hence we have
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to emulate that functionality in here.*/
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to emulate that functionality in here. */
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if (_BE_env.flipFlop3C0 == 0) {
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/* Access 3C0 as index register*/
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/* Access 3C0 as index register */
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_BE_env.emu3C0 = val;
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}
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else {
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/* Access 3C0 as data register*/
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} else {
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/* Access 3C0 as data register */
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if (_BE_env.emu3C0 < ATT_C)
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_BE_env.emu3C1[_BE_env.emu3C0] = val;
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}
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@ -363,10 +358,12 @@ static void VGA_outpb(
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_BE_env.emu3C6 = val;
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break;
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case 0x3C7:
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_BE_env.emu3C7 = (int)val * 3;
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_BE_env.emu3C7 = (int) val *3;
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break;
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case 0x3C8:
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_BE_env.emu3C8 = (int)val * 3;
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_BE_env.emu3C8 = (int) val *3;
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break;
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case 0x3C9:
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if (_BE_env.emu3C8 < PAL_C)
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@ -139,4 +139,3 @@ u32 pop_long (void);
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#endif
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#endif /* __X86EMU_PRIM_OPS_H */
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@ -1121,7 +1121,6 @@ unsigned decode_rm10_address(
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return 0; /* SHOULD NOT HAPPEN */
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}
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/****************************************************************************
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PARAMETERS:
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mod - modifier
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@ -1143,6 +1142,3 @@ unsigned decode_rmXX_address(int mod, int rm)
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return decode_rm01_address(rm);
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return decode_rm10_address(rm);
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}
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@ -2443,4 +2443,3 @@ DB( if (CHECK_SP_ACCESS())
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M.x86.R_SP += 4;
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return res;
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}
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@ -90,7 +90,7 @@
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#define MEM_IO_OE_CNTL 0x018C
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#define MC_CHIP_IO_OE_CNTL_AB 0x018C
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#define MC_FB_LOCATION 0x0148
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//#define MC_FB_LOCATION 0x0188
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/* #define MC_FB_LOCATION 0x0188 */
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#define HOST_PATH_CNTL 0x0130
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#define MEM_VGA_WP_SEL 0x0038
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#define MEM_VGA_RP_SEL 0x003C
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@ -193,8 +193,8 @@
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#define FP_V_SYNC_STRT_WID 0x02C8
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#define AUX_WINDOW_HORZ_CNTL 0x02D8
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#define AUX_WINDOW_VERT_CNTL 0x02DC
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//#define DDA_CONFIG 0x02e0
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//#define DDA_ON_OFF 0x02e4
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/* #define DDA_CONFIG 0x02e0 */
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/* #define DDA_ON_OFF 0x02e4 */
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#define DVI_I2C_CNTL_1 0x02e4
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#define GRPH_BUFFER_CNTL 0x02F0
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#define GRPH2_BUFFER_CNTL 0x03F0
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@ -403,7 +403,7 @@
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#define VGA_DDA_ON_OFF 0x02ec
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#define TV_MASTER_CNTL 0x0800
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//#define BASE_CODE 0x0f0b
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/* #define BASE_CODE 0x0f0b */
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#define BIOS_0_SCRATCH 0x0010
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#define BIOS_1_SCRATCH 0x0014
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#define BIOS_2_SCRATCH 0x0018
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@ -572,7 +572,7 @@
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/* FP bit constants */
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#define FP_CRTC_H_TOTAL_MASK 0x000003ff
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#define FP_CRTC_H_TOTAL_MASK 000003ff
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#define FP_CRTC_H_DISP_MASK 0x01ff0000
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#define FP_CRTC_V_TOTAL_MASK 0x00000fff
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#define FP_CRTC_V_DISP_MASK 0x0fff0000
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@ -1000,7 +1000,7 @@
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/* PAD_CTLR_STRENGTH */
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#define PAD_MANUAL_OVERRIDE 0x80000000
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// pllCLK_PIN_CNTL
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/* pllCLK_PIN_CNTL */
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#define CLK_PIN_CNTL__OSC_EN_MASK 0x00000001L
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#define CLK_PIN_CNTL__OSC_EN 0x00000001L
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#define CLK_PIN_CNTL__XTL_LOW_GAIN_MASK 0x00000004L
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@ -1026,7 +1026,7 @@
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#define CLK_PIN_CNTL__XTALIN_ALWAYS_ONb 0x00080000L
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#define CLK_PIN_CNTL__PWRSEQ_DELAY_MASK 0xff000000L
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// pllCLK_PWRMGT_CNTL
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/* pllCLK_PWRMGT_CNTL */
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#define CLK_PWRMGT_CNTL__MPLL_PWRMGT_OFF__SHIFT 0x00000000
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#define CLK_PWRMGT_CNTL__SPLL_PWRMGT_OFF__SHIFT 0x00000001
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#define CLK_PWRMGT_CNTL__PPLL_PWRMGT_OFF__SHIFT 0x00000002
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@ -1051,7 +1051,7 @@
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#define CLK_PWRMGT_CNTL__TVPLL_PWRMGT_OFF__SHIFT 0x0000001e
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#define CLK_PWRMGT_CNTL__TVCLK_TURNOFF__SHIFT 0x0000001f
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// pllP2PLL_CNTL
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/* pllP2PLL_CNTL */
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#define P2PLL_CNTL__P2PLL_RESET_MASK 0x00000001L
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#define P2PLL_CNTL__P2PLL_RESET 0x00000001L
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#define P2PLL_CNTL__P2PLL_SLEEP_MASK 0x00000002L
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@ -1076,7 +1076,7 @@
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#define P2PLL_CNTL__P2PLL_DISABLE_AUTO_RESET_MASK 0x00080000L
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#define P2PLL_CNTL__P2PLL_DISABLE_AUTO_RESET 0x00080000L
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// pllPIXCLKS_CNTL
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/* pllPIXCLKS_CNTL */
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#define PIXCLKS_CNTL__PIX2CLK_SRC_SEL__SHIFT 0x00000000
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#define PIXCLKS_CNTL__PIX2CLK_INVERT__SHIFT 0x00000004
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#define PIXCLKS_CNTL__PIX2CLK_SRC_INVERT__SHIFT 0x00000005
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|
@ -1090,7 +1090,7 @@
|
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#define PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb__SHIFT 0x0000000f
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// pllPIXCLKS_CNTL
|
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/* pllPIXCLKS_CNTL */
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#define PIXCLKS_CNTL__PIX2CLK_SRC_SEL_MASK 0x00000003L
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#define PIXCLKS_CNTL__PIX2CLK_INVERT 0x00000010L
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#define PIXCLKS_CNTL__PIX2CLK_SRC_INVERT 0x00000020L
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|
@ -1112,7 +1112,7 @@
|
|||
#define PIXCLKS_CNTL__R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF (1 << 23)
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|
||||
|
||||
// pllP2PLL_DIV_0
|
||||
/* pllP2PLL_DIV_0 */
|
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#define P2PLL_DIV_0__P2PLL_FB_DIV_MASK 0x000007ffL
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||||
#define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_W_MASK 0x00008000L
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#define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_W 0x00008000L
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|
@ -1120,7 +1120,7 @@
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|||
#define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_R 0x00008000L
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#define P2PLL_DIV_0__P2PLL_POST_DIV_MASK 0x00070000L
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||||
|
||||
// pllSCLK_CNTL
|
||||
/* pllSCLK_CNTL */
|
||||
#define SCLK_CNTL__SCLK_SRC_SEL_MASK 0x00000007L
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||||
#define SCLK_CNTL__CP_MAX_DYN_STOP_LAT 0x00000008L
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#define SCLK_CNTL__HDP_MAX_DYN_STOP_LAT 0x00000010L
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|
@ -1160,7 +1160,7 @@
|
|||
#define SCLK_CNTL__R300_FORCE_SU (1<<30)
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#define SCLK_CNTL__FORCEON_MASK 0xffff8000L
|
||||
|
||||
// pllSCLK_CNTL2
|
||||
/* pllSCLK_CNTL2 */
|
||||
#define SCLK_CNTL2__R300_TCL_MAX_DYN_STOP_LAT (1<<10)
|
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#define SCLK_CNTL2__R300_GA_MAX_DYN_STOP_LAT (1<<11)
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#define SCLK_CNTL2__R300_CBA_MAX_DYN_STOP_LAT (1<<12)
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|
|
@ -1168,7 +1168,7 @@
|
|||
#define SCLK_CNTL2__R300_FORCE_CBA (1<<14)
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#define SCLK_CNTL2__R300_FORCE_GA (1<<15)
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||||
|
||||
// SCLK_MORE_CNTL
|
||||
/* SCLK_MORE_CNTL */
|
||||
#define SCLK_MORE_CNTL__DISPREGS_MAX_DYN_STOP_LAT 0x00000001L
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||||
#define SCLK_MORE_CNTL__MC_GUI_MAX_DYN_STOP_LAT 0x00000002L
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||||
#define SCLK_MORE_CNTL__MC_HOST_MAX_DYN_STOP_LAT 0x00000004L
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|
@ -1188,7 +1188,7 @@
|
|||
#define SCLK_MORE_CNTL__CG_SPARE_RD_C_MASK 0xff000000L
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||||
#define SCLK_MORE_CNTL__FORCEON 0x00000700L
|
||||
|
||||
// MCLK_CNTL
|
||||
/* MCLK_CNTL */
|
||||
#define MCLK_CNTL__MCLKA_SRC_SEL_MASK 0x00000007L
|
||||
#define MCLK_CNTL__YCLKA_SRC_SEL_MASK 0x00000070L
|
||||
#define MCLK_CNTL__MCLKB_SRC_SEL_MASK 0x00000700L
|
||||
|
|
@ -1212,7 +1212,7 @@
|
|||
#define MCLK_CNTL__R300_DISABLE_MC_MCLKA (1 << 21)
|
||||
#define MCLK_CNTL__R300_DISABLE_MC_MCLKB (1 << 21)
|
||||
|
||||
// MCLK_MISC
|
||||
/* MCLK_MISC */
|
||||
#define MCLK_MISC__SCLK_SOURCED_FROM_MPLL_SEL_MASK 0x00000003L
|
||||
#define MCLK_MISC__MCLK_FROM_SPLL_DIV_SEL_MASK 0x00000004L
|
||||
#define MCLK_MISC__MCLK_FROM_SPLL_DIV_SEL 0x00000004L
|
||||
|
|
@ -1242,7 +1242,7 @@
|
|||
#define MCLK_MISC__TCLK_TO_YCLKB_EN 0x01000000L
|
||||
#define MCLK_MISC__CGM_SPARE_A_MASK 0x0e000000L
|
||||
|
||||
// VCLK_ECP_CNTL
|
||||
/* VCLK_ECP_CNTL */
|
||||
#define VCLK_ECP_CNTL__VCLK_SRC_SEL_MASK 0x00000003L
|
||||
#define VCLK_ECP_CNTL__VCLK_INVERT 0x00000010L
|
||||
#define VCLK_ECP_CNTL__PIXCLK_SRC_INVERT 0x00000020L
|
||||
|
|
@ -1253,7 +1253,7 @@
|
|||
#define VCLK_ECP_CNTL__SUBCLK_FORCE_ON 0x00080000L
|
||||
#define VCLK_ECP_CNTL__R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF (1<<23)
|
||||
|
||||
// PLL_PWRMGT_CNTL
|
||||
/* PLL_PWRMGT_CNTL */
|
||||
#define PLL_PWRMGT_CNTL__MPLL_TURNOFF_MASK 0x00000001L
|
||||
#define PLL_PWRMGT_CNTL__MPLL_TURNOFF 0x00000001L
|
||||
#define PLL_PWRMGT_CNTL__SPLL_TURNOFF_MASK 0x00000002L
|
||||
|
|
@ -1287,7 +1287,7 @@
|
|||
#define PLL_PWRMGT_CNTL__TCL_CLOCK_ACTIVE_RD 0x00200000L
|
||||
#define PLL_PWRMGT_CNTL__CG_NO2_DEBUG_MASK 0xff000000L
|
||||
|
||||
// CLK_PWRMGT_CNTL
|
||||
/* CLK_PWRMGT_CNTL */
|
||||
#define CLK_PWRMGT_CNTL__MPLL_PWRMGT_OFF_MASK 0x00000001L
|
||||
#define CLK_PWRMGT_CNTL__MPLL_PWRMGT_OFF 0x00000001L
|
||||
#define CLK_PWRMGT_CNTL__SPLL_PWRMGT_OFF_MASK 0x00000002L
|
||||
|
|
@ -1332,7 +1332,7 @@
|
|||
#define CLK_PWRMGT_CNTL__TVCLK_TURNOFF_MASK 0x80000000L
|
||||
#define CLK_PWRMGT_CNTL__TVCLK_TURNOFF 0x80000000L
|
||||
|
||||
// BUS_CNTL1
|
||||
/* BUS_CNTL1 */
|
||||
#define BUS_CNTL1__PMI_IO_DISABLE_MASK 0x00000001L
|
||||
#define BUS_CNTL1__PMI_IO_DISABLE 0x00000001L
|
||||
#define BUS_CNTL1__PMI_MEM_DISABLE_MASK 0x00000002L
|
||||
|
|
@ -1356,7 +1356,7 @@
|
|||
#define BUS_CNTL1__AGPCLK_VALID_MASK 0x80000000L
|
||||
#define BUS_CNTL1__AGPCLK_VALID 0x80000000L
|
||||
|
||||
// BUS_CNTL1
|
||||
/* BUS_CNTL1 */
|
||||
#define BUS_CNTL1__PMI_IO_DISABLE__SHIFT 0x00000000
|
||||
#define BUS_CNTL1__PMI_MEM_DISABLE__SHIFT 0x00000001
|
||||
#define BUS_CNTL1__PMI_BM_DISABLE__SHIFT 0x00000002
|
||||
|
|
@ -1370,7 +1370,7 @@
|
|||
#define BUS_CNTL1__SEND_SBA_LATENCY__SHIFT 0x0000001c
|
||||
#define BUS_CNTL1__AGPCLK_VALID__SHIFT 0x0000001f
|
||||
|
||||
// CRTC_OFFSET_CNTL
|
||||
/* CRTC_OFFSET_CNTL */
|
||||
#define CRTC_OFFSET_CNTL__CRTC_TILE_LINE_MASK 0x0000000fL
|
||||
#define CRTC_OFFSET_CNTL__CRTC_TILE_LINE_RIGHT_MASK 0x000000f0L
|
||||
#define CRTC_OFFSET_CNTL__CRTC_TILE_EN_RIGHT_MASK 0x00004000L
|
||||
|
|
@ -1395,7 +1395,7 @@
|
|||
#define CRTC_OFFSET_CNTL__CRTC_OFFSET_LOCK_MASK 0x80000000L
|
||||
#define CRTC_OFFSET_CNTL__CRTC_OFFSET_LOCK 0x80000000L
|
||||
|
||||
// CRTC_GEN_CNTL
|
||||
/* CRTC_GEN_CNTL */
|
||||
#define CRTC_GEN_CNTL__CRTC_DBL_SCAN_EN_MASK 0x00000001L
|
||||
#define CRTC_GEN_CNTL__CRTC_DBL_SCAN_EN 0x00000001L
|
||||
#define CRTC_GEN_CNTL__CRTC_INTERLACE_EN_MASK 0x00000002L
|
||||
|
|
@ -1416,7 +1416,7 @@
|
|||
#define CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B_MASK 0x04000000L
|
||||
#define CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B 0x04000000L
|
||||
|
||||
// CRTC2_GEN_CNTL
|
||||
/* CRTC2_GEN_CNTL */
|
||||
#define CRTC2_GEN_CNTL__CRTC2_DBL_SCAN_EN_MASK 0x00000001L
|
||||
#define CRTC2_GEN_CNTL__CRTC2_DBL_SCAN_EN 0x00000001L
|
||||
#define CRTC2_GEN_CNTL__CRTC2_INTERLACE_EN_MASK 0x00000002L
|
||||
|
|
@ -1448,7 +1448,7 @@
|
|||
#define CRTC2_GEN_CNTL__CRTC2_VSYNC_DIS_MASK 0x20000000L
|
||||
#define CRTC2_GEN_CNTL__CRTC2_VSYNC_DIS 0x20000000L
|
||||
|
||||
// AGP_CNTL
|
||||
/* AGP_CNTL */
|
||||
#define AGP_CNTL__MAX_IDLE_CLK_MASK 0x000000ffL
|
||||
#define AGP_CNTL__HOLD_RD_FIFO_MASK 0x00000100L
|
||||
#define AGP_CNTL__HOLD_RD_FIFO 0x00000100L
|
||||
|
|
@ -1488,7 +1488,7 @@
|
|||
#define AGP_CNTL__DELAY_FIRST_SBA_VAL_MASK 0x38000000L
|
||||
#define AGP_CNTL__AGP_MISC_MASK 0xc0000000L
|
||||
|
||||
// AGP_CNTL
|
||||
/* AGP_CNTL */
|
||||
#define AGP_CNTL__MAX_IDLE_CLK__SHIFT 0x00000000
|
||||
#define AGP_CNTL__HOLD_RD_FIFO__SHIFT 0x00000008
|
||||
#define AGP_CNTL__HOLD_RQ_FIFO__SHIFT 0x00000009
|
||||
|
|
@ -1511,7 +1511,7 @@
|
|||
#define AGP_CNTL__DELAY_FIRST_SBA_VAL__SHIFT 0x0000001b
|
||||
#define AGP_CNTL__AGP_MISC__SHIFT 0x0000001e
|
||||
|
||||
// DISP_MISC_CNTL
|
||||
/* DISP_MISC_CNTL */
|
||||
#define DISP_MISC_CNTL__SOFT_RESET_GRPH_PP_MASK 0x00000001L
|
||||
#define DISP_MISC_CNTL__SOFT_RESET_GRPH_PP 0x00000001L
|
||||
#define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_PP_MASK 0x00000002L
|
||||
|
|
@ -1543,7 +1543,7 @@
|
|||
#define DISP_MISC_CNTL__PALETTE_MEM_RD_MARGIN_MASK 0x0f000000L
|
||||
#define DISP_MISC_CNTL__RMX_BUF_MEM_RD_MARGIN_MASK 0xf0000000L
|
||||
|
||||
// DISP_PWR_MAN
|
||||
/* DISP_PWR_MAN */
|
||||
#define DISP_PWR_MAN__DISP_PWR_MAN_D3_CRTC_EN_MASK 0x00000001L
|
||||
#define DISP_PWR_MAN__DISP_PWR_MAN_D3_CRTC_EN 0x00000001L
|
||||
#define DISP_PWR_MAN__DISP2_PWR_MAN_D3_CRTC2_EN_MASK 0x00000010L
|
||||
|
|
@ -1572,15 +1572,15 @@
|
|||
#define DISP_PWR_MAN__AUTO_PWRUP_EN_MASK 0x04000000L
|
||||
#define DISP_PWR_MAN__AUTO_PWRUP_EN 0x04000000L
|
||||
|
||||
// MC_IND_INDEX
|
||||
/* MC_IND_INDEX */
|
||||
#define MC_IND_INDEX__MC_IND_ADDR_MASK 0x0000001fL
|
||||
#define MC_IND_INDEX__MC_IND_WR_EN_MASK 0x00000100L
|
||||
#define MC_IND_INDEX__MC_IND_WR_EN 0x00000100L
|
||||
|
||||
// MC_IND_DATA
|
||||
/* MC_IND_DATA */
|
||||
#define MC_IND_DATA__MC_IND_DATA_MASK 0xffffffffL
|
||||
|
||||
// MC_CHP_IO_CNTL_A1
|
||||
/* MC_CHP_IO_CNTL_A1 */
|
||||
#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_CKA__SHIFT 0x00000000
|
||||
#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_AA__SHIFT 0x00000001
|
||||
#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQMA__SHIFT 0x00000002
|
||||
|
|
@ -1605,7 +1605,7 @@
|
|||
#define MC_CHP_IO_CNTL_A1__MEM_DATA_ENIMP_A__SHIFT 0x0000001e
|
||||
#define MC_CHP_IO_CNTL_A1__MEM_CNTL_ENIMP_A__SHIFT 0x0000001f
|
||||
|
||||
// MC_CHP_IO_CNTL_B1
|
||||
/* MC_CHP_IO_CNTL_B1 */
|
||||
#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_CKB__SHIFT 0x00000000
|
||||
#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_AB__SHIFT 0x00000001
|
||||
#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQMB__SHIFT 0x00000002
|
||||
|
|
@ -1630,7 +1630,7 @@
|
|||
#define MC_CHP_IO_CNTL_B1__MEM_DATA_ENIMP_B__SHIFT 0x0000001e
|
||||
#define MC_CHP_IO_CNTL_B1__MEM_CNTL_ENIMP_B__SHIFT 0x0000001f
|
||||
|
||||
// MC_CHP_IO_CNTL_A1
|
||||
/* MC_CHP_IO_CNTL_A1 */
|
||||
#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_CKA_MASK 0x00000001L
|
||||
#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_CKA 0x00000001L
|
||||
#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_AA_MASK 0x00000002L
|
||||
|
|
@ -1671,7 +1671,7 @@
|
|||
#define MC_CHP_IO_CNTL_A1__MEM_CNTL_ENIMP_A_MASK 0x80000000L
|
||||
#define MC_CHP_IO_CNTL_A1__MEM_CNTL_ENIMP_A 0x80000000L
|
||||
|
||||
// MC_CHP_IO_CNTL_B1
|
||||
/* MC_CHP_IO_CNTL_B1 */
|
||||
#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_CKB_MASK 0x00000001L
|
||||
#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_CKB 0x00000001L
|
||||
#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_AB_MASK 0x00000002L
|
||||
|
|
@ -1712,7 +1712,7 @@
|
|||
#define MC_CHP_IO_CNTL_B1__MEM_CNTL_ENIMP_B_MASK 0x80000000L
|
||||
#define MC_CHP_IO_CNTL_B1__MEM_CNTL_ENIMP_B 0x80000000L
|
||||
|
||||
// MEM_SDRAM_MODE_REG
|
||||
/* MEM_SDRAM_MODE_REG */
|
||||
#define MEM_SDRAM_MODE_REG__MEM_MODE_REG_MASK 0x00007fffL
|
||||
#define MEM_SDRAM_MODE_REG__MEM_WR_LATENCY_MASK 0x000f0000L
|
||||
#define MEM_SDRAM_MODE_REG__MEM_CAS_LATENCY_MASK 0x00700000L
|
||||
|
|
@ -1735,7 +1735,7 @@
|
|||
#define MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET_MASK 0x80000000L
|
||||
#define MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET 0x80000000L
|
||||
|
||||
// MEM_SDRAM_MODE_REG
|
||||
/* MEM_SDRAM_MODE_REG */
|
||||
#define MEM_SDRAM_MODE_REG__MEM_MODE_REG__SHIFT 0x00000000
|
||||
#define MEM_SDRAM_MODE_REG__MEM_WR_LATENCY__SHIFT 0x00000010
|
||||
#define MEM_SDRAM_MODE_REG__MEM_CAS_LATENCY__SHIFT 0x00000014
|
||||
|
|
@ -1749,7 +1749,7 @@
|
|||
#define MEM_SDRAM_MODE_REG__MEM_CFG_TYPE__SHIFT 0x0000001e
|
||||
#define MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET__SHIFT 0x0000001f
|
||||
|
||||
// MEM_REFRESH_CNTL
|
||||
/* MEM_REFRESH_CNTL */
|
||||
#define MEM_REFRESH_CNTL__MEM_REFRESH_RATE_MASK 0x000000ffL
|
||||
#define MEM_REFRESH_CNTL__MEM_REFRESH_DIS_MASK 0x00000100L
|
||||
#define MEM_REFRESH_CNTL__MEM_REFRESH_DIS 0x00000100L
|
||||
|
|
@ -1779,7 +1779,7 @@
|
|||
#define MEM_REFRESH_CNTL__MEM_CLKBFB_ENABLE 0x10000000L
|
||||
#define MEM_REFRESH_CNTL__DLL_FB_SLCT_CKB_MASK 0xc0000000L
|
||||
|
||||
// MC_STATUS
|
||||
/* MC_STATUS */
|
||||
#define MC_STATUS__MEM_PWRUP_COMPL_A_MASK 0x00000001L
|
||||
#define MC_STATUS__MEM_PWRUP_COMPL_A 0x00000001L
|
||||
#define MC_STATUS__MEM_PWRUP_COMPL_B_MASK 0x00000002L
|
||||
|
|
@ -1797,7 +1797,7 @@
|
|||
#define MC_STATUS__IMP_N_VALUE_CK_R_BACK_MASK 0x01e00000L
|
||||
#define MC_STATUS__IMP_P_VALUE_CK_R_BACK_MASK 0x1e000000L
|
||||
|
||||
// MDLL_CKO
|
||||
/* MDLL_CKO */
|
||||
#define MDLL_CKO__MCKOA_SLEEP_MASK 0x00000001L
|
||||
#define MDLL_CKO__MCKOA_SLEEP 0x00000001L
|
||||
#define MDLL_CKO__MCKOA_RESET_MASK 0x00000002L
|
||||
|
|
@ -1821,7 +1821,7 @@
|
|||
#define MDLL_CKO__MCKOB_BP_SEL_MASK 0x80000000L
|
||||
#define MDLL_CKO__MCKOB_BP_SEL 0x80000000L
|
||||
|
||||
// MDLL_RDCKA
|
||||
/* MDLL_RDCKA */
|
||||
#define MDLL_RDCKA__MRDCKA0_SLEEP_MASK 0x00000001L
|
||||
#define MDLL_RDCKA__MRDCKA0_SLEEP 0x00000001L
|
||||
#define MDLL_RDCKA__MRDCKA0_RESET_MASK 0x00000002L
|
||||
|
|
@ -1849,7 +1849,7 @@
|
|||
#define MDLL_RDCKA__MRDCKA1_BP_SEL_MASK 0x80000000L
|
||||
#define MDLL_RDCKA__MRDCKA1_BP_SEL 0x80000000L
|
||||
|
||||
// MDLL_RDCKB
|
||||
/* MDLL_RDCKB */
|
||||
#define MDLL_RDCKB__MRDCKB0_SLEEP_MASK 0x00000001L
|
||||
#define MDLL_RDCKB__MRDCKB0_SLEEP 0x00000001L
|
||||
#define MDLL_RDCKB__MRDCKB0_RESET_MASK 0x00000002L
|
||||
|
|
@ -1981,6 +1981,4 @@
|
|||
#define ixR300_MC_DLL_CNTL 0x002f
|
||||
#define NB_TOM 0x15C
|
||||
|
||||
|
||||
#endif /* _RADEON_H */
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue