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Merge branch 'master' of git://git.denx.de/u-boot-marvell
- Common: honour hw_margin_ms property (Rasmus) - sp805_wdt: get platform clock from dt (Rayagonda)
This commit is contained in:
commit
9cb3ce2558
3 changed files with 57 additions and 39 deletions
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@ -7,6 +7,7 @@
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#include <asm/io.h>
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#include <common.h>
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#include <clk.h>
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#include <dm/device.h>
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#include <dm/fdtaddr.h>
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#include <dm/read.h>
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@ -34,6 +35,7 @@ DECLARE_GLOBAL_DATA_PTR;
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struct sp805_wdt_priv {
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void __iomem *reg;
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unsigned long clk_rate;
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};
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static int sp805_wdt_reset(struct udevice *dev)
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@ -63,8 +65,13 @@ static int sp805_wdt_start(struct udevice *dev, u64 timeout, ulong flags)
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* set 120s, the gd->bus_clk is less than 1145MHz, the load_value will
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* not overflow.
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*/
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load_value = (gd->bus_clk) /
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(2 * 1000 * SYS_FSL_WDT_CLK_DIV) * load_time;
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if (gd->bus_clk) {
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load_value = (gd->bus_clk) /
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(2 * 1000 * SYS_FSL_WDT_CLK_DIV) * load_time;
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} else {
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/* platform provide clk */
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load_value = (timeout / 2) * (priv->clk_rate / 1000);
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}
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writel(UNLOCK, priv->reg + WDTLOCK);
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writel(load_value, priv->reg + WDTLOAD);
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@ -105,11 +112,15 @@ static int sp805_wdt_probe(struct udevice *dev)
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static int sp805_wdt_ofdata_to_platdata(struct udevice *dev)
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{
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struct sp805_wdt_priv *priv = dev_get_priv(dev);
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struct clk clk;
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priv->reg = (void __iomem *)dev_read_addr(dev);
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if (IS_ERR(priv->reg))
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return PTR_ERR(priv->reg);
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if (!clk_get_by_index(dev, 0, &clk))
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priv->clk_rate = clk_get_rate(&clk);
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return 0;
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}
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@ -14,6 +14,48 @@
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DECLARE_GLOBAL_DATA_PTR;
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#define WATCHDOG_TIMEOUT_SECS (CONFIG_WATCHDOG_TIMEOUT_MSECS / 1000)
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/*
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* Reset every 1000ms, or however often is required as indicated by a
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* hw_margin_ms property.
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*/
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static ulong reset_period = 1000;
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int initr_watchdog(void)
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{
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u32 timeout = WATCHDOG_TIMEOUT_SECS;
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/*
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* Init watchdog: This will call the probe function of the
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* watchdog driver, enabling the use of the device
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*/
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if (uclass_get_device_by_seq(UCLASS_WDT, 0,
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(struct udevice **)&gd->watchdog_dev)) {
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debug("WDT: Not found by seq!\n");
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if (uclass_get_device(UCLASS_WDT, 0,
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(struct udevice **)&gd->watchdog_dev)) {
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printf("WDT: Not found!\n");
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return 0;
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}
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}
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if (CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)) {
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timeout = dev_read_u32_default(gd->watchdog_dev, "timeout-sec",
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WATCHDOG_TIMEOUT_SECS);
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reset_period = dev_read_u32_default(gd->watchdog_dev,
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"hw_margin_ms",
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4 * reset_period) / 4;
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}
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wdt_start(gd->watchdog_dev, timeout * 1000, 0);
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gd->flags |= GD_FLG_WDT_READY;
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printf("WDT: Started with%s servicing (%ds timeout)\n",
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IS_ENABLED(CONFIG_WATCHDOG) ? "" : "out", timeout);
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return 0;
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}
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int wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags)
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{
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const struct wdt_ops *ops = device_get_ops(dev);
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@ -85,7 +127,7 @@ void watchdog_reset(void)
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/* Do not reset the watchdog too often */
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now = get_timer(0);
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if (time_after(now, next_reset)) {
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next_reset = now + 1000; /* reset every 1000ms */
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next_reset = now + reset_period;
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wdt_reset(gd->watchdog_dev);
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}
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}
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@ -106,41 +106,6 @@ struct wdt_ops {
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int (*expire_now)(struct udevice *dev, ulong flags);
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};
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#if CONFIG_IS_ENABLED(WDT)
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#ifndef CONFIG_WATCHDOG_TIMEOUT_MSECS
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#define CONFIG_WATCHDOG_TIMEOUT_MSECS (60 * 1000)
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#endif
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#define WATCHDOG_TIMEOUT_SECS (CONFIG_WATCHDOG_TIMEOUT_MSECS / 1000)
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static inline int initr_watchdog(void)
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{
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u32 timeout = WATCHDOG_TIMEOUT_SECS;
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/*
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* Init watchdog: This will call the probe function of the
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* watchdog driver, enabling the use of the device
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*/
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if (uclass_get_device_by_seq(UCLASS_WDT, 0,
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(struct udevice **)&gd->watchdog_dev)) {
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debug("WDT: Not found by seq!\n");
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if (uclass_get_device(UCLASS_WDT, 0,
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(struct udevice **)&gd->watchdog_dev)) {
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printf("WDT: Not found!\n");
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return 0;
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}
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}
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if (CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)) {
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timeout = dev_read_u32_default(gd->watchdog_dev, "timeout-sec",
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WATCHDOG_TIMEOUT_SECS);
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}
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wdt_start(gd->watchdog_dev, timeout * 1000, 0);
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gd->flags |= GD_FLG_WDT_READY;
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printf("WDT: Started with%s servicing (%ds timeout)\n",
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IS_ENABLED(CONFIG_WATCHDOG) ? "" : "out", timeout);
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return 0;
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}
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#endif
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int initr_watchdog(void);
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#endif /* _WDT_H_ */
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