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Merge branch 'master' of git://git.denx.de/u-boot-i2c

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This commit is contained in:
Tom Rini 2013-10-17 12:09:49 -04:00
commit 9dff87a297
28 changed files with 1187 additions and 308 deletions
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31
README
View file

@ -1994,15 +1994,40 @@ CBFS (Coreboot Filesystem) support
second bus.
- drivers/i2c/tegra_i2c.c:
- activate this driver with CONFIG_SYS_I2C_TEGRA
- This driver adds 4 i2c buses with a fix speed from
100000 and the slave addr 0!
- activate this driver with CONFIG_SYS_I2C_TEGRA
- This driver adds 4 i2c buses with a fix speed from
100000 and the slave addr 0!
- drivers/i2c/ppc4xx_i2c.c
- activate this driver with CONFIG_SYS_I2C_PPC4XX
- CONFIG_SYS_I2C_PPC4XX_CH0 activate hardware channel 0
- CONFIG_SYS_I2C_PPC4XX_CH1 activate hardware channel 1
- drivers/i2c/i2c_mxc.c
- activate this driver with CONFIG_SYS_I2C_MXC
- define speed for bus 1 with CONFIG_SYS_MXC_I2C1_SPEED
- define slave for bus 1 with CONFIG_SYS_MXC_I2C1_SLAVE
- define speed for bus 2 with CONFIG_SYS_MXC_I2C2_SPEED
- define slave for bus 2 with CONFIG_SYS_MXC_I2C2_SLAVE
- define speed for bus 3 with CONFIG_SYS_MXC_I2C3_SPEED
- define slave for bus 3 with CONFIG_SYS_MXC_I2C3_SLAVE
If thoses defines are not set, default value is 100000
for speed, and 0 for slave.
- drivers/i2c/rcar_i2c.c:
- activate this driver with CONFIG_SYS_I2C_RCAR
- This driver adds 4 i2c buses
- CONFIG_SYS_RCAR_I2C0_BASE for setting the register channel 0
- CONFIG_SYS_RCAR_I2C0_SPEED for for the speed channel 0
- CONFIG_SYS_RCAR_I2C1_BASE for setting the register channel 1
- CONFIG_SYS_RCAR_I2C1_SPEED for for the speed channel 1
- CONFIG_SYS_RCAR_I2C2_BASE for setting the register channel 2
- CONFIG_SYS_RCAR_I2C2_SPEED for for the speed channel 2
- CONFIG_SYS_RCAR_I2C3_BASE for setting the register channel 3
- CONFIG_SYS_RCAR_I2C3_SPEED for for the speed channel 3
- CONFIF_SYS_RCAR_I2C_NUM_CONTROLLERS for number of i2c buses
additional defines:
CONFIG_SYS_NUM_I2C_BUSES

2
arch/arm/cpu/armv7/mx5/clock.c
View file

@ -94,7 +94,7 @@ void enable_usboh3_clk(bool enable)
MXC_CCM_CCGR2_USBOH3_60M(cg));
}
#ifdef CONFIG_I2C_MXC
#ifdef CONFIG_SYS_I2C_MXC
/* i2c_num can be from 0, to 1 for i.MX51 and 2 for i.MX53 */
int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
{

2
arch/arm/cpu/armv7/mx6/clock.c
View file

@ -48,7 +48,7 @@ void enable_usboh3_clk(unsigned char enable)
}
#ifdef CONFIG_I2C_MXC
#ifdef CONFIG_SYS_I2C_MXC
/* i2c_num can be from 0 - 2 */
int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
{

2
arch/arm/imx-common/Makefile
View file

@ -16,7 +16,7 @@ COBJS-y = iomux-v3.o
endif
ifeq ($(SOC),$(filter $(SOC),mx5 mx6))
COBJS-y += timer.o cpu.o speed.o
COBJS-$(CONFIG_I2C_MXC) += i2c-mxv7.o
COBJS-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o
endif
ifeq ($(SOC),$(filter $(SOC),mx6 mxs))
COBJS-y += misc.o

4
common/board_f.c
View file

@ -249,7 +249,11 @@ void dram_init_banksize(void)
static int init_func_i2c(void)
{
puts("I2C: ");
#ifdef CONFIG_SYS_I2C
i2c_init_all();
#else
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
#endif
puts("ready\n");
return 0;
}

3
drivers/i2c/Makefile
View file

@ -14,7 +14,6 @@ COBJS-$(CONFIG_DRIVER_DAVINCI_I2C) += davinci_i2c.o
COBJS-$(CONFIG_DW_I2C) += designware_i2c.o
COBJS-$(CONFIG_I2C_MVTWSI) += mvtwsi.o
COBJS-$(CONFIG_I2C_MV) += mv_i2c.o
COBJS-$(CONFIG_I2C_MXC) += mxc_i2c.o
COBJS-$(CONFIG_I2C_MXS) += mxs_i2c.o
COBJS-$(CONFIG_DRIVER_OMAP1510_I2C) += omap1510_i2c.o
COBJS-$(CONFIG_DRIVER_OMAP24XX_I2C) += omap24xx_i2c.o
@ -28,7 +27,9 @@ COBJS-$(CONFIG_SH_SH7734_I2C) += sh_sh7734_i2c.o
COBJS-$(CONFIG_SYS_I2C) += i2c_core.o
COBJS-$(CONFIG_SYS_I2C_FSL) += fsl_i2c.o
COBJS-$(CONFIG_SYS_I2C_FTI2C010) += fti2c010.o
COBJS-$(CONFIG_SYS_I2C_MXC) += mxc_i2c.o
COBJS-$(CONFIG_SYS_I2C_PPC4XX) += ppc4xx_i2c.o
COBJS-$(CONFIG_SYS_I2C_RCAR) += rcar_i2c.o
COBJS-$(CONFIG_SYS_I2C_SOFT) += soft_i2c.o
COBJS-$(CONFIG_SYS_I2C_TEGRA) += tegra_i2c.o
COBJS-$(CONFIG_ZYNQ_I2C) += zynq_i2c.o

39
drivers/i2c/i2c_core.c
View file

@ -53,32 +53,26 @@ void i2c_reloc_fixup(void)
return;
for (i = 0; i < max; i++) {
/* adapter itself */
addr = (unsigned long)i2c_adap_p;
addr += gd->reloc_off;
i2c_adap_p = (struct i2c_adapter *)addr;
/* i2c_init() */
addr = (unsigned long)i2c_adap_p->init;
addr += gd->reloc_off;
i2c_adap_p->init = (void (*)(int, int))addr;
i2c_adap_p->init = (void *)addr;
/* i2c_probe() */
addr = (unsigned long)i2c_adap_p->probe;
addr += gd->reloc_off;
i2c_adap_p->probe = (int (*)(uint8_t))addr;
i2c_adap_p->probe = (void *)addr;
/* i2c_read() */
addr = (unsigned long)i2c_adap_p->read;
addr += gd->reloc_off;
i2c_adap_p->read = (int (*)(uint8_t, uint, int, uint8_t *,
int))addr;
i2c_adap_p->read = (void *)addr;
/* i2c_write() */
addr = (unsigned long)i2c_adap_p->write;
addr += gd->reloc_off;
i2c_adap_p->write = (int (*)(uint8_t, uint, int, uint8_t *,
int))addr;
i2c_adap_p->write = (void *)addr;
/* i2c_set_bus_speed() */
addr = (unsigned long)i2c_adap_p->set_bus_speed;
addr += gd->reloc_off;
i2c_adap_p->set_bus_speed = (uint (*)(uint))addr;
i2c_adap_p->set_bus_speed = (void *)addr;
/* name */
addr = (unsigned long)i2c_adap_p->name;
addr += gd->reloc_off;
@ -138,6 +132,11 @@ static int i2c_mux_set(struct i2c_adapter *adap, int mux_id, int chip,
return -1;
buf = (uint8_t)((channel & 0x07) | (1 << 3));
break;
case I2C_MUX_PCA9548_ID:
if (channel > 7)
return -1;
buf = (uint8_t)(0x01 << channel);
break;
default:
printf("%s: wrong mux id: %d\n", __func__, mux_id);
return -1;
@ -278,20 +277,22 @@ unsigned int i2c_get_bus_num(void)
*/
int i2c_set_bus_num(unsigned int bus)
{
int max = ll_entry_count(struct i2c_adapter, i2c);
int max;
if ((bus == I2C_BUS) && (I2C_ADAP->init_done > 0))
return 0;
if (I2C_ADAPTER(bus) >= max) {
printf("Error, wrong i2c adapter %d max %d possible\n",
I2C_ADAPTER(bus), max);
return -2;
}
#ifndef CONFIG_SYS_I2C_DIRECT_BUS
if (bus >= CONFIG_SYS_NUM_I2C_BUSES)
return -1;
#endif
if ((bus == I2C_BUS) && (I2C_ADAP->init_done > 0))
return 0;
max = ll_entry_count(struct i2c_adapter, i2c);
if (I2C_ADAPTER(bus) >= max) {
printf("Error, wrong i2c adapter %d max %d possible\n",
I2C_ADAPTER(bus), max);
return -2;
}
#ifndef CONFIG_SYS_I2C_DIRECT_BUS
i2c_mux_disconnet_all();

137
drivers/i2c/mxc_i2c.c
View file

@ -102,6 +102,28 @@ static u16 i2c_clk_div[50][2] = {
};
#endif
#ifndef CONFIG_SYS_MXC_I2C1_SPEED
#define CONFIG_SYS_MXC_I2C1_SPEED 100000
#endif
#ifndef CONFIG_SYS_MXC_I2C2_SPEED
#define CONFIG_SYS_MXC_I2C2_SPEED 100000
#endif
#ifndef CONFIG_SYS_MXC_I2C3_SPEED
#define CONFIG_SYS_MXC_I2C3_SPEED 100000
#endif
#ifndef CONFIG_SYS_MXC_I2C1_SLAVE
#define CONFIG_SYS_MXC_I2C1_SLAVE 0
#endif
#ifndef CONFIG_SYS_MXC_I2C2_SLAVE
#define CONFIG_SYS_MXC_I2C2_SLAVE 0
#endif
#ifndef CONFIG_SYS_MXC_I2C3_SLAVE
#define CONFIG_SYS_MXC_I2C3_SLAVE 0
#endif
/*
* Calculate and set proper clock divider
*/
@ -153,21 +175,6 @@ static int bus_i2c_set_bus_speed(void *base, int speed)
return 0;
}
/*
* Get I2C Speed
*/
static unsigned int bus_i2c_get_bus_speed(void *base)
{
struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)base;
u8 clk_idx = readb(&i2c_regs->ifdr);
u8 clk_div;
for (clk_div = 0; i2c_clk_div[clk_div][1] != clk_idx; clk_div++)
;
return mxc_get_clock(MXC_I2C_CLK) / i2c_clk_div[clk_div][0];
}
#define ST_BUS_IDLE (0 | (I2SR_IBB << 8))
#define ST_BUS_BUSY (I2SR_IBB | (I2SR_IBB << 8))
#define ST_IIF (I2SR_IIF | (I2SR_IIF << 8))
@ -410,20 +417,30 @@ struct sram_data {
*/
static struct sram_data __attribute__((section(".data"))) srdata;
void *get_base(void)
{
#ifdef CONFIG_SYS_I2C_BASE
#ifdef CONFIG_I2C_MULTI_BUS
void *ret = srdata.i2c_data[srdata.curr_i2c_bus].base;
if (ret)
return ret;
#endif
return (void *)CONFIG_SYS_I2C_BASE;
#elif defined(CONFIG_I2C_MULTI_BUS)
return srdata.i2c_data[srdata.curr_i2c_bus].base;
static void * const i2c_bases[] = {
#if defined(CONFIG_MX25)
(void *)IMX_I2C_BASE,
(void *)IMX_I2C2_BASE,
(void *)IMX_I2C3_BASE
#elif defined(CONFIG_MX27)
(void *)IMX_I2C1_BASE,
(void *)IMX_I2C2_BASE
#elif defined(CONFIG_MX31) || defined(CONFIG_MX35) || \
defined(CONFIG_MX51) || defined(CONFIG_MX53) || \
defined(CONFIG_MX6)
(void *)I2C1_BASE_ADDR,
(void *)I2C2_BASE_ADDR,
(void *)I2C3_BASE_ADDR
#elif defined(CONFIG_VF610)
(void *)I2C0_BASE_ADDR
#else
return srdata.i2c_data[0].base;
#error "architecture not supported"
#endif
};
void *i2c_get_base(struct i2c_adapter *adap)
{
return i2c_bases[adap->hwadapnr];
}
static struct i2c_parms *i2c_get_parms(void *base)
@ -448,39 +465,26 @@ static int i2c_idle_bus(void *base)
return 0;
}
#ifdef CONFIG_I2C_MULTI_BUS
unsigned int i2c_get_bus_num(void)
static int mxc_i2c_read(struct i2c_adapter *adap, uint8_t chip,
uint addr, int alen, uint8_t *buffer,
int len)
{
return srdata.curr_i2c_bus;
return bus_i2c_read(i2c_get_base(adap), chip, addr, alen, buffer, len);
}
int i2c_set_bus_num(unsigned bus_idx)
static int mxc_i2c_write(struct i2c_adapter *adap, uint8_t chip,
uint addr, int alen, uint8_t *buffer,
int len)
{
if (bus_idx >= ARRAY_SIZE(srdata.i2c_data))
return -1;
if (!srdata.i2c_data[bus_idx].base)
return -1;
srdata.curr_i2c_bus = bus_idx;
return 0;
}
#endif
int i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len)
{
return bus_i2c_read(get_base(), chip, addr, alen, buf, len);
}
int i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len)
{
return bus_i2c_write(get_base(), chip, addr, alen, buf, len);
return bus_i2c_write(i2c_get_base(adap), chip, addr, alen, buffer, len);
}
/*
* Test if a chip at a given address responds (probe the chip)
*/
int i2c_probe(uchar chip)
static int mxc_i2c_probe(struct i2c_adapter *adap, uint8_t chip)
{
return bus_i2c_write(get_base(), chip, 0, 0, NULL, 0);
return bus_i2c_write(i2c_get_base(adap), chip, 0, 0, NULL, 0);
}
void bus_i2c_init(void *base, int speed, int unused,
@ -510,23 +514,38 @@ void bus_i2c_init(void *base, int speed, int unused,
/*
* Init I2C Bus
*/
void i2c_init(int speed, int unused)
static void mxc_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
{
bus_i2c_init(get_base(), speed, unused, NULL, NULL);
bus_i2c_init(i2c_get_base(adap), speed, slaveaddr, NULL, NULL);
}
/*
* Set I2C Speed
*/
int i2c_set_bus_speed(unsigned int speed)
static uint mxc_i2c_set_bus_speed(struct i2c_adapter *adap, uint speed)
{
return bus_i2c_set_bus_speed(get_base(), speed);
return bus_i2c_set_bus_speed(i2c_get_base(adap), speed);
}
/*
* Get I2C Speed
* Register mxc i2c adapters
*/
unsigned int i2c_get_bus_speed(void)
{
return bus_i2c_get_bus_speed(get_base());
}
U_BOOT_I2C_ADAP_COMPLETE(mxc0, mxc_i2c_init, mxc_i2c_probe,
mxc_i2c_read, mxc_i2c_write,
mxc_i2c_set_bus_speed,
CONFIG_SYS_MXC_I2C1_SPEED,
CONFIG_SYS_MXC_I2C1_SLAVE, 0)
U_BOOT_I2C_ADAP_COMPLETE(mxc1, mxc_i2c_init, mxc_i2c_probe,
mxc_i2c_read, mxc_i2c_write,
mxc_i2c_set_bus_speed,
CONFIG_SYS_MXC_I2C2_SPEED,
CONFIG_SYS_MXC_I2C2_SLAVE, 1)
#if defined(CONFIG_MX31) || defined(CONFIG_MX35) ||\
defined(CONFIG_MX51) || defined(CONFIG_MX53) ||\
defined(CONFIG_MX6)
U_BOOT_I2C_ADAP_COMPLETE(mxc2, mxc_i2c_init, mxc_i2c_probe,
mxc_i2c_read, mxc_i2c_write,
mxc_i2c_set_bus_speed,
CONFIG_SYS_MXC_I2C3_SPEED,
CONFIG_SYS_MXC_I2C3_SLAVE, 2)
#endif

288
drivers/i2c/rcar_i2c.c Normal file
View file

@ -0,0 +1,288 @@
/*
* drivers/i2c/rcar_i2c.c
*
* Copyright (C) 2013 Renesas Electronics Corporation
* Copyright (C) 2013 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
*
* SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
#include <i2c.h>
#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
struct rcar_i2c {
u32 icscr;
u32 icmcr;
u32 icssr;
u32 icmsr;
u32 icsier;
u32 icmier;
u32 icccr;
u32 icsar;
u32 icmar;
u32 icrxdtxd;
u32 icccr2;
u32 icmpr;
u32 ichpr;
u32 iclpr;
};
#define MCR_MDBS 0x80 /* non-fifo mode switch */
#define MCR_FSCL 0x40 /* override SCL pin */
#define MCR_FSDA 0x20 /* override SDA pin */
#define MCR_OBPC 0x10 /* override pins */
#define MCR_MIE 0x08 /* master if enable */
#define MCR_TSBE 0x04
#define MCR_FSB 0x02 /* force stop bit */
#define MCR_ESG 0x01 /* en startbit gen. */
#define MSR_MASK 0x7f
#define MSR_MNR 0x40 /* nack received */
#define MSR_MAL 0x20 /* arbitration lost */
#define MSR_MST 0x10 /* sent a stop */
#define MSR_MDE 0x08
#define MSR_MDT 0x04
#define MSR_MDR 0x02
#define MSR_MAT 0x01 /* slave addr xfer done */
static const struct rcar_i2c *i2c_dev[CONFIF_SYS_RCAR_I2C_NUM_CONTROLLERS] = {
(struct rcar_i2c *)CONFIG_SYS_RCAR_I2C0_BASE,
(struct rcar_i2c *)CONFIG_SYS_RCAR_I2C1_BASE,
(struct rcar_i2c *)CONFIG_SYS_RCAR_I2C2_BASE,
(struct rcar_i2c *)CONFIG_SYS_RCAR_I2C3_BASE,
};
static void rcar_i2c_raw_rw_common(struct rcar_i2c *dev, u8 chip, uint addr)
{
/* set slave address */
writel(chip << 1, &dev->icmar);
/* set register address */
writel(addr, &dev->icrxdtxd);
/* clear status */
writel(0, &dev->icmsr);
/* start master send */
writel(MCR_MDBS | MCR_MIE | MCR_ESG, &dev->icmcr);
while ((readl(&dev->icmsr) & (MSR_MAT | MSR_MDE))
!= (MSR_MAT | MSR_MDE))
udelay(10);
/* clear ESG */
writel(MCR_MDBS | MCR_MIE, &dev->icmcr);
/* start SCLclk */
writel(~(MSR_MAT | MSR_MDE), &dev->icmsr);
while (!(readl(&dev->icmsr) & MSR_MDE))
udelay(10);
}
static void rcar_i2c_raw_rw_finish(struct rcar_i2c *dev)
{
while (!(readl(&dev->icmsr) & MSR_MST))
udelay(10);
writel(0, &dev->icmcr);
}
static int
rcar_i2c_raw_write(struct rcar_i2c *dev, u8 chip, uint addr, u8 *val, int size)
{
rcar_i2c_raw_rw_common(dev, chip, addr);
/* set send date */
writel(*val, &dev->icrxdtxd);
/* start SCLclk */
writel(~MSR_MDE, &dev->icmsr);
while (!(readl(&dev->icmsr) & MSR_MDE))
udelay(10);
/* set stop condition */
writel(MCR_MDBS | MCR_MIE | MCR_FSB, &dev->icmcr);
/* start SCLclk */
writel(~MSR_MDE, &dev->icmsr);
rcar_i2c_raw_rw_finish(dev);
return 0;
}
static u8
rcar_i2c_raw_read(struct rcar_i2c *dev, u8 chip, uint addr)
{
u8 ret;
rcar_i2c_raw_rw_common(dev, chip, addr);
/* set slave address, receive */
writel((chip << 1) | 1, &dev->icmar);
/* start master receive */
writel(MCR_MDBS | MCR_MIE | MCR_ESG, &dev->icmcr);
while ((readl(&dev->icmsr) & (MSR_MAT | MSR_MDE))
!= (MSR_MAT | MSR_MDE))
udelay(10);
/* clear ESG */
writel(MCR_MDBS | MCR_MIE, &dev->icmcr);
/* prepare stop condition */
writel(MCR_MDBS | MCR_MIE | MCR_FSB, &dev->icmcr);
/* start SCLclk */
writel(~(MSR_MAT | MSR_MDR), &dev->icmsr);
while (!(readl(&dev->icmsr) & MSR_MDR))
udelay(10);
/* get receive data */
ret = (u8)readl(&dev->icrxdtxd);
/* start SCLclk */
writel(~MSR_MDR, &dev->icmsr);
rcar_i2c_raw_rw_finish(dev);
return ret;
}
/*
* SCL = iicck / (20 + SCGD * 8 + F[(ticf + tr + intd) * iicck])
* iicck : I2C internal clock < 20 MHz
* ticf : I2C SCL falling time: 35 ns
* tr : I2C SCL rising time: 200 ns
* intd : LSI internal delay: I2C0: 50 ns I2C1-3: 5
* F[n] : n rounded up to an integer
*/
static u32 rcar_clock_gen(int i2c_no, u32 bus_speed)
{
u32 iicck, f, scl, scgd;
u32 intd = 5;
int bit = 0, cdf_width = 3;
for (bit = 0; bit < (1 << cdf_width); bit++) {
iicck = CONFIG_HP_CLK_FREQ / (1 + bit);
if (iicck < 20000000)
break;
}
if (bit > (1 << cdf_width)) {
puts("rcar-i2c: Can not get CDF\n");
return 0;
}
if (i2c_no == 0)
intd = 50;
f = (35 + 200 + intd) * (iicck / 1000000000);
for (scgd = 0; scgd < 0x40; scgd++) {
scl = iicck / (20 + (scgd * 8) + f);
if (scl <= bus_speed)
break;
}
if (scgd > 0x40) {
puts("rcar-i2c: Can not get SDGB\n");
return 0;
}
debug("%s: scl: %d\n", __func__, scl);
debug("%s: bit %x\n", __func__, bit);
debug("%s: scgd %x\n", __func__, scgd);
debug("%s: iccr %x\n", __func__, (scgd << (cdf_width) | bit));
return scgd << (cdf_width) | bit;
}
static void
rcar_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
{
struct rcar_i2c *dev = (struct rcar_i2c *)i2c_dev[adap->hwadapnr];
u32 icccr = 0;
/* No i2c support prior to relocation */
if (!(gd->flags & GD_FLG_RELOC))
return;
/*
* reset slave mode.
* slave mode is not used on this driver
*/
writel(0, &dev->icsier);
writel(0, &dev->icsar);
writel(0, &dev->icscr);
writel(0, &dev->icssr);
/* reset master mode */
writel(0, &dev->icmier);
writel(0, &dev->icmcr);
writel(0, &dev->icmsr);
writel(0, &dev->icmar);
icccr = rcar_clock_gen(adap->hwadapnr, adap->speed);
if (icccr == 0)
puts("I2C: Init failed\n");
else
writel(icccr, &dev->icccr);
}
static int rcar_i2c_read(struct i2c_adapter *adap, uint8_t chip,
uint addr, int alen, u8 *data, int len)
{
struct rcar_i2c *dev = (struct rcar_i2c *)i2c_dev[adap->hwadapnr];
int i;
for (i = 0; i < len; i++)
data[i] = rcar_i2c_raw_read(dev, chip, addr + i);
return 0;
}
static int rcar_i2c_write(struct i2c_adapter *adap, uint8_t chip, uint addr,
int alen, u8 *data, int len)
{
struct rcar_i2c *dev = (struct rcar_i2c *)i2c_dev[adap->hwadapnr];
return rcar_i2c_raw_write(dev, chip, addr, data, len);
}
static int
rcar_i2c_probe(struct i2c_adapter *adap, u8 dev)
{
return rcar_i2c_read(adap, dev, 0, 0, NULL, 0);
}
static unsigned int rcar_i2c_set_bus_speed(struct i2c_adapter *adap,
unsigned int speed)
{
struct rcar_i2c *dev = (struct rcar_i2c *)i2c_dev[adap->hwadapnr];
u32 icccr;
int ret = 0;
rcar_i2c_raw_rw_finish(dev);
icccr = rcar_clock_gen(adap->hwadapnr, speed);
if (icccr == 0) {
puts("I2C: Init failed\n");
ret = -1;
} else {
writel(icccr, &dev->icccr);
}
return ret;
}
/*
* Register RCAR i2c adapters
*/
U_BOOT_I2C_ADAP_COMPLETE(rcar_0, rcar_i2c_init, rcar_i2c_probe, rcar_i2c_read,
rcar_i2c_write, rcar_i2c_set_bus_speed,
CONFIG_SYS_RCAR_I2C0_SPEED, 0, 0)
U_BOOT_I2C_ADAP_COMPLETE(rcar_1, rcar_i2c_init, rcar_i2c_probe, rcar_i2c_read,
rcar_i2c_write, rcar_i2c_set_bus_speed,
CONFIG_SYS_RCAR_I2C1_SPEED, 0, 1)
U_BOOT_I2C_ADAP_COMPLETE(rcar_2, rcar_i2c_init, rcar_i2c_probe, rcar_i2c_read,
rcar_i2c_write, rcar_i2c_set_bus_speed,
CONFIG_SYS_RCAR_I2C2_SPEED, 0, 2)
U_BOOT_I2C_ADAP_COMPLETE(rcar_3, rcar_i2c_init, rcar_i2c_probe, rcar_i2c_read,
rcar_i2c_write, rcar_i2c_set_bus_speed,
CONFIG_SYS_RCAR_I2C3_SPEED, 0, 3)

835
drivers/i2c/s3c24x0_i2c.c
View file

File diff suppressed because it is too large Load diff

38
drivers/i2c/s3c24x0_i2c.h
View file

@ -15,10 +15,48 @@ struct s3c24x0_i2c {
u32 iiclc;
};
struct exynos5_hsi2c {
u32 usi_ctl;
u32 usi_fifo_ctl;
u32 usi_trailing_ctl;
u32 usi_clk_ctl;
u32 usi_clk_slot;
u32 spi_ctl;
u32 uart_ctl;
u32 res1;
u32 usi_int_en;
u32 usi_int_stat;
u32 usi_modem_stat;
u32 usi_error_stat;
u32 usi_fifo_stat;
u32 usi_txdata;
u32 usi_rxdata;
u32 res2;
u32 usi_conf;
u32 usi_auto_conf;
u32 usi_timeout;
u32 usi_manual_cmd;
u32 usi_trans_status;
u32 usi_timing_hs1;
u32 usi_timing_hs2;
u32 usi_timing_hs3;
u32 usi_timing_fs1;
u32 usi_timing_fs2;
u32 usi_timing_fs3;
u32 usi_timing_sla;
u32 i2c_addr;
};
struct s3c24x0_i2c_bus {
bool active; /* port is active and available */
int node; /* device tree node */
int bus_num; /* i2c bus number */
struct s3c24x0_i2c *regs;
struct exynos5_hsi2c *hsregs;
int is_highspeed; /* High speed type, rather than I2C */
unsigned clock_frequency;
int id;
unsigned clk_cycle;
unsigned clk_div;
};
#endif /* _S3C24X0_I2C_H */

10
drivers/i2c/sh_i2c.c
View file

@ -1,6 +1,6 @@
/*
* Copyright (C) 2011 Renesas Solutions Corp.
* Copyright (C) 2011 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
* Copyright (C) 2011, 2013 Renesas Solutions Corp.
* Copyright (C) 2011, 2013 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
@ -8,6 +8,8 @@
#include <common.h>
#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
/* Every register is 32bit aligned, but only 8bits in size */
#define ureg(name) u8 name; u8 __pad_##name##0; u16 __pad_##name##1;
struct sh_i2c {
@ -240,6 +242,10 @@ void i2c_init(int speed, int slaveaddr)
{
int num, denom, tmp;
/* No i2c support prior to relocation */
if (!(gd->flags & GD_FLG_RELOC))
return;
#ifdef CONFIG_I2C_MULTI_BUS
current_bus = 0;
#endif

11
include/configs/apf27.h
View file

@ -321,11 +321,12 @@
*/
#ifdef CONFIG_CMD_I2C
#define CONFIG_HARD_I2C
#define CONFIG_I2C_MXC
#define CONFIG_SYS_I2C_BASE IMX_I2C1_BASE
#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
#define CONFIG_SYS_I2C_SLAVE 0x7F
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
#define CONFIG_SYS_MXC_I2C1_SPEED 100000 /* 100 kHz */
#define CONFIG_SYS_MXC_I2C1_SLAVE 0x7F
#define CONFIG_SYS_MXC_I2C2_SPEED 100000 /* 100 kHz */
#define CONFIG_SYS_MXC_I2C2_SLAVE 0x7F
#define CONFIG_SYS_I2C_NOPROBES { }
#ifdef CONFIG_CMD_EEPROM

9
include/configs/flea3.h
View file

@ -50,11 +50,10 @@
/*
* Hardware drivers
*/
#define CONFIG_HARD_I2C
#define CONFIG_I2C_MXC
#define CONFIG_SYS_I2C_BASE I2C3_BASE_ADDR
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_SYS_I2C_SLAVE 0xfe
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
#define CONFIG_SYS_SPD_BUS_NUM 2 /* I2C3 */
#define CONFIG_SYS_MXC_I2C3_SLAVE 0xfe
#define CONFIG_MXC_SPI
#define CONFIG_MXC_GPIO

7
include/configs/imx31_phycore.h
View file

@ -35,11 +35,10 @@
* Hardware drivers
*/
#define CONFIG_HARD_I2C
#define CONFIG_I2C_MXC
#define CONFIG_SYS_I2C_BASE I2C2_BASE_ADDR
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
#define CONFIG_SYS_SPD_BUS_NUM 1 /* I2C2 */
#define CONFIG_SYS_I2C_CLK_OFFSET I2C2_CLK_OFFSET
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_MXC_UART
#define CONFIG_MXC_UART_BASE UART1_BASE

7
include/configs/m53evk.h
View file

@ -161,10 +161,9 @@
* I2C
*/
#ifdef CONFIG_CMD_I2C
#define CONFIG_HARD_I2C
#define CONFIG_I2C_MXC
#define CONFIG_SYS_I2C_BASE I2C2_BASE_ADDR
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
#define CONFIG_SYS_SPD_BUS_NUM 1 /* I2C2 */
#endif
/*

7
include/configs/mx25pdk.h
View file

@ -111,10 +111,9 @@
/* I2C Configs */
#define CONFIG_CMD_I2C
#define CONFIG_HARD_I2C
#define CONFIG_I2C_MXC
#define CONFIG_SYS_I2C_BASE IMX_I2C_BASE
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
#define CONFIG_SYS_SPD_BUS_NUM 0 /* I2C1 */
/* RTC */
#define CONFIG_RTC_IMXDI

7
include/configs/mx35pdk.h
View file

@ -40,10 +40,9 @@
/*
* Hardware drivers
*/
#define CONFIG_HARD_I2C
#define CONFIG_I2C_MXC
#define CONFIG_SYS_I2C_BASE I2C1_BASE_ADDR
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
#define CONFIG_SYS_SPD_BUS_NUM 0 /* I2C1 */
#define CONFIG_MXC_SPI
#define CONFIG_MXC_GPIO

7
include/configs/mx53ard.h
View file

@ -44,10 +44,9 @@
/* I2C Configs */
#define CONFIG_CMD_I2C
#define CONFIG_HARD_I2C
#define CONFIG_I2C_MXC
#define CONFIG_SYS_I2C_BASE I2C2_BASE_ADDR
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
#define CONFIG_SYS_SPD_BUS_NUM 1 /* I2C2 */
/* MMC Configs */
#define CONFIG_FSL_ESDHC

7
include/configs/mx53evk.h
View file

@ -37,10 +37,9 @@
/* I2C Configs */
#define CONFIG_CMD_I2C
#define CONFIG_HARD_I2C
#define CONFIG_I2C_MXC
#define CONFIG_SYS_I2C_BASE I2C2_BASE_ADDR
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
#define CONFIG_SYS_SPD_BUS_NUM 1 /* I2C2 */
/* PMIC Configs */
#define CONFIG_POWER

7
include/configs/mx53loco.h
View file

@ -71,10 +71,9 @@
#define CONFIG_MXC_USB_FLAGS 0
/* I2C Configs */
#define CONFIG_HARD_I2C
#define CONFIG_I2C_MXC
#define CONFIG_SYS_I2C_BASE I2C1_BASE_ADDR
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
#define CONFIG_SYS_SPD_BUS_NUM 0 /* I2C1 */
/* PMIC Controller */
#define CONFIG_POWER

7
include/configs/mx53smd.h
View file

@ -34,10 +34,9 @@
/* I2C Configs */
#define CONFIG_CMD_I2C
#define CONFIG_HARD_I2C
#define CONFIG_I2C_MXC
#define CONFIG_SYS_I2C_BASE I2C2_BASE_ADDR
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
#define CONFIG_SYS_SPD_BUS_NUM 1 /* I2C2 */
/* MMC Configs */
#define CONFIG_FSL_ESDHC

4
include/configs/mx6qsabreauto.h
View file

@ -36,8 +36,8 @@
/* I2C Configs */
#define CONFIG_CMD_I2C
#define CONFIG_I2C_MULTI_BUS
#define CONFIG_I2C_MXC
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
#define CONFIG_SYS_I2C_SPEED 100000
#endif /* __MX6QSABREAUTO_CONFIG_H */

4
include/configs/nitrogen6x.h
View file

@ -52,8 +52,8 @@
/* I2C Configs */
#define CONFIG_CMD_I2C
#define CONFIG_I2C_MULTI_BUS
#define CONFIG_I2C_MXC
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
#define CONFIG_SYS_I2C_SPEED 100000
/* OCOTP Configs */

4
include/configs/titanium.h
View file

@ -41,8 +41,8 @@
/* I2C Configs */
#define CONFIG_CMD_I2C
#define CONFIG_I2C_MULTI_BUS
#define CONFIG_I2C_MXC
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
#define CONFIG_SYS_I2C_SPEED 100000
/* MMC Configs */

7
include/configs/vf610twr.h
View file

@ -70,10 +70,9 @@
/* I2C Configs */
#define CONFIG_CMD_I2C
#define CONFIG_HARD_I2C
#define CONFIG_I2C_MXC
#define CONFIG_SYS_I2C_BASE I2C0_BASE_ADDR
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
#define CONFIG_SYS_SPD_BUS_NUM 0
#define CONFIG_BOOTDELAY 3

7
include/configs/woodburn_common.h
View file

@ -45,10 +45,9 @@
/*
* Hardware drivers
*/
#define CONFIG_HARD_I2C
#define CONFIG_I2C_MXC
#define CONFIG_SYS_I2C_BASE I2C1_BASE_ADDR
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
#define CONFIG_SYS_SPD_BUS_NUM 0
#define CONFIG_MXC_SPI
#define CONFIG_MXC_GPIO

2
include/i2c.h
View file

@ -135,6 +135,8 @@ extern struct i2c_bus_hose i2c_bus[];
#define I2C_MUX_PCA9544 {I2C_MUX_PCA9544_ID, "PCA9544A"}
#define I2C_MUX_PCA9547_ID 4
#define I2C_MUX_PCA9547 {I2C_MUX_PCA9547_ID, "PCA9547A"}
#define I2C_MUX_PCA9548_ID 5
#define I2C_MUX_PCA9548 {I2C_MUX_PCA9548_ID, "PCA9548"}
#endif
#ifndef I2C_SOFT_DECLARATIONS