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mx31: Fix PDR0_CSI_PODF
The CSI PODF bit-field used by the previous code for the i.MX31 CCM PDR0 register is actually composed of two bit-fields: one pre-divider and one post-divider. This patch fixes the CCM access macros and the code using them accordingly. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
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parent
b809b3ac13
commit
9e0081d573
6 changed files with 14 additions and 12 deletions
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@ -569,7 +569,8 @@ struct esdc_regs {
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#define MX31_IIM_BASE_ADDR 0x5001C000
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#define PDR0_CSI_PODF(x) (((x) & 0x1ff) << 23)
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#define PDR0_CSI_PODF(x) (((x) & 0x3f) << 26)
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#define PDR0_CSI_PRDF(x) (((x) & 0x7) << 23)
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#define PDR0_PER_PODF(x) (((x) & 0x1f) << 16)
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#define PDR0_HSP_PODF(x) (((x) & 0x7) << 11)
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#define PDR0_NFC_PODF(x) (((x) & 0x7) << 8)
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@ -592,7 +593,8 @@ struct esdc_regs {
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#define PLL_MFI(x) (((x) & 0xf) << 10)
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#define PLL_MFN(x) (((x) & 0x3ff) << 0)
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#define GET_PDR0_CSI_PODF(x) (((x) >> 23) & 0x1ff)
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#define GET_PDR0_CSI_PODF(x) (((x) >> 26) & 0x3f)
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#define GET_PDR0_CSI_PRDF(x) (((x) >> 23) & 0x7)
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#define GET_PDR0_PER_PODF(x) (((x) >> 16) & 0x1f)
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#define GET_PDR0_HSP_PODF(x) (((x) >> 11) & 0x7)
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#define GET_PDR0_NFC_PODF(x) (((x) >> 8) & 0x7)
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@ -246,8 +246,8 @@ lowlevel_init:
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/* COSR */
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str r1, [r0, #0x1c]
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/* RedBoot sets 0x1ff, 7, 3, 5, 1, 3, 0 */
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/* REG CCM_PDR0, PDR0_CSI_PODF(0x1ff) | PDR0_PER_PODF(7) | PDR0_HSP_PODF(2) | PDR0_NFC_PODF(6) | PDR0_IPG_PODF(1) | PDR0_MAX_PODF(2) | PDR0_MCU_PODF(0)*/
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/* RedBoot sets 0x3f, 7, 7, 3, 5, 1, 3, 0 */
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/* REG CCM_PDR0, PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | PDR0_PER_PODF(7) | PDR0_HSP_PODF(2) | PDR0_NFC_PODF(6) | PDR0_IPG_PODF(1) | PDR0_MAX_PODF(2) | PDR0_MCU_PODF(0)*/
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/* Redboot: 0, 51, 10, 12 / 0, 14, 9, 13 */
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/* REG CCM_MPCTL, PLL_PD(0) | PLL_MFD(0x33) | PLL_MFI(7) | PLL_MFN(0x23)*/
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@ -52,7 +52,7 @@ static void board_setup_clocks(void)
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writel((CCM_CCMR_SETUP | CCMR_MPE) & ~CCMR_MDS, &ccm->ccmr);
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/* Set up clock to 532MHz */
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writel(PDR0_CSI_PODF(0x1ff) | PDR0_PER_PODF(7) |
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writel(PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | PDR0_PER_PODF(7) |
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PDR0_HSP_PODF(3) | PDR0_NFC_PODF(5) |
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PDR0_IPG_PODF(1) | PDR0_MAX_PODF(3) |
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PDR0_MCU_PODF(0), &ccm->pdr0);
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@ -54,7 +54,7 @@ lowlevel_init:
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REG CCM_CCMR, 0x074B0BF5 | CCMR_MPE
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REG CCM_CCMR, (0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS
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REG CCM_PDR0, PDR0_CSI_PODF(0xff1) | PDR0_PER_PODF(7) | PDR0_HSP_PODF(3) | PDR0_NFC_PODF(5) | PDR0_IPG_PODF(1) | PDR0_MAX_PODF(3) | PDR0_MCU_PODF(0)
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REG CCM_PDR0, PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | PDR0_PER_PODF(7) | PDR0_HSP_PODF(3) | PDR0_NFC_PODF(5) | PDR0_IPG_PODF(1) | PDR0_MAX_PODF(3) | PDR0_MCU_PODF(0)
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REG CCM_MPCTL, PLL_PD(0) | PLL_MFD(0xe) | PLL_MFI(9) | PLL_MFN(0xd)
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@ -54,7 +54,7 @@ lowlevel_init:
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REG CCM_CCMR, 0x074B0BF5 | CCMR_MPE
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REG CCM_CCMR, (0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS
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REG CCM_PDR0, PDR0_CSI_PODF(0x1ff) | PDR0_PER_PODF(7) | PDR0_HSP_PODF(2) | PDR0_NFC_PODF(6) | PDR0_IPG_PODF(1) | PDR0_MAX_PODF(2) | PDR0_MCU_PODF(0)
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REG CCM_PDR0, PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | PDR0_PER_PODF(7) | PDR0_HSP_PODF(2) | PDR0_NFC_PODF(6) | PDR0_IPG_PODF(1) | PDR0_MAX_PODF(2) | PDR0_MCU_PODF(0)
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REG CCM_MPCTL, PLL_PD(0) | PLL_MFD(0x33) | PLL_MFI(7) | PLL_MFN(0x23)
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REG CCM_SPCTL, PLL_PD(1) | PLL_MFD(4) | PLL_MFI(12) | PLL_MFN(1)
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@ -203,11 +203,11 @@
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/* Configuration of lowlevel_init.S (clocks and SDRAM) */
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#define CCM_CCMR_SETUP 0x074B0BF5
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#define CCM_PDR0_SETUP_532MHZ (PDR0_CSI_PODF(0x1ff) | PDR0_PER_PODF(7) | \
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PDR0_HSP_PODF(3) | PDR0_NFC_PODF(5) | \
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PDR0_IPG_PODF(1) | PDR0_MAX_PODF(3) | \
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PDR0_MCU_PODF(0))
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#define CCM_MPCTL_SETUP_532MHZ (PLL_PD(0) | PLL_MFD(51) | PLL_MFI(10) | \
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#define CCM_PDR0_SETUP_532MHZ (PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | \
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PDR0_PER_PODF(7) | PDR0_HSP_PODF(3) | \
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PDR0_NFC_PODF(5) | PDR0_IPG_PODF(1) | \
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PDR0_MAX_PODF(3) | PDR0_MCU_PODF(0))
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#define CCM_MPCTL_SETUP_532MHZ (PLL_PD(0) | PLL_MFD(51) | PLL_MFI(10) | \
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PLL_MFN(12))
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#define ESDMISC_MDDR_SETUP 0x00000004
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