mirror of
https://github.com/Fishwaldo/u-boot.git
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ARM: at91/dt: sama5d2: Fix the warning from dtc
Fix the warning from dtc like, ---8<---- Warning (unit_address_vs_reg): Node /ahb/apb/pmc@f0014000/periph64ck/sdmmc0_hclk has a reg or ranges property, but no unit name --->8---- Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Acked-by: Stephen Warren <swarren@nvidia.com>
This commit is contained in:
Wenyou Yang
Andreas Bießmann
parent
b892b054b1
commit
9e63c49a52
1 changed files with 70 additions and 70 deletions
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@ -79,7 +79,7 @@
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#clock-cells = <0>;
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#clock-cells = <0>;
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};
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};
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plla: pllack {
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plla: pllack@0 {
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compatible = "atmel,sama5d3-clk-pll";
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compatible = "atmel,sama5d3-clk-pll";
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#clock-cells = <0>;
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#clock-cells = <0>;
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clocks = <&main>;
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clocks = <&main>;
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@ -146,17 +146,17 @@
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interrupt-parent = <&pmc>;
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interrupt-parent = <&pmc>;
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clocks = <&main>, <&plladiv>, <&utmi>, <&mck>;
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clocks = <&main>, <&plladiv>, <&utmi>, <&mck>;
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prog0: prog0 {
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prog0: prog@0 {
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#clock-cells = <0>;
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#clock-cells = <0>;
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reg = <0>;
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reg = <0>;
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};
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};
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prog1: prog1 {
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prog1: prog@1 {
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#clock-cells = <0>;
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#clock-cells = <0>;
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reg = <1>;
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reg = <1>;
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};
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};
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prog2: prog2 {
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prog2: prog@2 {
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#clock-cells = <0>;
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#clock-cells = <0>;
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reg = <2>;
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reg = <2>;
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};
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};
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@ -167,49 +167,49 @@
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#address-cells = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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#size-cells = <0>;
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ddrck: ddrck {
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ddrck: ddrck@2 {
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#clock-cells = <0>;
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#clock-cells = <0>;
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reg = <2>;
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reg = <2>;
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clocks = <&mck>;
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clocks = <&mck>;
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};
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};
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lcdck: lcdck {
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lcdck: lcdck@3 {
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#clock-cells = <0>;
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#clock-cells = <0>;
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reg = <3>;
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reg = <3>;
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clocks = <&mck>;
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clocks = <&mck>;
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};
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};
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uhpck: uhpck {
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uhpck: uhpck@6 {
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#clock-cells = <0>;
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#clock-cells = <0>;
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reg = <6>;
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reg = <6>;
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clocks = <&usb>;
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clocks = <&usb>;
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};
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};
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udpck: udpck {
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udpck: udpck@7 {
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#clock-cells = <0>;
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#clock-cells = <0>;
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reg = <7>;
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reg = <7>;
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clocks = <&usb>;
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clocks = <&usb>;
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};
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};
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pck0: pck0 {
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pck0: pck0@8 {
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#clock-cells = <0>;
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#clock-cells = <0>;
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reg = <8>;
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reg = <8>;
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clocks = <&prog0>;
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clocks = <&prog0>;
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};
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};
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pck1: pck1 {
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pck1: pck1@9 {
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#clock-cells = <0>;
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#clock-cells = <0>;
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reg = <9>;
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reg = <9>;
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clocks = <&prog1>;
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clocks = <&prog1>;
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};
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};
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pck2: pck2 {
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pck2: pck2@10 {
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#clock-cells = <0>;
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#clock-cells = <0>;
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reg = <10>;
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reg = <10>;
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clocks = <&prog2>;
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clocks = <&prog2>;
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};
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};
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iscck: iscck {
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iscck: iscck@18 {
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#clock-cells = <0>;
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#clock-cells = <0>;
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reg = <18>;
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reg = <18>;
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clocks = <&mck>;
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clocks = <&mck>;
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@ -222,203 +222,203 @@
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#size-cells = <0>;
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#size-cells = <0>;
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clocks = <&h32ck>;
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clocks = <&h32ck>;
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macb0_clk: macb0_clk {
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macb0_clk: macb0_clk@5 {
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#clock-cells = <0>;
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#clock-cells = <0>;
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reg = <5>;
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reg = <5>;
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atmel,clk-output-range = <0 83000000>;
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atmel,clk-output-range = <0 83000000>;
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};
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};
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tdes_clk: tdes_clk {
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tdes_clk: tdes_clk@11 {
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#clock-cells = <0>;
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#clock-cells = <0>;
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reg = <11>;
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reg = <11>;
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atmel,clk-output-range = <0 83000000>;
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atmel,clk-output-range = <0 83000000>;
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};
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};
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matrix1_clk: matrix1_clk {
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matrix1_clk: matrix1_clk@14 {
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#clock-cells = <0>;
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#clock-cells = <0>;
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reg = <14>;
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reg = <14>;
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};
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};
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hsmc_clk: hsmc_clk {
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hsmc_clk: hsmc_clk@17 {
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#clock-cells = <0>;
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#clock-cells = <0>;
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reg = <17>;
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reg = <17>;
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};
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};
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pioA_clk: pioA_clk {
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pioA_clk: pioA_clk@18 {
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#clock-cells = <0>;
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#clock-cells = <0>;
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reg = <18>;
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reg = <18>;
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atmel,clk-output-range = <0 83000000>;
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atmel,clk-output-range = <0 83000000>;
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};
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};
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flx0_clk: flx0_clk {
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flx0_clk: flx0_clk@19 {
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#clock-cells = <0>;
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#clock-cells = <0>;
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reg = <19>;
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reg = <19>;
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atmel,clk-output-range = <0 83000000>;
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atmel,clk-output-range = <0 83000000>;
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};
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};
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flx1_clk: flx1_clk {
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flx1_clk: flx1_clk@20 {
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#clock-cells = <0>;
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#clock-cells = <0>;
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reg = <20>;
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reg = <20>;
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atmel,clk-output-range = <0 83000000>;
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atmel,clk-output-range = <0 83000000>;
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};
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};
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flx2_clk: flx2_clk {
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flx2_clk: flx2_clk@21 {
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#clock-cells = <0>;
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#clock-cells = <0>;
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reg = <21>;
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reg = <21>;
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atmel,clk-output-range = <0 83000000>;
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atmel,clk-output-range = <0 83000000>;
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};
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};
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flx3_clk: flx3_clk {
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flx3_clk: flx3_clk@22 {
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#clock-cells = <0>;
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#clock-cells = <0>;
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reg = <22>;
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reg = <22>;
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atmel,clk-output-range = <0 83000000>;
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atmel,clk-output-range = <0 83000000>;
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};
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};
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flx4_clk: flx4_clk {
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flx4_clk: flx4_clk@23 {
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#clock-cells = <0>;
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#clock-cells = <0>;
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reg = <23>;
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reg = <23>;
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atmel,clk-output-range = <0 83000000>;
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atmel,clk-output-range = <0 83000000>;
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};
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};
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uart0_clk: uart0_clk {
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uart0_clk: uart0_clk@24 {
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#clock-cells = <0>;
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#clock-cells = <0>;
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reg = <24>;
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reg = <24>;
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atmel,clk-output-range = <0 83000000>;
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atmel,clk-output-range = <0 83000000>;
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};
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};
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uart1_clk: uart1_clk {
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uart1_clk: uart1_clk@25 {
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#clock-cells = <0>;
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#clock-cells = <0>;
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reg = <25>;
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reg = <25>;
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atmel,clk-output-range = <0 83000000>;
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atmel,clk-output-range = <0 83000000>;
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};
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};
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uart2_clk: uart2_clk {
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uart2_clk: uart2_clk@26 {
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#clock-cells = <0>;
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#clock-cells = <0>;
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reg = <26>;
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reg = <26>;
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atmel,clk-output-range = <0 83000000>;
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atmel,clk-output-range = <0 83000000>;
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};
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};
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uart3_clk: uart3_clk {
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uart3_clk: uart3_clk@27 {
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#clock-cells = <0>;
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#clock-cells = <0>;
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reg = <27>;
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reg = <27>;
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atmel,clk-output-range = <0 83000000>;
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atmel,clk-output-range = <0 83000000>;
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};
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};
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uart4_clk: uart4_clk {
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uart4_clk: uart4_clk@28 {
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#clock-cells = <0>;
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#clock-cells = <0>;
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reg = <28>;
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reg = <28>;
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atmel,clk-output-range = <0 83000000>;
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atmel,clk-output-range = <0 83000000>;
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};
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};
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twi0_clk: twi0_clk {
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twi0_clk: twi0_clk@29 {
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reg = <29>;
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reg = <29>;
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#clock-cells = <0>;
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#clock-cells = <0>;
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atmel,clk-output-range = <0 83000000>;
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atmel,clk-output-range = <0 83000000>;
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};
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};
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twi1_clk: twi1_clk {
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twi1_clk: twi1_clk@30 {
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#clock-cells = <0>;
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#clock-cells = <0>;
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reg = <30>;
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reg = <30>;
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atmel,clk-output-range = <0 83000000>;
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atmel,clk-output-range = <0 83000000>;
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};
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};
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spi0_clk: spi0_clk {
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spi0_clk: spi0_clk@33 {
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#clock-cells = <0>;
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#clock-cells = <0>;
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reg = <33>;
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reg = <33>;
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atmel,clk-output-range = <0 83000000>;
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atmel,clk-output-range = <0 83000000>;
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};
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};
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spi1_clk: spi1_clk {
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spi1_clk: spi1_clk@34 {
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#clock-cells = <0>;
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#clock-cells = <0>;
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reg = <34>;
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reg = <34>;
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atmel,clk-output-range = <0 83000000>;
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atmel,clk-output-range = <0 83000000>;
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};
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};
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tcb0_clk: tcb0_clk {
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tcb0_clk: tcb0_clk@35 {
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#clock-cells = <0>;
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#clock-cells = <0>;
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reg = <35>;
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reg = <35>;
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atmel,clk-output-range = <0 83000000>;
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atmel,clk-output-range = <0 83000000>;
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};
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};
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tcb1_clk: tcb1_clk {
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tcb1_clk: tcb1_clk@36 {
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#clock-cells = <0>;
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#clock-cells = <0>;
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reg = <36>;
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reg = <36>;
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atmel,clk-output-range = <0 83000000>;
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atmel,clk-output-range = <0 83000000>;
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};
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};
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pwm_clk: pwm_clk {
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pwm_clk: pwm_clk@38 {
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#clock-cells = <0>;
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#clock-cells = <0>;
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reg = <38>;
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reg = <38>;
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atmel,clk-output-range = <0 83000000>;
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atmel,clk-output-range = <0 83000000>;
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};
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};
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adc_clk: adc_clk {
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adc_clk: adc_clk@40 {
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#clock-cells = <0>;
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#clock-cells = <0>;
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reg = <40>;
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reg = <40>;
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atmel,clk-output-range = <0 83000000>;
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atmel,clk-output-range = <0 83000000>;
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};
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};
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uhphs_clk: uhphs_clk {
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uhphs_clk: uhphs_clk@41 {
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#clock-cells = <0>;
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#clock-cells = <0>;
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reg = <41>;
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reg = <41>;
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atmel,clk-output-range = <0 83000000>;
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atmel,clk-output-range = <0 83000000>;
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};
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};
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udphs_clk: udphs_clk {
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udphs_clk: udphs_clk@42 {
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#clock-cells = <0>;
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#clock-cells = <0>;
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reg = <42>;
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reg = <42>;
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atmel,clk-output-range = <0 83000000>;
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atmel,clk-output-range = <0 83000000>;
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};
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};
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ssc0_clk: ssc0_clk {
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ssc0_clk: ssc0_clk@43 {
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#clock-cells = <0>;
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#clock-cells = <0>;
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reg = <43>;
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reg = <43>;
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atmel,clk-output-range = <0 83000000>;
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atmel,clk-output-range = <0 83000000>;
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};
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};
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ssc1_clk: ssc1_clk {
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ssc1_clk: ssc1_clk@44 {
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#clock-cells = <0>;
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#clock-cells = <0>;
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reg = <44>;
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reg = <44>;
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atmel,clk-output-range = <0 83000000>;
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atmel,clk-output-range = <0 83000000>;
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};
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};
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trng_clk: trng_clk {
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trng_clk: trng_clk@47 {
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#clock-cells = <0>;
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#clock-cells = <0>;
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reg = <47>;
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reg = <47>;
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atmel,clk-output-range = <0 83000000>;
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atmel,clk-output-range = <0 83000000>;
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};
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};
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pdmic_clk: pdmic_clk {
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pdmic_clk: pdmic_clk@48 {
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#clock-cells = <0>;
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#clock-cells = <0>;
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reg = <48>;
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reg = <48>;
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atmel,clk-output-range = <0 83000000>;
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atmel,clk-output-range = <0 83000000>;
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};
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};
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i2s0_clk: i2s0_clk {
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i2s0_clk: i2s0_clk@54 {
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#clock-cells = <0>;
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#clock-cells = <0>;
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reg = <54>;
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reg = <54>;
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atmel,clk-output-range = <0 83000000>;
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atmel,clk-output-range = <0 83000000>;
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};
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};
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i2s1_clk: i2s1_clk {
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i2s1_clk: i2s1_clk@55 {
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#clock-cells = <0>;
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#clock-cells = <0>;
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reg = <55>;
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reg = <55>;
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atmel,clk-output-range = <0 83000000>;
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atmel,clk-output-range = <0 83000000>;
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};
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};
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can0_clk: can0_clk {
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can0_clk: can0_clk@56 {
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#clock-cells = <0>;
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#clock-cells = <0>;
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reg = <56>;
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reg = <56>;
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atmel,clk-output-range = <0 83000000>;
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atmel,clk-output-range = <0 83000000>;
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};
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};
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can1_clk: can1_clk {
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can1_clk: can1_clk@57 {
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#clock-cells = <0>;
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#clock-cells = <0>;
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reg = <57>;
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reg = <57>;
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atmel,clk-output-range = <0 83000000>;
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atmel,clk-output-range = <0 83000000>;
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};
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};
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classd_clk: classd_clk {
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classd_clk: classd_clk@59 {
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#clock-cells = <0>;
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#clock-cells = <0>;
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reg = <59>;
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reg = <59>;
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atmel,clk-output-range = <0 83000000>;
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atmel,clk-output-range = <0 83000000>;
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@ -431,67 +431,67 @@
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#size-cells = <0>;
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#size-cells = <0>;
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clocks = <&mck>;
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clocks = <&mck>;
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dma0_clk: dma0_clk {
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dma0_clk: dma0_clk@6 {
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#clock-cells = <0>;
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#clock-cells = <0>;
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reg = <6>;
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reg = <6>;
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};
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};
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dma1_clk: dma1_clk {
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dma1_clk: dma1_clk@7 {
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#clock-cells = <0>;
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#clock-cells = <0>;
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reg = <7>;
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reg = <7>;
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};
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};
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aes_clk: aes_clk {
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aes_clk: aes_clk@9 {
|
||||||
#clock-cells = <0>;
|
#clock-cells = <0>;
|
||||||
reg = <9>;
|
reg = <9>;
|
||||||
};
|
};
|
||||||
|
|
||||||
aesb_clk: aesb_clk {
|
aesb_clk: aesb_clk@10 {
|
||||||
#clock-cells = <0>;
|
#clock-cells = <0>;
|
||||||
reg = <10>;
|
reg = <10>;
|
||||||
};
|
};
|
||||||
|
|
||||||
sha_clk: sha_clk {
|
sha_clk: sha_clk@12 {
|
||||||
#clock-cells = <0>;
|
#clock-cells = <0>;
|
||||||
reg = <12>;
|
reg = <12>;
|
||||||
};
|
};
|
||||||
|
|
||||||
mpddr_clk: mpddr_clk {
|
mpddr_clk: mpddr_clk@13 {
|
||||||
#clock-cells = <0>;
|
#clock-cells = <0>;
|
||||||
reg = <13>;
|
reg = <13>;
|
||||||
};
|
};
|
||||||
|
|
||||||
matrix0_clk: matrix0_clk {
|
matrix0_clk: matrix0_clk@15 {
|
||||||
#clock-cells = <0>;
|
#clock-cells = <0>;
|
||||||
reg = <15>;
|
reg = <15>;
|
||||||
};
|
};
|
||||||
|
|
||||||
sdmmc0_hclk: sdmmc0_hclk {
|
sdmmc0_hclk: sdmmc0_hclk@31 {
|
||||||
#clock-cells = <0>;
|
#clock-cells = <0>;
|
||||||
reg = <31>;
|
reg = <31>;
|
||||||
};
|
};
|
||||||
|
|
||||||
sdmmc1_hclk: sdmmc1_hclk {
|
sdmmc1_hclk: sdmmc1_hclk@32 {
|
||||||
#clock-cells = <0>;
|
#clock-cells = <0>;
|
||||||
reg = <32>;
|
reg = <32>;
|
||||||
};
|
};
|
||||||
|
|
||||||
lcdc_clk: lcdc_clk {
|
lcdc_clk: lcdc_clk@45 {
|
||||||
#clock-cells = <0>;
|
#clock-cells = <0>;
|
||||||
reg = <45>;
|
reg = <45>;
|
||||||
};
|
};
|
||||||
|
|
||||||
isc_clk: isc_clk {
|
isc_clk: isc_clk@46 {
|
||||||
#clock-cells = <0>;
|
#clock-cells = <0>;
|
||||||
reg = <46>;
|
reg = <46>;
|
||||||
};
|
};
|
||||||
|
|
||||||
qspi0_clk: qspi0_clk {
|
qspi0_clk: qspi0_clk@52 {
|
||||||
#clock-cells = <0>;
|
#clock-cells = <0>;
|
||||||
reg = <52>;
|
reg = <52>;
|
||||||
};
|
};
|
||||||
|
|
||||||
qspi1_clk: qspi1_clk {
|
qspi1_clk: qspi1_clk@53 {
|
||||||
#clock-cells = <0>;
|
#clock-cells = <0>;
|
||||||
reg = <53>;
|
reg = <53>;
|
||||||
};
|
};
|
||||||
|
|
@ -504,62 +504,62 @@
|
||||||
interrupt-parent = <&pmc>;
|
interrupt-parent = <&pmc>;
|
||||||
clocks = <&main>, <&plla>, <&utmi>, <&mck>;
|
clocks = <&main>, <&plla>, <&utmi>, <&mck>;
|
||||||
|
|
||||||
sdmmc0_gclk: sdmmc0_gclk {
|
sdmmc0_gclk: sdmmc0_gclk@31 {
|
||||||
#clock-cells = <0>;
|
#clock-cells = <0>;
|
||||||
reg = <31>;
|
reg = <31>;
|
||||||
};
|
};
|
||||||
|
|
||||||
sdmmc1_gclk: sdmmc1_gclk {
|
sdmmc1_gclk: sdmmc1_gclk@32 {
|
||||||
#clock-cells = <0>;
|
#clock-cells = <0>;
|
||||||
reg = <32>;
|
reg = <32>;
|
||||||
};
|
};
|
||||||
|
|
||||||
tcb0_gclk: tcb0_gclk {
|
tcb0_gclk: tcb0_gclk@35 {
|
||||||
#clock-cells = <0>;
|
#clock-cells = <0>;
|
||||||
reg = <35>;
|
reg = <35>;
|
||||||
atmel,clk-output-range = <0 83000000>;
|
atmel,clk-output-range = <0 83000000>;
|
||||||
};
|
};
|
||||||
|
|
||||||
tcb1_gclk: tcb1_gclk {
|
tcb1_gclk: tcb1_gclk@36 {
|
||||||
#clock-cells = <0>;
|
#clock-cells = <0>;
|
||||||
reg = <36>;
|
reg = <36>;
|
||||||
atmel,clk-output-range = <0 83000000>;
|
atmel,clk-output-range = <0 83000000>;
|
||||||
};
|
};
|
||||||
|
|
||||||
pwm_gclk: pwm_gclk {
|
pwm_gclk: pwm_gclk@38 {
|
||||||
#clock-cells = <0>;
|
#clock-cells = <0>;
|
||||||
reg = <38>;
|
reg = <38>;
|
||||||
atmel,clk-output-range = <0 83000000>;
|
atmel,clk-output-range = <0 83000000>;
|
||||||
};
|
};
|
||||||
|
|
||||||
pdmic_gclk: pdmic_gclk {
|
pdmic_gclk: pdmic_gclk@48 {
|
||||||
#clock-cells = <0>;
|
#clock-cells = <0>;
|
||||||
reg = <48>;
|
reg = <48>;
|
||||||
};
|
};
|
||||||
|
|
||||||
i2s0_gclk: i2s0_gclk {
|
i2s0_gclk: i2s0_gclk@54 {
|
||||||
#clock-cells = <0>;
|
#clock-cells = <0>;
|
||||||
reg = <54>;
|
reg = <54>;
|
||||||
};
|
};
|
||||||
|
|
||||||
i2s1_gclk: i2s1_gclk {
|
i2s1_gclk: i2s1_gclk@55 {
|
||||||
#clock-cells = <0>;
|
#clock-cells = <0>;
|
||||||
reg = <55>;
|
reg = <55>;
|
||||||
};
|
};
|
||||||
|
|
||||||
can0_gclk: can0_gclk {
|
can0_gclk: can0_gclk@56 {
|
||||||
#clock-cells = <0>;
|
#clock-cells = <0>;
|
||||||
reg = <56>;
|
reg = <56>;
|
||||||
atmel,clk-output-range = <0 80000000>;
|
atmel,clk-output-range = <0 80000000>;
|
||||||
};
|
};
|
||||||
|
|
||||||
can1_gclk: can1_gclk {
|
can1_gclk: can1_gclk@57 {
|
||||||
#clock-cells = <0>;
|
#clock-cells = <0>;
|
||||||
reg = <57>;
|
reg = <57>;
|
||||||
atmel,clk-output-range = <0 80000000>;
|
atmel,clk-output-range = <0 80000000>;
|
||||||
};
|
};
|
||||||
|
|
||||||
classd_gclk: classd_gclk {
|
classd_gclk: classd_gclk@59 {
|
||||||
#clock-cells = <0>;
|
#clock-cells = <0>;
|
||||||
reg = <59>;
|
reg = <59>;
|
||||||
atmel,clk-output-range = <0 100000000>;
|
atmel,clk-output-range = <0 100000000>;
|
||||||
|
|
|
||||||
Loading…
Add table
Reference in a new issue