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Merge branch 'master' of git://git.denx.de/u-boot-avr32

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This commit is contained in:
Tom Rini 2015-02-17 22:11:36 -05:00
commit 9ec84f103b
40 changed files with 294 additions and 307 deletions
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1
arch/arm/lib/Makefile
View file

@ -35,6 +35,7 @@ endif
obj-$(CONFIG_SEMIHOSTING) += semihosting.o
obj-y += sections.o
obj-y += stack.o
ifdef CONFIG_ARM64
obj-y += gic_64.o
obj-y += interrupts_64.o

42
arch/arm/lib/stack.c Normal file
View file

@ -0,0 +1,42 @@
/*
* Copyright (c) 2015 Andreas Bießmann <andreas.devel@googlemail.com>
*
* Copyright (c) 2011 The Chromium OS Authors.
* (C) Copyright 2002-2006
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
DECLARE_GLOBAL_DATA_PTR;
int arch_reserve_stacks(void)
{
#ifdef CONFIG_SPL_BUILD
gd->start_addr_sp -= 128; /* leave 32 words for abort-stack */
gd->irq_sp = gd->start_addr_sp;
#else
/* setup stack pointer for exceptions */
gd->irq_sp = gd->start_addr_sp;
# if !defined(CONFIG_ARM64)
# ifdef CONFIG_USE_IRQ
gd->start_addr_sp -= (CONFIG_STACKSIZE_IRQ + CONFIG_STACKSIZE_FIQ);
debug("Reserving %zu Bytes for IRQ stack at: %08lx\n",
CONFIG_STACKSIZE_IRQ + CONFIG_STACKSIZE_FIQ, gd->start_addr_sp);
/* 8-byte alignment for ARM ABI compliance */
gd->start_addr_sp &= ~0x07;
# endif
/* leave 3 words for abort-stack, plus 1 for alignment */
gd->start_addr_sp -= 16;
# endif
#endif
return 0;
}

3
arch/avr32/config.mk
View file

@ -9,6 +9,9 @@ ifeq ($(CROSS_COMPILE),)
CROSS_COMPILE := avr32-linux-
endif
# avr32 has generic board support
__HAVE_ARCH_GENERIC_BOARD := y
CONFIG_STANDALONE_LOAD_ADDR ?= 0x00000000
PLATFORM_RELFLAGS += -ffixed-r5 -fPIC -mno-init-got -mrelax

1
arch/avr32/cpu/Makefile
View file

@ -16,5 +16,6 @@ obj-y += cache.o
obj-y += interrupts.o
obj-$(CONFIG_PORTMUX_PIO) += portmux-pio.o
obj-$(CONFIG_PORTMUX_GPIO) += portmux-gpio.o
obj-y += mmc.o
obj-$(if $(filter at32ap700x,$(SOC)),y) += at32ap700x/

8
arch/avr32/cpu/at32ap700x/mmu.c
View file

@ -7,7 +7,7 @@ void mmu_init_r(unsigned long dest_addr)
uintptr_t vmr_table_addr;
/* Round monitor address down to the nearest page boundary */
dest_addr &= PAGE_ADDR_MASK;
dest_addr &= MMU_PAGE_ADDR_MASK;
/* Initialize TLB entry 0 to cover the monitor, and lock it */
sysreg_write(TLBEHI, dest_addr | SYSREG_BIT(TLBEHI_V));
@ -36,7 +36,7 @@ int mmu_handle_tlb_miss(void)
unsigned int fault_pgno;
int first, last;
fault_pgno = sysreg_read(TLBEAR) >> PAGE_SHIFT;
fault_pgno = sysreg_read(TLBEAR) >> MMU_PAGE_SHIFT;
vmr_table = (const struct mmu_vm_range *)sysreg_read(PTBR);
/* Do a binary search through the VM ranges */
@ -60,8 +60,8 @@ int mmu_handle_tlb_miss(void)
/* Got it; let's slam it into the TLB */
uint32_t tlbelo;
tlbelo = vmr->phys & ~PAGE_ADDR_MASK;
tlbelo |= fault_pgno << PAGE_SHIFT;
tlbelo = vmr->phys & ~MMU_PAGE_ADDR_MASK;
tlbelo |= fault_pgno << MMU_PAGE_SHIFT;
sysreg_write(TLBELO, tlbelo);
__builtin_tlbw();

2
arch/avr32/cpu/cpu.c
View file

@ -27,7 +27,7 @@
DECLARE_GLOBAL_DATA_PTR;
int cpu_init(void)
int arch_cpu_init(void)
{
extern void _evba(void);

6
arch/avr32/cpu/exception.c
View file

@ -96,11 +96,11 @@ void do_unknown_exception(unsigned int ecr, struct pt_regs *regs)
printf("CPU Mode: %s\n", cpu_modes[mode]);
/* Avoid exception loops */
if (regs->sp < (gd->arch.stack_end - CONFIG_STACKSIZE)
|| regs->sp >= gd->arch.stack_end)
if (regs->sp < (gd->start_addr_sp - CONFIG_STACKSIZE) ||
regs->sp >= gd->start_addr_sp)
printf("\nStack pointer seems bogus, won't do stack dump\n");
else
dump_mem("\nStack: ", regs->sp, gd->arch.stack_end);
dump_mem("\nStack: ", regs->sp, gd->start_addr_sp);
panic("Unhandled exception\n");
}

16
arch/avr32/cpu/mmc.c Normal file
View file

@ -0,0 +1,16 @@
/*
* Copyright (C) 2004-2006 Atmel Corporation
* Copyright (C) 2015 Andreas Bießmann <andreas.devel@googlmail.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <atmel_mci.h>
#include <asm/arch/hardware.h>
/* provide cpu_mmc_init, to overwrite provide board_mmc_init */
int cpu_mmc_init(bd_t *bd)
{
/* This calls the atmel_mci_init in gen_atmel_mci.c */
return atmel_mci_init((void *)ATMEL_BASE_MMCI);
}

2
arch/avr32/cpu/u-boot.lds
View file

@ -48,9 +48,11 @@ SECTIONS
_edata = .;
.bss (NOLOAD) : {
__bss_start = .;
*(.bss)
*(.bss.*)
}
. = ALIGN(8);
__bss_end = .;
__init_end = .;
}

6
arch/avr32/include/asm/arch-at32ap700x/mmu.h
View file

@ -13,9 +13,9 @@
#include <asm/sysreg.h>
#define PAGE_SHIFT 20
#define PAGE_SIZE (1UL << PAGE_SHIFT)
#define PAGE_ADDR_MASK (~(PAGE_SIZE - 1))
#define MMU_PAGE_SHIFT 20
#define MMU_PAGE_SIZE (1UL << MMU_PAGE_SHIFT)
#define MMU_PAGE_ADDR_MASK (~(MMU_PAGE_SIZE - 1))
#define MMU_VMR_CACHE_NONE \
(SYSREG_BF(AP, 3) | SYSREG_BF(SZ, 3) | SYSREG_BIT(TLBELO_D))

1
arch/avr32/include/asm/config.h
View file

@ -8,5 +8,6 @@
#define _ASM_CONFIG_H_
#define CONFIG_NEEDS_MANUAL_RELOC
#define CONFIG_SYS_GENERIC_GLOBAL_DATA
#endif

7
arch/avr32/include/asm/dma-mapping.h
View file

@ -14,7 +14,12 @@ enum dma_data_direction {
DMA_TO_DEVICE = 1,
DMA_FROM_DEVICE = 2,
};
extern void *dma_alloc_coherent(size_t len, unsigned long *handle);
static inline void *dma_alloc_coherent(size_t len, unsigned long *handle)
{
*handle = (unsigned long)memalign(ARCH_DMA_MINALIGN, len);
return (void *)*handle;
}
static inline unsigned long dma_map_single(volatile void *vaddr, size_t len,
enum dma_data_direction dir)

1
arch/avr32/include/asm/global_data.h
View file

@ -8,7 +8,6 @@
/* Architecture-specific global data */
struct arch_global_data {
unsigned long stack_end; /* highest stack address */
unsigned long cpu_hz; /* cpu core clock frequency */
};

10
arch/avr32/include/asm/u-boot.h
View file

@ -6,6 +6,11 @@
#ifndef __ASM_U_BOOT_H__
#define __ASM_U_BOOT_H__ 1
#ifdef CONFIG_SYS_GENERIC_BOARD
/* Use the generic board which requires a unified bd_info */
#include <asm-generic/u-boot.h>
#else
typedef struct bd_info {
unsigned char bi_phy_id[4];
unsigned long bi_board_number;
@ -22,7 +27,12 @@ typedef struct bd_info {
#define bi_memstart bi_dram[0].start
#define bi_memsize bi_dram[0].size
#endif
/* For image.h:image_check_target_arch() */
#define IH_ARCH_DEFAULT IH_ARCH_AVR32
int arch_cpu_init(void);
int dram_init(void);
#endif /* __ASM_U_BOOT_H__ */

3
arch/avr32/lib/Makefile
View file

@ -8,6 +8,9 @@
#
obj-y += memset.o
ifndef CONFIG_SYS_GENERIC_BOARD
obj-y += board.o
endif
obj-$(CONFIG_CMD_BOOTM) += bootm.o
obj-y += interrupts.o
obj-y += dram_init.o

83
arch/avr32/lib/board.c
View file

@ -9,7 +9,6 @@
#include <stdio_dev.h>
#include <version.h>
#include <net.h>
#include <atmel_mci.h>
#ifdef CONFIG_BITBANGMII
#include <miiphy.h>
@ -30,6 +29,12 @@ DECLARE_GLOBAL_DATA_PTR;
unsigned long monitor_flash_len;
__weak void dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = gd->ram_size;
}
/* Weak aliases for optional board functions */
static int __do_nothing(void)
{
@ -38,57 +43,6 @@ static int __do_nothing(void)
int board_postclk_init(void) __attribute__((weak, alias("__do_nothing")));
int board_early_init_r(void) __attribute__((weak, alias("__do_nothing")));
/* provide cpu_mmc_init, to overwrite provide board_mmc_init */
int cpu_mmc_init(bd_t *bd)
{
/* This calls the atmel_mci_init in gen_atmel_mci.c */
return atmel_mci_init((void *)ATMEL_BASE_MMCI);
}
#ifdef CONFIG_SYS_DMA_ALLOC_LEN
#include <asm/arch/cacheflush.h>
#include <asm/io.h>
static unsigned long dma_alloc_start;
static unsigned long dma_alloc_end;
static unsigned long dma_alloc_brk;
static void dma_alloc_init(void)
{
unsigned long monitor_addr;
monitor_addr = CONFIG_SYS_MONITOR_BASE + gd->reloc_off;
dma_alloc_end = monitor_addr - CONFIG_SYS_MALLOC_LEN;
dma_alloc_start = dma_alloc_end - CONFIG_SYS_DMA_ALLOC_LEN;
dma_alloc_brk = dma_alloc_start;
printf("DMA: Using memory from 0x%08lx to 0x%08lx\n",
dma_alloc_start, dma_alloc_end);
invalidate_dcache_range((unsigned long)cached(dma_alloc_start),
dma_alloc_end);
}
void *dma_alloc_coherent(size_t len, unsigned long *handle)
{
unsigned long paddr = dma_alloc_brk;
if (dma_alloc_brk + len > dma_alloc_end)
return NULL;
dma_alloc_brk = ((paddr + len + CONFIG_SYS_DCACHE_LINESZ - 1)
& ~(CONFIG_SYS_DCACHE_LINESZ - 1));
*handle = paddr;
return uncached(paddr);
}
#else
static inline void dma_alloc_init(void)
{
}
#endif
static int init_baudrate(void)
{
gd->baudrate = getenv_ulong("baudrate", 10, CONFIG_BAUDRATE);
@ -134,7 +88,6 @@ void board_init_f(ulong board_type)
unsigned long monitor_len;
unsigned long monitor_addr;
unsigned long addr;
long sdram_size;
/* Initialize the global data pointer */
memset(&gd_data, 0, sizeof(gd_data));
@ -142,17 +95,17 @@ void board_init_f(ulong board_type)
/* Perform initialization sequence */
board_early_init_f();
cpu_init();
arch_cpu_init();
board_postclk_init();
env_init();
init_baudrate();
serial_init();
console_init_f();
display_banner();
sdram_size = initdram(board_type);
dram_init();
/* If we have no SDRAM, we can't go on */
if (sdram_size <= 0)
if (gd->ram_size <= 0)
panic("No working SDRAM available\n");
/*
@ -166,7 +119,7 @@ void board_init_f(ulong board_type)
* - global data struct
* - stack
*/
addr = CONFIG_SYS_SDRAM_BASE + sdram_size;
addr = CONFIG_SYS_SDRAM_BASE + gd->ram_size;
monitor_len = (char *)(&__bss_end) - _text;
/*
@ -180,12 +133,6 @@ void board_init_f(ulong board_type)
/* Reserve memory for malloc() */
addr -= CONFIG_SYS_MALLOC_LEN;
#ifdef CONFIG_SYS_DMA_ALLOC_LEN
/* Reserve DMA memory (must be cache aligned) */
addr &= ~(CONFIG_SYS_DCACHE_LINESZ - 1);
addr -= CONFIG_SYS_DMA_ALLOC_LEN;
#endif
#ifdef CONFIG_LCD
#ifdef CONFIG_FB_ADDR
printf("LCD: Frame buffer allocated at preset 0x%08x\n",
@ -210,16 +157,11 @@ void board_init_f(ulong board_type)
/* And finally, a new, bigger stack. */
new_sp = (unsigned long *)addr;
gd->arch.stack_end = addr;
gd->start_addr_sp = addr;
*(--new_sp) = 0;
*(--new_sp) = 0;
/*
* Initialize the board information struct with the
* information we have.
*/
bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
bd->bi_dram[0].size = sdram_size;
dram_init_banksize();
memcpy(new_gd, gd, sizeof(gd_t));
@ -264,7 +206,6 @@ void board_init_r(gd_t *new_gd, ulong dest_addr)
/* The malloc area is right below the monitor image in RAM */
mem_malloc_init(CONFIG_SYS_MONITOR_BASE + gd->reloc_off -
CONFIG_SYS_MALLOC_LEN, CONFIG_SYS_MALLOC_LEN);
dma_alloc_init();
enable_interrupts();

17
arch/avr32/lib/dram_init.c Normal file
View file

@ -0,0 +1,17 @@
/*
* Copyright (C) 2015 Andreas Bießmann <andreas.devel@googlemail.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
DECLARE_GLOBAL_DATA_PTR;
int dram_init(void)
{
/* check for the maximum amount of memory possible on AP7000 devices */
gd->ram_size = get_ram_size(
(void *)CONFIG_SYS_SDRAM_BASE,
(256<<20));
return 0;
}

5
arch/avr32/lib/interrupts.c
View file

@ -7,6 +7,11 @@
#include <asm/sysreg.h>
int interrupt_init(void)
{
return 0;
}
void enable_interrupts(void)
{
asm volatile("csrf %0" : : "n"(SYSREG_GM_OFFSET));

1
arch/powerpc/lib/Makefile
View file

@ -40,6 +40,7 @@ obj-y += extable.o
obj-y += interrupts.o
obj-$(CONFIG_CMD_KGDB) += kgdb.o
obj-$(CONFIG_CMD_IDE) += ide.o
obj-y += stack.o
obj-y += time.o
# Don't include the MPC5xxx special memcpy into the

31
arch/powerpc/lib/stack.c Normal file
View file

@ -0,0 +1,31 @@
/*
* Copyright (c) 2015 Andreas Bießmann <andreas.devel@googlemail.com>
*
* Copyright (c) 2011 The Chromium OS Authors.
* (C) Copyright 2002-2006
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
DECLARE_GLOBAL_DATA_PTR;
int arch_reserve_stacks(void)
{
ulong *s;
/* setup stack pointer for exceptions */
gd->irq_sp = gd->start_addr_sp;
/* Clear initial stack frame */
s = (ulong *)gd->start_addr_sp;
*s = 0; /* Terminate back chain */
*++s = 0; /* NULL return address */
return 0;
}

32
board/atmel/atngw100/atngw100.c
View file

@ -18,14 +18,14 @@ DECLARE_GLOBAL_DATA_PTR;
struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = {
{
.virt_pgno = CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT,
.nr_pages = CONFIG_SYS_FLASH_SIZE >> PAGE_SHIFT,
.phys = (CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT)
.virt_pgno = CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT,
.nr_pages = CONFIG_SYS_FLASH_SIZE >> MMU_PAGE_SHIFT,
.phys = (CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT)
| MMU_VMR_CACHE_NONE,
}, {
.virt_pgno = CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT,
.nr_pages = EBI_SDRAM_SIZE >> PAGE_SHIFT,
.phys = (CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT)
.virt_pgno = CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT,
.nr_pages = EBI_SDRAM_SIZE >> MMU_PAGE_SHIFT,
.phys = (CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT)
| MMU_VMR_CACHE_WRBACK,
},
};
@ -52,6 +52,8 @@ int board_early_init_f(void)
hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE));
portmux_enable_ebi(16, 23, 0, PORTMUX_DRIVE_HIGH);
sdram_init(uncached(EBI_SDRAM_BASE), &sdram_config);
portmux_enable_usart1(PORTMUX_DRIVE_MIN);
#if defined(CONFIG_MACB)
@ -68,24 +70,6 @@ int board_early_init_f(void)
return 0;
}
phys_size_t initdram(int board_type)
{
unsigned long expected_size;
unsigned long actual_size;
void *sdram_base;
sdram_base = uncached(EBI_SDRAM_BASE);
expected_size = sdram_init(sdram_base, &sdram_config);
actual_size = get_ram_size(sdram_base, expected_size);
if (expected_size != actual_size)
printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
actual_size >> 20, expected_size >> 20);
return actual_size;
}
int board_early_init_r(void)
{
gd->bd->bi_phy_id[0] = 0x01;

39
board/atmel/atngw100mkii/atngw100mkii.c
View file

@ -23,21 +23,21 @@ DECLARE_GLOBAL_DATA_PTR;
struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = {
{
/* Atmel AT49BV640D 8 MiB x16 NOR flash on NCS0 */
.virt_pgno = CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT,
.nr_pages = CONFIG_SYS_FLASH_SIZE >> PAGE_SHIFT,
.phys = (CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT)
.virt_pgno = CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT,
.nr_pages = CONFIG_SYS_FLASH_SIZE >> MMU_PAGE_SHIFT,
.phys = (CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT)
| MMU_VMR_CACHE_NONE,
}, {
/* Micron MT29F2G16AAD 256 MiB x16 NAND flash on NCS3 */
.virt_pgno = EBI_SRAM_CS3_BASE >> PAGE_SHIFT,
.nr_pages = EBI_SRAM_CS3_SIZE >> PAGE_SHIFT,
.phys = (EBI_SRAM_CS3_BASE >> PAGE_SHIFT)
.virt_pgno = EBI_SRAM_CS3_BASE >> MMU_PAGE_SHIFT,
.nr_pages = EBI_SRAM_CS3_SIZE >> MMU_PAGE_SHIFT,
.phys = (EBI_SRAM_CS3_BASE >> MMU_PAGE_SHIFT)
| MMU_VMR_CACHE_NONE,
}, {
/* 2x16-bit ISSI IS42S16320B 64 MiB SDRAM (128 MiB total) */
.virt_pgno = CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT,
.nr_pages = EBI_SDRAM_SIZE >> PAGE_SHIFT,
.phys = (CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT)
.virt_pgno = CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT,
.nr_pages = EBI_SDRAM_SIZE >> MMU_PAGE_SHIFT,
.phys = (CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT)
| MMU_VMR_CACHE_WRBACK,
},
};
@ -69,6 +69,9 @@ int board_early_init_f(void)
portmux_select_gpio(PORTMUX_PORT_E, 1 << 23,
PORTMUX_DIR_OUTPUT | PORTMUX_INIT_HIGH
| PORTMUX_DRIVE_MIN);
sdram_init(uncached(EBI_SDRAM_BASE), &sdram_config);
portmux_enable_usart1(PORTMUX_DRIVE_MIN);
#if defined(CONFIG_MACB)
@ -85,24 +88,6 @@ int board_early_init_f(void)
return 0;
}
phys_size_t initdram(int board_type)
{
unsigned long expected_size;
unsigned long actual_size;
void *sdram_base;
sdram_base = uncached(EBI_SDRAM_BASE);
expected_size = sdram_init(sdram_base, &sdram_config);
actual_size = get_ram_size(sdram_base, expected_size);
if (expected_size != actual_size)
printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
actual_size >> 20, expected_size >> 20);
return actual_size;
}
int board_early_init_r(void)
{
gd->bd->bi_phy_id[0] = 0x01;

33
board/atmel/atstk1000/atstk1000.c
View file

@ -17,14 +17,14 @@ DECLARE_GLOBAL_DATA_PTR;
struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = {
{
.virt_pgno = CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT,
.nr_pages = CONFIG_SYS_FLASH_SIZE >> PAGE_SHIFT,
.phys = (CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT)
.virt_pgno = CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT,
.nr_pages = CONFIG_SYS_FLASH_SIZE >> MMU_PAGE_SHIFT,
.phys = (CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT)
| MMU_VMR_CACHE_NONE,
}, {
.virt_pgno = CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT,
.nr_pages = EBI_SDRAM_SIZE >> PAGE_SHIFT,
.phys = (CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT)
.virt_pgno = CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT,
.nr_pages = EBI_SDRAM_SIZE >> MMU_PAGE_SHIFT,
.phys = (CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT)
| MMU_VMR_CACHE_WRBACK,
},
};
@ -78,7 +78,10 @@ int board_early_init_f(void)
hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE));
portmux_enable_ebi(sdram_config.data_bits, 23, 0, PORTMUX_DRIVE_HIGH);
sdram_init(uncached(EBI_SDRAM_BASE), &sdram_config);
portmux_enable_usart1(PORTMUX_DRIVE_MIN);
#if defined(CONFIG_MACB)
portmux_enable_macb0(PORTMUX_MACB_MII, PORTMUX_DRIVE_LOW);
portmux_enable_macb1(PORTMUX_MACB_MII, PORTMUX_DRIVE_LOW);
@ -90,24 +93,6 @@ int board_early_init_f(void)
return 0;
}
phys_size_t initdram(int board_type)
{
unsigned long expected_size;
unsigned long actual_size;
void *sdram_base;
sdram_base = uncached(EBI_SDRAM_BASE);
expected_size = sdram_init(sdram_base, &sdram_config);
actual_size = get_ram_size(sdram_base, expected_size);
if (expected_size != actual_size)
printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
actual_size >> 20, expected_size >> 20);
return actual_size;
}
int board_early_init_r(void)
{
gd->bd->bi_phy_id[0] = 0x10;

33
board/earthlcd/favr-32-ezkit/favr-32-ezkit.c
View file

@ -17,14 +17,14 @@ DECLARE_GLOBAL_DATA_PTR;
struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = {
{
.virt_pgno = CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT,
.nr_pages = CONFIG_SYS_FLASH_SIZE >> PAGE_SHIFT,
.phys = (CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT)
.virt_pgno = CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT,
.nr_pages = CONFIG_SYS_FLASH_SIZE >> MMU_PAGE_SHIFT,
.phys = (CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT)
| MMU_VMR_CACHE_NONE,
}, {
.virt_pgno = CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT,
.nr_pages = EBI_SDRAM_SIZE >> PAGE_SHIFT,
.phys = (CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT)
.virt_pgno = CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT,
.nr_pages = EBI_SDRAM_SIZE >> MMU_PAGE_SHIFT,
.phys = (CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT)
| MMU_VMR_CACHE_WRBACK,
},
};
@ -52,6 +52,9 @@ int board_early_init_f(void)
hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE));
portmux_enable_ebi(32, 23, 0, PORTMUX_DRIVE_HIGH);
sdram_init(uncached(EBI_SDRAM_BASE), &sdram_config);
portmux_enable_usart3(PORTMUX_DRIVE_MIN);
#if defined(CONFIG_MACB)
portmux_enable_macb0(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH);
@ -63,24 +66,6 @@ int board_early_init_f(void)
return 0;
}
phys_size_t initdram(int board_type)
{
unsigned long expected_size;
unsigned long actual_size;
void *sdram_base;
sdram_base = uncached(EBI_SDRAM_BASE);
expected_size = sdram_init(sdram_base, &sdram_config);
actual_size = get_ram_size(sdram_base, expected_size);
if (expected_size != actual_size)
printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
actual_size >> 20, expected_size >> 20);
return actual_size;
}
int board_early_init_r(void)
{
gd->bd->bi_phy_id[0] = 0x01;

32
board/in-circuit/grasshopper/grasshopper.c
View file

@ -18,14 +18,14 @@ DECLARE_GLOBAL_DATA_PTR;
struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = {
{
.virt_pgno = CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT,
.nr_pages = CONFIG_SYS_FLASH_SIZE >> PAGE_SHIFT,
.phys = (CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT)
.virt_pgno = CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT,
.nr_pages = CONFIG_SYS_FLASH_SIZE >> MMU_PAGE_SHIFT,
.phys = (CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT)
| MMU_VMR_CACHE_NONE,
}, {
.virt_pgno = CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT,
.nr_pages = EBI_SDRAM_SIZE >> PAGE_SHIFT,
.phys = (CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT)
.virt_pgno = CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT,
.nr_pages = EBI_SDRAM_SIZE >> MMU_PAGE_SHIFT,
.phys = (CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT)
| MMU_VMR_CACHE_WRBACK,
},
};
@ -53,6 +53,8 @@ int board_early_init_f(void)
hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE));
portmux_enable_ebi(SDRAM_DATA_32BIT, 23, 0, PORTMUX_DRIVE_HIGH);
sdram_init(uncached(EBI_SDRAM_BASE), &sdram_config);
portmux_enable_usart0(PORTMUX_DRIVE_MIN);
portmux_enable_usart1(PORTMUX_DRIVE_MIN);
#if defined(CONFIG_MACB)
@ -69,24 +71,6 @@ int board_early_init_f(void)
return 0;
}
phys_size_t initdram(int board_type)
{
unsigned long expected_size;
unsigned long actual_size;
void *sdram_base;
sdram_base = uncached(EBI_SDRAM_BASE);
expected_size = sdram_init(sdram_base, &sdram_config);
actual_size = get_ram_size(sdram_base, expected_size);
if (expected_size != actual_size)
printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
actual_size >> 20, expected_size >> 20);
return actual_size;
}
int board_early_init_r(void)
{
gd->bd->bi_phy_id[0] = 0x00;

38
board/mimc/mimc200/mimc200.c
View file

@ -20,19 +20,19 @@
struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = {
{
.virt_pgno = CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT,
.nr_pages = CONFIG_SYS_FLASH_SIZE >> PAGE_SHIFT,
.phys = (CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT)
.virt_pgno = CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT,
.nr_pages = CONFIG_SYS_FLASH_SIZE >> MMU_PAGE_SHIFT,
.phys = (CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT)
| MMU_VMR_CACHE_NONE,
}, {
.virt_pgno = EBI_SRAM_CS2_BASE >> PAGE_SHIFT,
.nr_pages = EBI_SRAM_CS2_SIZE >> PAGE_SHIFT,
.phys = (EBI_SRAM_CS2_BASE >> PAGE_SHIFT)
.virt_pgno = EBI_SRAM_CS2_BASE >> MMU_PAGE_SHIFT,
.nr_pages = EBI_SRAM_CS2_SIZE >> MMU_PAGE_SHIFT,
.phys = (EBI_SRAM_CS2_BASE >> MMU_PAGE_SHIFT)
| MMU_VMR_CACHE_NONE,
}, {
.virt_pgno = CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT,
.nr_pages = EBI_SDRAM_SIZE >> PAGE_SHIFT,
.phys = (CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT)
.virt_pgno = CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT,
.nr_pages = EBI_SDRAM_SIZE >> MMU_PAGE_SHIFT,
.phys = (CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT)
| MMU_VMR_CACHE_WRBACK,
},
};
@ -91,6 +91,8 @@ int board_early_init_f(void)
/* Enable 26 address bits and NCS2 */
portmux_enable_ebi(16, 26, PORTMUX_EBI_CS(2), PORTMUX_DRIVE_HIGH);
sdram_init(uncached(EBI_SDRAM_BASE), &sdram_config);
portmux_enable_usart1(PORTMUX_DRIVE_MIN);
/* de-assert "force sys reset" pin */
@ -151,24 +153,6 @@ int board_early_init_f(void)
return 0;
}
phys_size_t initdram(int board_type)
{
unsigned long expected_size;
unsigned long actual_size;
void *sdram_base;
sdram_base = uncached(EBI_SDRAM_BASE);
expected_size = sdram_init(sdram_base, &sdram_config);
actual_size = get_ram_size(sdram_base, expected_size);
if (expected_size != actual_size)
printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
actual_size >> 20, expected_size >> 20);
return actual_size;
}
int board_early_init_r(void)
{
gd->bd->bi_phy_id[0] = 0x01;

32
board/miromico/hammerhead/hammerhead.c
View file

@ -21,14 +21,14 @@ DECLARE_GLOBAL_DATA_PTR;
struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = {
{
.virt_pgno = CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT,
.nr_pages = CONFIG_SYS_FLASH_SIZE >> PAGE_SHIFT,
.phys = (CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT)
.virt_pgno = CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT,
.nr_pages = CONFIG_SYS_FLASH_SIZE >> MMU_PAGE_SHIFT,
.phys = (CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT)
| MMU_VMR_CACHE_NONE,
}, {
.virt_pgno = CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT,
.nr_pages = EBI_SDRAM_SIZE >> PAGE_SHIFT,
.phys = (CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT)
.virt_pgno = CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT,
.nr_pages = EBI_SDRAM_SIZE >> MMU_PAGE_SHIFT,
.phys = (CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT)
| MMU_VMR_CACHE_WRBACK,
},
};
@ -63,6 +63,8 @@ int board_early_init_f(void)
hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE));
portmux_enable_ebi(32, 23, 0, PORTMUX_DRIVE_HIGH);
sdram_init(uncached(EBI_SDRAM_BASE), &sdram_config);
portmux_enable_usart1(PORTMUX_DRIVE_MIN);
#if defined(CONFIG_MACB)
@ -74,24 +76,6 @@ int board_early_init_f(void)
return 0;
}
phys_size_t initdram(int board_type)
{
unsigned long expected_size;
unsigned long actual_size;
void *sdram_base;
sdram_base = uncached(EBI_SDRAM_BASE);
expected_size = sdram_init(sdram_base, &sdram_config);
actual_size = get_ram_size(sdram_base, expected_size);
if (expected_size != actual_size)
printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
actual_size >> 20, expected_size >> 20);
return actual_size;
}
int board_early_init_r(void)
{
gd->bd->bi_phy_id[0] = 0x01;

46
common/board_f.c
View file

@ -573,48 +573,22 @@ static int reserve_fdt(void)
return 0;
}
int arch_reserve_stacks(void)
{
return 0;
}
static int reserve_stacks(void)
{
#ifdef CONFIG_SPL_BUILD
# ifdef CONFIG_ARM
gd->start_addr_sp -= 128; /* leave 32 words for abort-stack */
gd->irq_sp = gd->start_addr_sp;
# endif
#else
# ifdef CONFIG_PPC
ulong *s;
# endif
/* setup stack pointer for exceptions */
/* make stack pointer 16-byte aligned */
gd->start_addr_sp -= 16;
gd->start_addr_sp &= ~0xf;
gd->irq_sp = gd->start_addr_sp;
/*
* Handle architecture-specific things here
* TODO(sjg@chromium.org): Perhaps create arch_reserve_stack()
* to handle this and put in arch/xxx/lib/stack.c
* let the architecture specific code tailor gd->start_addr_sp and
* gd->irq_sp
*/
# if defined(CONFIG_ARM) && !defined(CONFIG_ARM64)
# ifdef CONFIG_USE_IRQ
gd->start_addr_sp -= (CONFIG_STACKSIZE_IRQ + CONFIG_STACKSIZE_FIQ);
debug("Reserving %zu Bytes for IRQ stack at: %08lx\n",
CONFIG_STACKSIZE_IRQ + CONFIG_STACKSIZE_FIQ, gd->start_addr_sp);
/* 8-byte alignment for ARM ABI compliance */
gd->start_addr_sp &= ~0x07;
# endif
/* leave 3 words for abort-stack, plus 1 for alignment */
gd->start_addr_sp -= 16;
# elif defined(CONFIG_PPC)
/* Clear initial stack frame */
s = (ulong *) gd->start_addr_sp;
*s = 0; /* Terminate back chain */
*++s = 0; /* NULL return address */
# endif /* Architecture specific code */
return 0;
#endif
return arch_reserve_stacks();
}
static int display_new_sp(void)
@ -909,7 +883,7 @@ static init_fnc_t init_sequence_f[] = {
#endif
announce_dram_init,
/* TODO: unify all these dram functions? */
#if defined(CONFIG_ARM) || defined(CONFIG_X86) || defined(CONFIG_MICROBLAZE)
#if defined(CONFIG_ARM) || defined(CONFIG_X86) || defined(CONFIG_MICROBLAZE) || defined(CONFIG_AVR32)
dram_init, /* configure available RAM banks */
#endif
#if defined(CONFIG_MIPS) || defined(CONFIG_PPC)

28
common/board_r.c
View file

@ -55,6 +55,9 @@
#include <dm/root.h>
#include <linux/compiler.h>
#include <linux/err.h>
#ifdef CONFIG_AVR32
#include <asm/arch/mmu.h>
#endif
DECLARE_GLOBAL_DATA_PTR;
@ -459,6 +462,18 @@ static int initr_env(void)
return 0;
}
#ifdef CONFIG_SYS_BOOTPARAMS_LEN
static int initr_malloc_bootparams(void)
{
gd->bd->bi_boot_params = (ulong)malloc(CONFIG_SYS_BOOTPARAMS_LEN);
if (!gd->bd->bi_boot_params) {
puts("WARNING: Cannot allocate space for boot parameters\n");
return -ENOMEM;
}
return 0;
}
#endif
#ifdef CONFIG_SC3
/* TODO: with new initcalls, move this into the driver */
extern void sc3_read_eeprom(void);
@ -486,7 +501,7 @@ static int initr_api(void)
#endif
/* enable exceptions */
#ifdef CONFIG_ARM
#if defined(CONFIG_ARM) || defined(CONFIG_AVR32)
static int initr_enable_interrupts(void)
{
enable_interrupts();
@ -775,6 +790,9 @@ init_fnc_t init_sequence_r[] = {
initr_dataflash,
#endif
initr_env,
#ifdef CONFIG_SYS_BOOTPARAMS_LEN
initr_malloc_bootparams,
#endif
INIT_FUNC_WATCHDOG_RESET
initr_secondary_cpu,
#ifdef CONFIG_SC3
@ -810,10 +828,10 @@ init_fnc_t init_sequence_r[] = {
initr_kgdb,
#endif
interrupt_init,
#if defined(CONFIG_ARM)
#if defined(CONFIG_ARM) || defined(CONFIG_AVR32)
initr_enable_interrupts,
#endif
#if defined(CONFIG_X86) || defined(CONFIG_MICROBLAZE)
#if defined(CONFIG_X86) || defined(CONFIG_MICROBLAZE) || defined(CONFIG_AVR32)
timer_init, /* initialize timer */
#endif
#if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT)
@ -878,6 +896,10 @@ void board_init_r(gd_t *new_gd, ulong dest_addr)
int i;
#endif
#ifdef CONFIG_AVR32
mmu_init_r(dest_addr);
#endif
#if !defined(CONFIG_X86) && !defined(CONFIG_ARM) && !defined(CONFIG_ARM64)
gd = new_gd;
#endif

4
common/cmd_bdinfo.c
View file

@ -345,8 +345,8 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
bd_t *bd = gd->bd;
print_num("boot_params", (ulong)bd->bi_boot_params);
print_num("memstart", (ulong)bd->bi_memstart);
print_lnum("memsize", (u64)bd->bi_memsize);
print_num("memstart", (ulong)bd->bi_dram[0].start);
print_lnum("memsize", (u64)bd->bi_dram[0].size);
print_num("flashstart", (ulong)bd->bi_flashstart);
print_num("flashsize", (ulong)bd->bi_flashsize);
print_num("flashoffset", (ulong)bd->bi_flashoffset);

4
include/asm-generic/u-boot.h
View file

@ -32,6 +32,10 @@ typedef struct bd_info {
unsigned long bi_flashoffset; /* reserved area for startup monitor */
unsigned long bi_sramstart; /* start of SRAM memory */
unsigned long bi_sramsize; /* size of SRAM memory */
#ifdef CONFIG_AVR32
unsigned char bi_phy_id[4]; /* PHY address for ATAG_ETHERNET */
unsigned long bi_board_number;/* ATAG_BOARDINFO */
#endif
#ifdef CONFIG_ARM
unsigned long bi_arm_freq; /* arm frequency */
unsigned long bi_dsp_freq; /* dsp core frequency */

18
include/common.h
View file

@ -252,6 +252,24 @@ static inline int print_cpuinfo(void)
int update_flash_size(int flash_size);
int arch_early_init_r(void);
/**
* Reserve all necessary stacks
*
* This is used in generic board init sequence in common/board_f.c. Each
* architecture could provide this function to tailor the required stacks.
*
* On entry gd->start_addr_sp is pointing to the suggested top of the stack.
* The callee ensures gd->start_add_sp is 16-byte aligned, so architectures
* require only this can leave it untouched.
*
* On exit gd->start_addr_sp and gd->irq_sp should be set to the respective
* positions of the stack. The stack pointer(s) will be set to this later.
* gd->irq_sp is only required, if the architecture needs it.
*
* @return 0 if no error
*/
__weak int arch_reserve_stacks(void);
/**
* Show the DRAM size in a board-specific way
*

1
include/configs/atngw100.h
View file

@ -143,7 +143,6 @@
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE)
#define CONFIG_SYS_MALLOC_LEN (256*1024)
#define CONFIG_SYS_DMA_ALLOC_LEN (16384)
/* Allow 4MB for the kernel run-time image */
#define CONFIG_SYS_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000)

1
include/configs/atngw100mkii.h
View file

@ -164,7 +164,6 @@
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE)
#define CONFIG_SYS_MALLOC_LEN (256*1024)
#define CONFIG_SYS_DMA_ALLOC_LEN (16384)
/* Allow 4MB for the kernel run-time image */
#define CONFIG_SYS_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000)

5
include/configs/atstk1002.h
View file

@ -104,6 +104,10 @@
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
/* generic board */
#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_BOARD_EARLY_INIT_R
/*
* Command line configuration.
@ -158,7 +162,6 @@
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE)
#define CONFIG_SYS_MALLOC_LEN (256*1024)
#define CONFIG_SYS_DMA_ALLOC_LEN (16384)
/* Allow 4MB for the kernel run-time image */
#define CONFIG_SYS_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000)

1
include/configs/atstk1006.h
View file

@ -159,7 +159,6 @@
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE)
#define CONFIG_SYS_MALLOC_LEN (256*1024)
#define CONFIG_SYS_DMA_ALLOC_LEN (16384)
/* Allow 4MB for the kernel run-time image */
#define CONFIG_SYS_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000)

1
include/configs/favr-32-ezkit.h
View file

@ -162,7 +162,6 @@
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE)
#define CONFIG_SYS_MALLOC_LEN (256*1024)
#define CONFIG_SYS_DMA_ALLOC_LEN (16384)
/* Allow 4MB for the kernel run-time image */
#define CONFIG_SYS_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000)

5
include/configs/grasshopper.h
View file

@ -62,6 +62,10 @@
#define CONFIG_USART_BASE ATMEL_BASE_USART1
#define CONFIG_USART_ID 1
#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_BOARD_EARLY_INIT_R
/* User serviceable stuff */
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
@ -151,7 +155,6 @@
CONFIG_SYS_INTRAM_SIZE)
#define CONFIG_SYS_MALLOC_LEN (256*1024)
#define CONFIG_SYS_DMA_ALLOC_LEN (16384)
/* Allow 4MB for the kernel run-time image */
#define CONFIG_SYS_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000)

1
include/configs/hammerhead.h
View file

@ -137,7 +137,6 @@
#define CONFIG_SYS_MALLOC_LEN (256*1024)
#define CONFIG_SYS_DMA_ALLOC_LEN (16384)
/* Allow 4MB for the kernel run-time image */
#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x00400000)

1
include/configs/mimc200.h
View file

@ -157,7 +157,6 @@
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE)
#define CONFIG_SYS_MALLOC_LEN (1024*1024)
#define CONFIG_SYS_DMA_ALLOC_LEN (16384)
/* Allow 4MB for the kernel run-time image */
#define CONFIG_SYS_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000)