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clk: mt7622: add needed clocks for ssusb-node

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MT7622 needs additional clock definitions to work properly

Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
This commit is contained in:
Frank Wunderlich 2020-08-20 16:37:55 +02:00 • committed by Tom Rini
parent a7e0ef15dd
commit 9f25aa13ea
1 changed files with 42 additions and 0 deletions
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42
drivers/clk/mediatek/clk-mt7622.c
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@ -521,6 +521,20 @@ static const struct mtk_gate_regs sgmii_cg_regs = {
.flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \ .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \
} }
static const struct mtk_gate_regs ssusb_cg_regs = {
.set_ofs = 0x30,
.clr_ofs = 0x30,
.sta_ofs = 0x30,
};
#define GATE_SSUSB(_id, _parent, _shift) { \
.id = _id, \
.parent = _parent, \
.regs = &ssusb_cg_regs, \
.shift = _shift, \
.flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \
}
static const struct mtk_gate sgmii_cgs[] = { static const struct mtk_gate sgmii_cgs[] = {
GATE_SGMII(CLK_SGMII_TX250M_EN, CLK_TOP_SSUSB_TX250M, 2), GATE_SGMII(CLK_SGMII_TX250M_EN, CLK_TOP_SSUSB_TX250M, 2),
GATE_SGMII(CLK_SGMII_RX250M_EN, CLK_TOP_SSUSB_EQ_RX250M, 3), GATE_SGMII(CLK_SGMII_RX250M_EN, CLK_TOP_SSUSB_EQ_RX250M, 3),
@ -528,6 +542,15 @@ static const struct mtk_gate sgmii_cgs[] = {
GATE_SGMII(CLK_SGMII_CDR_FB, CLK_TOP_SSUSB_CDR_FB, 5), GATE_SGMII(CLK_SGMII_CDR_FB, CLK_TOP_SSUSB_CDR_FB, 5),
}; };
static const struct mtk_gate ssusb_cgs[] = {
GATE_SSUSB(CLK_SSUSB_U2_PHY_1P_EN, CLK_TOP_TO_U2_PHY_1P, 0),
GATE_SSUSB(CLK_SSUSB_U2_PHY_EN, CLK_TOP_TO_U2_PHY, 1),
GATE_SSUSB(CLK_SSUSB_REF_EN, CLK_TOP_TO_USB3_REF, 5),
GATE_SSUSB(CLK_SSUSB_SYS_EN, CLK_TOP_TO_USB3_SYS, 6),
GATE_SSUSB(CLK_SSUSB_MCU_EN, CLK_TOP_AXI_SEL, 7),
GATE_SSUSB(CLK_SSUSB_DMA_EN, CLK_TOP_HIF_SEL, 8),
};
static const struct mtk_clk_tree mt7622_clk_tree = { static const struct mtk_clk_tree mt7622_clk_tree = {
.xtal_rate = 25 * MHZ, .xtal_rate = 25 * MHZ,
.xtal2_rate = 25 * MHZ, .xtal2_rate = 25 * MHZ,
@ -630,6 +653,11 @@ static int mt7622_sgmiisys_probe(struct udevice *dev)
return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, sgmii_cgs); return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, sgmii_cgs);
} }
static int mt7622_ssusbsys_probe(struct udevice *dev)
{
return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, ssusb_cgs);
}
static const struct udevice_id mt7622_apmixed_compat[] = { static const struct udevice_id mt7622_apmixed_compat[] = {
{ .compatible = "mediatek,mt7622-apmixedsys" }, { .compatible = "mediatek,mt7622-apmixedsys" },
{ } { }
@ -670,6 +698,11 @@ static const struct udevice_id mt7622_mcucfg_compat[] = {
{ } { }
}; };
static const struct udevice_id mt7622_ssusbsys_compat[] = {
{ .compatible = "mediatek,mt7622-ssusbsys" },
{ }
};
U_BOOT_DRIVER(mtk_mcucfg) = { U_BOOT_DRIVER(mtk_mcucfg) = {
.name = "mt7622-mcucfg", .name = "mt7622-mcucfg",
.id = UCLASS_SYSCON, .id = UCLASS_SYSCON,
@ -746,3 +779,12 @@ U_BOOT_DRIVER(mtk_clk_sgmiisys) = {
.priv_auto_alloc_size = sizeof(struct mtk_cg_priv), .priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
.ops = &mtk_clk_gate_ops, .ops = &mtk_clk_gate_ops,
}; };
U_BOOT_DRIVER(mtk_clk_ssusbsys) = {
.name = "mt7622-clock-ssusbsys",
.id = UCLASS_CLK,
.of_match = mt7622_ssusbsys_compat,
.probe = mt7622_ssusbsys_probe,
.priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
.ops = &mtk_clk_gate_ops,
};