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ARM: UniPhier: remove unnecessary cache coherency code
Cache coherency for SMP is cared by Linux. In U-Boot, the secondary CPU(s) are just sleeping. Nothing in memory is shared with the primary CPU. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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1 changed files with 1 additions and 23 deletions
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@ -1,7 +1,5 @@
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/*
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/*
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* Copyright (C) 2012-2015 Panasonic Corporation
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* Copyright (C) 2012-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
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* Copyright (C) 2015 Socionext Inc.
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* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
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*
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*
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* SPDX-License-Identifier: GPL-2.0+
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* SPDX-License-Identifier: GPL-2.0+
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*/
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*/
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@ -67,20 +65,6 @@ secondary_startup:
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* jump to Linux
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* jump to Linux
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* kick secondaries ---(sev)---> jump to Linux
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* kick secondaries ---(sev)---> jump to Linux
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*/
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*/
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/*
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* ACTLR (Auxiliary Control Register) for Cortex-A9
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* bit[9] Parity on
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* bit[8] Alloc in one way
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* bit[7] EXCL (Exclusive cache bit)
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* bit[6] SMP
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* bit[3] Write full line of zeros mode
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* bit[2] L1 prefetch enable
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* bit[1] L2 prefetch enable
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* bit[0] FW (Cache and TLB maintenance broadcast)
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*/
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mrc p15, 0, r0, c1, c0, 1 @ ACTLR (Auxiliary Control Register)
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orr r0, r0, #0x41 @ enable SMP, FW bit
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mcr p15, 0, r0, c1, c0, 1
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/* branch by CPU ID */
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/* branch by CPU ID */
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mrc p15, 0, r0, c0, c0, 5 @ MPIDR (Multiprocessor Affinity Register)
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mrc p15, 0, r0, c0, c0, 5 @ MPIDR (Multiprocessor Affinity Register)
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@ -112,12 +96,6 @@ primary_cpu:
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str r0, [r1]
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str r0, [r1]
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ldr r0, [r1] @ make sure str is complete before sev
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ldr r0, [r1] @ make sure str is complete before sev
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sev @ kick the secondary CPU
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sev @ kick the secondary CPU
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mrc p15, 4, r1, c15, c0, 0 @ Configuration Base Address Register
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bfc r1, #0, #13 @ clear bit 12-0
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mov r0, #-1
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str r0, [r1, #SCU_INV_ALL] @ SCU Invalidate All Register
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mov r0, #1 @ SCU enable
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str r0, [r1, #SCU_CTRL] @ SCU Control Register
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#endif
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#endif
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bl setup_init_ram @ RAM area for temporary stack pointer
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bl setup_init_ram @ RAM area for temporary stack pointer
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