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mips: traps: Set WG bit in EBase register on Octeon

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WG (bit 11) needs to be set on Octeon to enable writing bits 63:30 of
the exception base register.

Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Stefan Roese 2020-05-14 11:59:06 +02:00 • committed by Daniel Schwierzeck
parent a414281da4
commit a02bc1f992
2 changed files with 5 additions and 0 deletions
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1
arch/mips/include/asm/mipsregs.h
View file

@ -366,6 +366,7 @@
* Bits in the coprocessor 0 EBase register. * Bits in the coprocessor 0 EBase register.
*/ */
#define EBASE_CPUNUM 0x3ff #define EBASE_CPUNUM 0x3ff
#define EBASE_WG (_ULCAST_(1) << 11)
/* /*
* Bits in the coprocessor 0 config register. * Bits in the coprocessor 0 config register.

4
arch/mips/lib/traps.c
View file

@ -108,6 +108,10 @@ void trap_init(ulong reloc_addr)
saved_ebase = read_c0_ebase() & 0xfffff000; saved_ebase = read_c0_ebase() & 0xfffff000;
/* Set WG bit on Octeon to enable writing to bits 63:30 */
if (IS_ENABLED(CONFIG_ARCH_OCTEON))
ebase |= EBASE_WG;
write_c0_ebase(ebase); write_c0_ebase(ebase);
clear_c0_status(ST0_BEV); clear_c0_status(ST0_BEV);
execution_hazard_barrier(); execution_hazard_barrier();