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https://github.com/Fishwaldo/u-boot.git
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ATMEL: fix dataflash (dirty) this file should be converted to struct SoC access
Signed-off-by: Reinhard Meyer <u-boot@emk-elektronik.de>
This commit is contained in:
Reinhard Meyer
Albert ARIBAUD
parent
86592f6059
commit
a0cfd18876
2 changed files with 57 additions and 38 deletions
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@ -21,13 +21,21 @@
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#include <common.h>
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#ifndef CONFIG_AT91_LEGACY
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#define CONFIG_AT91_LEGACY
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#warning Please update to use C structur SoC access !
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# define CONFIG_ATMEL_LEGACY
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# warning Please update to use C structure SoC access !
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#endif
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#include <asm/arch/hardware.h>
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#include <common.h>
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#include <spi.h>
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#include <malloc.h>
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#include <asm/io.h>
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#include <asm/arch/clk.h>
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#include <asm/arch/hardware.h>
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#include "atmel_spi.h"
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#include <asm/arch/gpio.h>
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#include <asm/arch/io.h>
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#include <asm/arch/at91_pio.h>
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#include <asm/arch/at91_spi.h>
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@ -41,18 +49,18 @@
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void AT91F_SpiInit(void)
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{
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/* Reset the SPI */
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writel(AT91_SPI_SWRST, AT91_BASE_SPI + AT91_SPI_CR);
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writel(AT91_SPI_SWRST, ATMEL_BASE_SPI0 + AT91_SPI_CR);
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/* Configure SPI in Master Mode with No CS selected !!! */
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writel(AT91_SPI_MSTR | AT91_SPI_MODFDIS | AT91_SPI_PCS,
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AT91_BASE_SPI + AT91_SPI_MR);
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ATMEL_BASE_SPI0 + AT91_SPI_MR);
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/* Configure CS0 */
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writel(AT91_SPI_NCPHA |
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(AT91_SPI_DLYBS & DATAFLASH_TCSS) |
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(AT91_SPI_DLYBCT & DATAFLASH_TCHS) |
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((get_mck_clk_rate() / AT91_SPI_CLK) << 8),
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AT91_BASE_SPI + AT91_SPI_CSR(0));
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ATMEL_BASE_SPI0 + AT91_SPI_CSR(0));
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#ifdef CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS1
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/* Configure CS1 */
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@ -60,7 +68,7 @@ void AT91F_SpiInit(void)
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(AT91_SPI_DLYBS & DATAFLASH_TCSS) |
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(AT91_SPI_DLYBCT & DATAFLASH_TCHS) |
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((get_mck_clk_rate() / AT91_SPI_CLK) << 8),
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AT91_BASE_SPI + AT91_SPI_CSR(1));
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ATMEL_BASE_SPI0 + AT91_SPI_CSR(1));
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#endif
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#ifdef CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS2
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/* Configure CS2 */
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@ -68,7 +76,7 @@ void AT91F_SpiInit(void)
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(AT91_SPI_DLYBS & DATAFLASH_TCSS) |
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(AT91_SPI_DLYBCT & DATAFLASH_TCHS) |
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((get_mck_clk_rate() / AT91_SPI_CLK) << 8),
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AT91_BASE_SPI + AT91_SPI_CSR(2));
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ATMEL_BASE_SPI0 + AT91_SPI_CSR(2));
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#endif
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#ifdef CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3
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/* Configure CS3 */
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@ -76,21 +84,22 @@ void AT91F_SpiInit(void)
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(AT91_SPI_DLYBS & DATAFLASH_TCSS) |
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(AT91_SPI_DLYBCT & DATAFLASH_TCHS) |
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((get_mck_clk_rate() / AT91_SPI_CLK) << 8),
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AT91_BASE_SPI + AT91_SPI_CSR(3));
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ATMEL_BASE_SPI0 + AT91_SPI_CSR(3));
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#endif
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/* SPI_Enable */
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writel(AT91_SPI_SPIEN, AT91_BASE_SPI + AT91_SPI_CR);
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writel(AT91_SPI_SPIEN, ATMEL_BASE_SPI0 + AT91_SPI_CR);
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while (!(readl(AT91_BASE_SPI + AT91_SPI_SR) & AT91_SPI_SPIENS));
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while (!(readl(ATMEL_BASE_SPI0 + AT91_SPI_SR) & AT91_SPI_SPIENS))
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;
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/*
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* Add tempo to get SPI in a safe state.
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* Should not be needed for new silicon (Rev B)
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*/
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udelay(500000);
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readl(AT91_BASE_SPI + AT91_SPI_SR);
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readl(AT91_BASE_SPI + AT91_SPI_RDR);
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readl(ATMEL_BASE_SPI0 + AT91_SPI_SR);
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readl(ATMEL_BASE_SPI0 + AT91_SPI_RDR);
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}
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@ -100,33 +109,33 @@ void AT91F_SpiEnable(int cs)
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switch (cs) {
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case 0: /* Configure SPI CS0 for Serial DataFlash AT45DBxx */
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mode = readl(AT91_BASE_SPI + AT91_SPI_MR);
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mode = readl(ATMEL_BASE_SPI0 + AT91_SPI_MR);
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mode &= 0xFFF0FFFF;
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writel(mode | ((AT91_SPI_PCS0_DATAFLASH_CARD<<16) & AT91_SPI_PCS),
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AT91_BASE_SPI + AT91_SPI_MR);
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ATMEL_BASE_SPI0 + AT91_SPI_MR);
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break;
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case 1: /* Configure SPI CS1 for Serial DataFlash AT45DBxx */
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mode = readl(AT91_BASE_SPI + AT91_SPI_MR);
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mode = readl(ATMEL_BASE_SPI0 + AT91_SPI_MR);
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mode &= 0xFFF0FFFF;
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writel(mode | ((AT91_SPI_PCS1_DATAFLASH_CARD<<16) & AT91_SPI_PCS),
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AT91_BASE_SPI + AT91_SPI_MR);
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ATMEL_BASE_SPI0 + AT91_SPI_MR);
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break;
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case 2: /* Configure SPI CS2 for Serial DataFlash AT45DBxx */
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mode = readl(AT91_BASE_SPI + AT91_SPI_MR);
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mode = readl(ATMEL_BASE_SPI0 + AT91_SPI_MR);
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mode &= 0xFFF0FFFF;
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writel(mode | ((AT91_SPI_PCS2_DATAFLASH_CARD<<16) & AT91_SPI_PCS),
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AT91_BASE_SPI + AT91_SPI_MR);
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ATMEL_BASE_SPI0 + AT91_SPI_MR);
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break;
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case 3:
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mode = readl(AT91_BASE_SPI + AT91_SPI_MR);
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mode = readl(ATMEL_BASE_SPI0 + AT91_SPI_MR);
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mode &= 0xFFF0FFFF;
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writel(mode | ((AT91_SPI_PCS3_DATAFLASH_CARD<<16) & AT91_SPI_PCS),
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AT91_BASE_SPI + AT91_SPI_MR);
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ATMEL_BASE_SPI0 + AT91_SPI_MR);
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break;
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}
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/* SPI_Enable */
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writel(AT91_SPI_SPIEN, AT91_BASE_SPI + AT91_SPI_CR);
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writel(AT91_SPI_SPIEN, ATMEL_BASE_SPI0 + AT91_SPI_CR);
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}
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unsigned int AT91F_SpiWrite1(AT91PS_DataflashDesc pDesc);
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@ -134,37 +143,48 @@ unsigned int AT91F_SpiWrite1(AT91PS_DataflashDesc pDesc);
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unsigned int AT91F_SpiWrite(AT91PS_DataflashDesc pDesc)
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{
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unsigned int timeout;
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unsigned int timebase;
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pDesc->state = BUSY;
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writel(AT91_SPI_TXTDIS + AT91_SPI_RXTDIS, AT91_BASE_SPI + AT91_SPI_PTCR);
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writel(AT91_SPI_TXTDIS + AT91_SPI_RXTDIS,
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ATMEL_BASE_SPI0 + AT91_SPI_PTCR);
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/* Initialize the Transmit and Receive Pointer */
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writel((unsigned int)pDesc->rx_cmd_pt, AT91_BASE_SPI + AT91_SPI_RPR);
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writel((unsigned int)pDesc->tx_cmd_pt, AT91_BASE_SPI + AT91_SPI_TPR);
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writel((unsigned int)pDesc->rx_cmd_pt,
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ATMEL_BASE_SPI0 + AT91_SPI_RPR);
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writel((unsigned int)pDesc->tx_cmd_pt,
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ATMEL_BASE_SPI0 + AT91_SPI_TPR);
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/* Intialize the Transmit and Receive Counters */
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writel(pDesc->rx_cmd_size, AT91_BASE_SPI + AT91_SPI_RCR);
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writel(pDesc->tx_cmd_size, AT91_BASE_SPI + AT91_SPI_TCR);
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writel(pDesc->rx_cmd_size, ATMEL_BASE_SPI0 + AT91_SPI_RCR);
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writel(pDesc->tx_cmd_size, ATMEL_BASE_SPI0 + AT91_SPI_TCR);
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if (pDesc->tx_data_size != 0) {
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/* Initialize the Next Transmit and Next Receive Pointer */
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writel((unsigned int)pDesc->rx_data_pt, AT91_BASE_SPI + AT91_SPI_RNPR);
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writel((unsigned int)pDesc->tx_data_pt, AT91_BASE_SPI + AT91_SPI_TNPR);
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writel((unsigned int)pDesc->rx_data_pt,
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ATMEL_BASE_SPI0 + AT91_SPI_RNPR);
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writel((unsigned int)pDesc->tx_data_pt,
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ATMEL_BASE_SPI0 + AT91_SPI_TNPR);
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/* Intialize the Next Transmit and Next Receive Counters */
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writel(pDesc->rx_data_size, AT91_BASE_SPI + AT91_SPI_RNCR);
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writel(pDesc->tx_data_size, AT91_BASE_SPI + AT91_SPI_TNCR);
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writel(pDesc->rx_data_size,
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ATMEL_BASE_SPI0 + AT91_SPI_RNCR);
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writel(pDesc->tx_data_size,
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ATMEL_BASE_SPI0 + AT91_SPI_TNCR);
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}
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/* arm simple, non interrupt dependent timer */
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reset_timer_masked();
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timebase = get_timer(0);
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timeout = 0;
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writel(AT91_SPI_TXTEN + AT91_SPI_RXTEN, AT91_BASE_SPI + AT91_SPI_PTCR);
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while (!(readl(AT91_BASE_SPI + AT91_SPI_SR) & AT91_SPI_RXBUFF) &&
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((timeout = get_timer_masked()) < CONFIG_SYS_SPI_WRITE_TOUT));
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writel(AT91_SPI_TXTDIS + AT91_SPI_RXTDIS, AT91_BASE_SPI + AT91_SPI_PTCR);
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writel(AT91_SPI_TXTEN + AT91_SPI_RXTEN,
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ATMEL_BASE_SPI0 + AT91_SPI_PTCR);
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while (!(readl(ATMEL_BASE_SPI0 + AT91_SPI_SR) & AT91_SPI_RXBUFF) &&
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((timeout = get_timer(timebase)) < CONFIG_SYS_SPI_WRITE_TOUT))
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;
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writel(AT91_SPI_TXTDIS + AT91_SPI_RXTDIS,
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ATMEL_BASE_SPI0 + AT91_SPI_PTCR);
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pDesc->state = IDLE;
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if (timeout >= CONFIG_SYS_SPI_WRITE_TOUT) {
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@ -34,7 +34,6 @@
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#define _DataFlash_h
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#include <asm/arch/hardware.h>
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#include "config.h"
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/*number of protected area*/
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