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strider: use optimised bus timing for FPGA access
Use optimised bus timing for FPGA access. Signed-off-by: Reinhard Pfau <reinhard.pfau@gdsys.cc> Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
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4709805657
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a119357c43
1 changed files with 5 additions and 6 deletions
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@ -279,14 +279,13 @@
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| BR_PS_16 /* 16 bit port */ \
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| BR_PS_16 /* 16 bit port */ \
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| BR_MS_GPCM /* MSEL = GPCM */ \
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| BR_MS_GPCM /* MSEL = GPCM */ \
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| BR_V) /* valid */
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| BR_V) /* valid */
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#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_FPGA0_SIZE) \
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#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_FPGA0_SIZE) \
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| OR_UPM_XAM \
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| OR_UPM_XAM \
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| OR_GPCM_CSNT \
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| OR_GPCM_CSNT \
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| OR_GPCM_ACS_DIV2 \
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| OR_GPCM_SCY_5 \
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| OR_GPCM_XACS \
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| OR_GPCM_TRLX_CLEAR \
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| OR_GPCM_SCY_15 \
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| OR_GPCM_EHTR_CLEAR)
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| OR_GPCM_TRLX_SET \
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| OR_GPCM_EHTR_SET)
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#define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE
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#define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE
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#define CONFIG_SYS_FPGA_DONE(k) 0x0010
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#define CONFIG_SYS_FPGA_DONE(k) 0x0010
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