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ARM: add an "eet" variant of the imx31_phycore board
The "eet" variant of the imx31_phycore board has an OLED display, using a s6e63d6 display controller on the first SPI interface, using GPIO57 as a chip-select for it. With this configuration you can display 256 colour BMP images in 16-bit RGB (RGB565) LCD mode. Signed-off-by: Guennadi Liakhovetski <lg@denx.de> Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
This commit is contained in:
Guennadi Liakhovetski
Anatolij Gustschin
parent
0c99f6ab31
commit
a2bb7105a7
4 changed files with 101 additions and 1 deletions
6
Makefile
6
Makefile
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@ -3029,8 +3029,12 @@ apollon_config : unconfig
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imx31_litekit_config : unconfig
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@$(MKCONFIG) $(@:_config=) arm arm1136 imx31_litekit NULL mx31
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imx31_phycore_eet_config \
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imx31_phycore_config : unconfig
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@$(MKCONFIG) $(@:_config=) arm arm1136 imx31_phycore NULL mx31
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@if [ -n "$(findstring _eet_,$@)" ]; then \
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echo "#define CONFIG_IMX31_PHYCORE_EET" >> $(obj)include/config.h; \
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fi
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@$(MKCONFIG) -a imx31_phycore arm arm1136 imx31_phycore NULL mx31
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mx31ads_config : unconfig
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@$(MKCONFIG) $(@:_config=) arm arm1136 mx31ads freescale mx31
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@ -23,6 +23,7 @@
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#include <common.h>
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#include <s6e63d6.h>
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#include <asm/arch/mx31.h>
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#include <asm/arch/mx31-regs.h>
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@ -66,6 +67,62 @@ int board_init (void)
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return 0;
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}
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#ifdef BOARD_LATE_INIT
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int board_late_init(void)
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{
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#ifdef CONFIG_S6E63D6
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struct s6e63d6 data = {
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/*
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* See comment in mxc_spi.c::decode_cs() for .cs field format.
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* We use GPIO 57 as a chipselect for the S6E63D6 and chipselect
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* 2 of the SPI controller #1, since it is unused.
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*/
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.cs = 2 | (57 << 8),
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.bus = 0,
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.id = 0,
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};
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int ret;
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/* SPI1 */
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mx31_gpio_mux(MUX_CSPI1_SCLK__CSPI1_CLK);
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mx31_gpio_mux(MUX_CSPI1_SPI_RDY__CSPI1_DATAREADY_B);
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mx31_gpio_mux(MUX_CSPI1_MOSI__CSPI1_MOSI);
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mx31_gpio_mux(MUX_CSPI1_MISO__CSPI1_MISO);
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mx31_gpio_mux(MUX_CSPI1_SS0__CSPI1_SS0_B);
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mx31_gpio_mux(MUX_CSPI1_SS1__CSPI1_SS1_B);
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mx31_gpio_mux(MUX_CSPI1_SS2__CSPI1_SS2_B);
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/* start SPI1 clock */
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__REG(CCM_CGR2) = __REG(CCM_CGR2) | (3 << 2);
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/* GPIO 57 */
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/* sw_mux_ctl_key_col4_key_col5_key_col6_key_col7 */
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mx31_gpio_mux(IOMUX_MODE(0x63, MUX_CTL_GPIO));
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/* SPI1 CS2 is free */
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ret = s6e63d6_init(&data);
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if (ret)
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return ret;
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/*
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* This is a "magic" sequence to initialise a C0240QGLA / C0283QGLC
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* OLED display connected to a S6E63D6 SPI display controller in the
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* 18 bit RGB mode
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*/
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s6e63d6_index(&data, 2);
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s6e63d6_param(&data, 0x0182);
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s6e63d6_index(&data, 3);
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s6e63d6_param(&data, 0x8130);
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s6e63d6_index(&data, 0x10);
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s6e63d6_param(&data, 0x0000);
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s6e63d6_index(&data, 5);
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s6e63d6_param(&data, 0x0001);
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s6e63d6_index(&data, 0x22);
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#endif
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return 0;
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}
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#endif
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int checkboard (void)
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{
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printf("Board: Phytec phyCore i.MX31\n");
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@ -134,7 +134,14 @@
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#define MUX_CTL_CSPI2_SS0 0x85
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#define MUX_CTL_CSPI2_SS1 0x86
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#define MUX_CTL_CSPI2_SS2 0x87
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#define MUX_CTL_CSPI1_SS2 0x88
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#define MUX_CTL_CSPI1_SCLK 0x89
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#define MUX_CTL_CSPI1_SPI_RDY 0x8a
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#define MUX_CTL_CSPI2_MOSI 0x8b
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#define MUX_CTL_CSPI1_MOSI 0x8c
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#define MUX_CTL_CSPI1_MISO 0x8d
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#define MUX_CTL_CSPI1_SS0 0x8e
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#define MUX_CTL_CSPI1_SS1 0x8f
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/*
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* Helper macros for the MUX_[contact name]__[pin function] macros
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@ -160,6 +167,15 @@
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IOMUX_MODE(MUX_CTL_CSPI2_SPI_RDY, MUX_CTL_FUNC)
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#define MUX_CSPI2_SCLK__CSPI2_CLK IOMUX_MODE(MUX_CTL_CSPI2_SCLK, MUX_CTL_FUNC)
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#define MUX_CSPI1_SS0__CSPI1_SS0_B IOMUX_MODE(MUX_CTL_CSPI1_SS0, MUX_CTL_FUNC)
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#define MUX_CSPI1_SS1__CSPI1_SS1_B IOMUX_MODE(MUX_CTL_CSPI1_SS1, MUX_CTL_FUNC)
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#define MUX_CSPI1_SS2__CSPI1_SS2_B IOMUX_MODE(MUX_CTL_CSPI1_SS2, MUX_CTL_FUNC)
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#define MUX_CSPI1_MOSI__CSPI1_MOSI IOMUX_MODE(MUX_CTL_CSPI1_MOSI, MUX_CTL_FUNC)
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#define MUX_CSPI1_MISO__CSPI1_MISO IOMUX_MODE(MUX_CTL_CSPI1_MISO, MUX_CTL_FUNC)
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#define MUX_CSPI1_SPI_RDY__CSPI1_DATAREADY_B \
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IOMUX_MODE(MUX_CTL_CSPI1_SPI_RDY, MUX_CTL_FUNC)
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#define MUX_CSPI1_SCLK__CSPI1_CLK IOMUX_MODE(MUX_CTL_CSPI1_SCLK, MUX_CTL_FUNC)
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#define MUX_CSPI2_MOSI__I2C2_SCL IOMUX_MODE(MUX_CTL_CSPI2_MOSI, MUX_CTL_ALT1)
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#define MUX_CSPI2_MISO__I2C2_SDA IOMUX_MODE(MUX_CTL_CSPI2_MISO, MUX_CTL_ALT1)
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@ -178,4 +178,27 @@
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#undef CONFIG_JFFS2_CMDLINE
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#define CONFIG_JFFS2_DEV "nor0"
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/* EET platform additions */
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#ifdef CONFIG_IMX31_PHYCORE_EET
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#define BOARD_LATE_INIT
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#define CONFIG_MX31_GPIO 1
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#define CONFIG_HARD_SPI 1
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#define CONFIG_MXC_SPI 1
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#define CONFIG_CMD_SPI
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#define CONFIG_S6E63D6 1
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#define CONFIG_LCD 1
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#define CONFIG_VIDEO_MX3 1
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#define CONFIG_SYS_WHITE_ON_BLACK 1
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#define LCD_BPP LCD_COLOR8
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#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE 1
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#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
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#define CONFIG_SPLASH_SCREEN 1
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#define CONFIG_CMD_BMP 1
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#endif
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#endif /* __CONFIG_H */
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