mirror of
https://github.com/Fishwaldo/u-boot.git
synced 2025-03-18 13:11:31 +00:00
ARM: add an "eet" variant of the imx31_phycore board
The "eet" variant of the imx31_phycore board has an OLED display, using a s6e63d6 display controller on the first SPI interface, using GPIO57 as a chip-select for it. With this configuration you can display 256 colour BMP images in 16-bit RGB (RGB565) LCD mode. Signed-off-by: Guennadi Liakhovetski <lg@denx.de> Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
This commit is contained in:
Guennadi Liakhovetski
Anatolij Gustschin
parent
0c99f6ab31
commit
a2bb7105a7
4 changed files with 101 additions and 1 deletions
6
Makefile
6
Makefile
|
|
@ -3029,8 +3029,12 @@ apollon_config : unconfig
|
|||
imx31_litekit_config : unconfig
|
||||
@$(MKCONFIG) $(@:_config=) arm arm1136 imx31_litekit NULL mx31
|
||||
|
||||
imx31_phycore_eet_config \
|
||||
imx31_phycore_config : unconfig
|
||||
@$(MKCONFIG) $(@:_config=) arm arm1136 imx31_phycore NULL mx31
|
||||
@if [ -n "$(findstring _eet_,$@)" ]; then \
|
||||
echo "#define CONFIG_IMX31_PHYCORE_EET" >> $(obj)include/config.h; \
|
||||
fi
|
||||
@$(MKCONFIG) -a imx31_phycore arm arm1136 imx31_phycore NULL mx31
|
||||
|
||||
mx31ads_config : unconfig
|
||||
@$(MKCONFIG) $(@:_config=) arm arm1136 mx31ads freescale mx31
|
||||
|
|
|
|||
|
|
@ -23,6 +23,7 @@
|
|||
|
||||
|
||||
#include <common.h>
|
||||
#include <s6e63d6.h>
|
||||
#include <asm/arch/mx31.h>
|
||||
#include <asm/arch/mx31-regs.h>
|
||||
|
||||
|
|
@ -66,6 +67,62 @@ int board_init (void)
|
|||
return 0;
|
||||
}
|
||||
|
||||
#ifdef BOARD_LATE_INIT
|
||||
int board_late_init(void)
|
||||
{
|
||||
#ifdef CONFIG_S6E63D6
|
||||
struct s6e63d6 data = {
|
||||
/*
|
||||
* See comment in mxc_spi.c::decode_cs() for .cs field format.
|
||||
* We use GPIO 57 as a chipselect for the S6E63D6 and chipselect
|
||||
* 2 of the SPI controller #1, since it is unused.
|
||||
*/
|
||||
.cs = 2 | (57 << 8),
|
||||
.bus = 0,
|
||||
.id = 0,
|
||||
};
|
||||
int ret;
|
||||
|
||||
/* SPI1 */
|
||||
mx31_gpio_mux(MUX_CSPI1_SCLK__CSPI1_CLK);
|
||||
mx31_gpio_mux(MUX_CSPI1_SPI_RDY__CSPI1_DATAREADY_B);
|
||||
mx31_gpio_mux(MUX_CSPI1_MOSI__CSPI1_MOSI);
|
||||
mx31_gpio_mux(MUX_CSPI1_MISO__CSPI1_MISO);
|
||||
mx31_gpio_mux(MUX_CSPI1_SS0__CSPI1_SS0_B);
|
||||
mx31_gpio_mux(MUX_CSPI1_SS1__CSPI1_SS1_B);
|
||||
mx31_gpio_mux(MUX_CSPI1_SS2__CSPI1_SS2_B);
|
||||
|
||||
/* start SPI1 clock */
|
||||
__REG(CCM_CGR2) = __REG(CCM_CGR2) | (3 << 2);
|
||||
|
||||
/* GPIO 57 */
|
||||
/* sw_mux_ctl_key_col4_key_col5_key_col6_key_col7 */
|
||||
mx31_gpio_mux(IOMUX_MODE(0x63, MUX_CTL_GPIO));
|
||||
|
||||
/* SPI1 CS2 is free */
|
||||
ret = s6e63d6_init(&data);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/*
|
||||
* This is a "magic" sequence to initialise a C0240QGLA / C0283QGLC
|
||||
* OLED display connected to a S6E63D6 SPI display controller in the
|
||||
* 18 bit RGB mode
|
||||
*/
|
||||
s6e63d6_index(&data, 2);
|
||||
s6e63d6_param(&data, 0x0182);
|
||||
s6e63d6_index(&data, 3);
|
||||
s6e63d6_param(&data, 0x8130);
|
||||
s6e63d6_index(&data, 0x10);
|
||||
s6e63d6_param(&data, 0x0000);
|
||||
s6e63d6_index(&data, 5);
|
||||
s6e63d6_param(&data, 0x0001);
|
||||
s6e63d6_index(&data, 0x22);
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
int checkboard (void)
|
||||
{
|
||||
printf("Board: Phytec phyCore i.MX31\n");
|
||||
|
|
|
|||
|
|
@ -134,7 +134,14 @@
|
|||
#define MUX_CTL_CSPI2_SS0 0x85
|
||||
#define MUX_CTL_CSPI2_SS1 0x86
|
||||
#define MUX_CTL_CSPI2_SS2 0x87
|
||||
#define MUX_CTL_CSPI1_SS2 0x88
|
||||
#define MUX_CTL_CSPI1_SCLK 0x89
|
||||
#define MUX_CTL_CSPI1_SPI_RDY 0x8a
|
||||
#define MUX_CTL_CSPI2_MOSI 0x8b
|
||||
#define MUX_CTL_CSPI1_MOSI 0x8c
|
||||
#define MUX_CTL_CSPI1_MISO 0x8d
|
||||
#define MUX_CTL_CSPI1_SS0 0x8e
|
||||
#define MUX_CTL_CSPI1_SS1 0x8f
|
||||
|
||||
/*
|
||||
* Helper macros for the MUX_[contact name]__[pin function] macros
|
||||
|
|
@ -160,6 +167,15 @@
|
|||
IOMUX_MODE(MUX_CTL_CSPI2_SPI_RDY, MUX_CTL_FUNC)
|
||||
#define MUX_CSPI2_SCLK__CSPI2_CLK IOMUX_MODE(MUX_CTL_CSPI2_SCLK, MUX_CTL_FUNC)
|
||||
|
||||
#define MUX_CSPI1_SS0__CSPI1_SS0_B IOMUX_MODE(MUX_CTL_CSPI1_SS0, MUX_CTL_FUNC)
|
||||
#define MUX_CSPI1_SS1__CSPI1_SS1_B IOMUX_MODE(MUX_CTL_CSPI1_SS1, MUX_CTL_FUNC)
|
||||
#define MUX_CSPI1_SS2__CSPI1_SS2_B IOMUX_MODE(MUX_CTL_CSPI1_SS2, MUX_CTL_FUNC)
|
||||
#define MUX_CSPI1_MOSI__CSPI1_MOSI IOMUX_MODE(MUX_CTL_CSPI1_MOSI, MUX_CTL_FUNC)
|
||||
#define MUX_CSPI1_MISO__CSPI1_MISO IOMUX_MODE(MUX_CTL_CSPI1_MISO, MUX_CTL_FUNC)
|
||||
#define MUX_CSPI1_SPI_RDY__CSPI1_DATAREADY_B \
|
||||
IOMUX_MODE(MUX_CTL_CSPI1_SPI_RDY, MUX_CTL_FUNC)
|
||||
#define MUX_CSPI1_SCLK__CSPI1_CLK IOMUX_MODE(MUX_CTL_CSPI1_SCLK, MUX_CTL_FUNC)
|
||||
|
||||
#define MUX_CSPI2_MOSI__I2C2_SCL IOMUX_MODE(MUX_CTL_CSPI2_MOSI, MUX_CTL_ALT1)
|
||||
#define MUX_CSPI2_MISO__I2C2_SDA IOMUX_MODE(MUX_CTL_CSPI2_MISO, MUX_CTL_ALT1)
|
||||
|
||||
|
|
|
|||
|
|
@ -178,4 +178,27 @@
|
|||
#undef CONFIG_JFFS2_CMDLINE
|
||||
#define CONFIG_JFFS2_DEV "nor0"
|
||||
|
||||
/* EET platform additions */
|
||||
#ifdef CONFIG_IMX31_PHYCORE_EET
|
||||
#define BOARD_LATE_INIT
|
||||
|
||||
#define CONFIG_MX31_GPIO 1
|
||||
|
||||
#define CONFIG_HARD_SPI 1
|
||||
#define CONFIG_MXC_SPI 1
|
||||
#define CONFIG_CMD_SPI
|
||||
|
||||
#define CONFIG_S6E63D6 1
|
||||
|
||||
#define CONFIG_LCD 1
|
||||
#define CONFIG_VIDEO_MX3 1
|
||||
#define CONFIG_SYS_WHITE_ON_BLACK 1
|
||||
#define LCD_BPP LCD_COLOR8
|
||||
#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE 1
|
||||
#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
|
||||
|
||||
#define CONFIG_SPLASH_SCREEN 1
|
||||
#define CONFIG_CMD_BMP 1
|
||||
#endif
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue