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ppc4xx: Update lwmon5 board support
This patch includes the following changes for the lwmon5 board support: - Enable cache in SDRAM - Use common EHCI driver instead of the PPC4xx specific OHCI driver This can be done since only high-speed devices are connected. - Remove cached TLB entry again after ECC setup - Use correct define for cache enabling (CONFIG_4xx_DCACHE instead of CONFIG_SYS_ENABLE_SDRAM_CACHE) - Enable FIT image support Signed-off-by: Stefan Roese <sr@denx.de>
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2 changed files with 32 additions and 12 deletions
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@ -45,10 +45,10 @@
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* memory.
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*
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* If at some time this restriction doesn't apply anymore, just define
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* CONFIG_SYS_ENABLE_SDRAM_CACHE in the board config file and this code should setup
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* CONFIG_4xx_DCACHE in the board config file and this code should setup
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* everything correctly.
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*/
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#ifdef CONFIG_SYS_ENABLE_SDRAM_CACHE
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#ifdef CONFIG_4xx_DCACHE
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#define MY_TLB_WORD2_I_ENABLE 0 /* enable caching on SDRAM */
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#else
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#define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on SDRAM */
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@ -220,18 +220,32 @@ phys_size_t initdram (int board_type)
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program_tlb(0, CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MBYTES_SDRAM << 20,
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MY_TLB_WORD2_I_ENABLE);
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#if defined(CONFIG_DDR_ECC)
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#if defined(CONFIG_4xx_DCACHE)
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/*
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* If ECC is enabled, initialize the parity bits.
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*/
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program_ecc(0, CONFIG_SYS_MBYTES_SDRAM << 20, 0);
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#else /* CONFIG_4xx_DCACHE */
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/*
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* Setup 2nd TLB with same physical address but different virtual address
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* with cache enabled. This is done for fast ECC generation.
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*/
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program_tlb(0, CONFIG_SYS_DDR_CACHED_ADDR, CONFIG_SYS_MBYTES_SDRAM << 20, 0);
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#ifdef CONFIG_DDR_ECC
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/*
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* If ECC is enabled, initialize the parity bits.
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*/
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program_ecc(CONFIG_SYS_DDR_CACHED_ADDR, CONFIG_SYS_MBYTES_SDRAM << 20, 0);
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#endif
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/*
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* Now after initialization (auto-calibration and ECC generation)
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* remove the TLB entries with caches enabled and program again with
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* desired cache functionality
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*/
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remove_tlb(CONFIG_SYS_DDR_CACHED_ADDR, CONFIG_SYS_MBYTES_SDRAM << 20);
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#endif /* CONFIG_4xx_DCACHE */
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#endif /* CONFIG_DDR_ECC */
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/*
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* Clear possible errors resulting from data-eye-search.
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@ -43,6 +43,8 @@
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#define CONFIG_SYS_CLK_FREQ 33300000 /* external freq to pll */
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#define CONFIG_4xx_DCACHE /* enable cache in SDRAM */
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#define CONFIG_BOARD_EARLY_INIT_F /* Call board_early_init_f */
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#define CONFIG_BOARD_EARLY_INIT_R /* Call board_early_init_r */
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#define CONFIG_BOARD_POSTCLK_INIT /* Call board_postclk_init */
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@ -321,6 +323,8 @@
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/* Update size in "reg" property of NOR FLASH device tree nodes */
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#define CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
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#define CONFIG_FIT /* enable FIT image support */
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#define CONFIG_POST_KEY_MAGIC "3C+3E" /* press F3 + F5 keys to force POST */
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#define CONFIG_PREBOOT "setenv bootdelay 15"
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@ -393,16 +397,18 @@
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#define CONFIG_VIDEO_SW_CURSOR
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#define CONFIG_SPLASH_SCREEN
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/* USB */
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#ifdef CONFIG_440EPX
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#define CONFIG_USB_OHCI
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/*
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* USB/EHCI
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*/
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#define CONFIG_USB_EHCI /* Enable EHCI USB support */
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#define CONFIG_USB_EHCI_PPC4XX /* on PPC4xx platform */
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#define CONFIG_SYS_PPC4XX_USB_ADDR 0xe0000300
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#define CONFIG_EHCI_DCACHE /* with dcache handling support */
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#define CONFIG_EHCI_MMIO_BIG_ENDIAN
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#define CONFIG_EHCI_DESC_BIG_ENDIAN
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#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* re-init HCD after CMD_RESET */
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#define CONFIG_USB_STORAGE
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/* Comment this out to enable USB 1.1 device */
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#define USB_2_0_DEVICE
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#endif /* CONFIG_440EPX */
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/* Partitions */
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#define CONFIG_MAC_PARTITION
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#define CONFIG_DOS_PARTITION
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