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MIPS: sync processor and register definitions with linux-4.4

Browse source 
Update definitions for processor, registers as well as assemby
macros.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
This commit is contained in:
Daniel Schwierzeck 2016-01-12 21:48:26 +01:00
parent 23ff8633fd
commit a3ab2ae7f6
8 changed files with 1324 additions and 666 deletions
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126
arch/mips/include/asm/asm.h
View file

@ -1,8 +1,4 @@
/* /*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1995, 1996, 1997, 1999, 2001 by Ralf Baechle * Copyright (C) 1995, 1996, 1997, 1999, 2001 by Ralf Baechle
* Copyright (C) 1999 by Silicon Graphics, Inc. * Copyright (C) 1999 by Silicon Graphics, Inc.
* Copyright (C) 2001 MIPS Technologies, Inc. * Copyright (C) 2001 MIPS Technologies, Inc.
@ -13,6 +9,8 @@
* Some of the routines below contain useless nops that will be optimized * Some of the routines below contain useless nops that will be optimized
* away by gas in -O mode. These nops are however required to fill delay * away by gas in -O mode. These nops are however required to fill delay
* slots in noreorder mode. * slots in noreorder mode.
*
* SPDX-License-Identifier: GPL-2.0
*/ */
#ifndef __ASM_ASM_H #ifndef __ASM_ASM_H
#define __ASM_ASM_H #define __ASM_ASM_H
@ -33,58 +31,58 @@
* Not used for the kernel but here seems to be the right place. * Not used for the kernel but here seems to be the right place.
*/ */
#ifdef __PIC__ #ifdef __PIC__
#define CPRESTORE(register) \ #define CPRESTORE(register) \
.cprestore register .cprestore register
#define CPADD(register) \ #define CPADD(register) \
.cpadd register .cpadd register
#define CPLOAD(register) \ #define CPLOAD(register) \
.cpload register .cpload register
#else #else
#define CPRESTORE(register) #define CPRESTORE(register)
#define CPADD(register) #define CPADD(register)
#define CPLOAD(register) #define CPLOAD(register)
#endif #endif
#define ENTRY(symbol) \ #define ENTRY(symbol) \
.globl symbol; \ .globl symbol; \
.type symbol, @function; \ .type symbol, @function; \
.ent symbol, 0; \ .ent symbol, 0; \
symbol: symbol:
/* /*
* LEAF - declare leaf routine * LEAF - declare leaf routine
*/ */
#define LEAF(symbol) \ #define LEAF(symbol) \
.globl symbol; \ .globl symbol; \
.align 2; \ .align 2; \
.type symbol, @function; \ .type symbol, @function; \
.ent symbol, 0; \ .ent symbol, 0; \
.section .text.symbol, "x"; \ .section .text.symbol, "x"; \
symbol: .frame sp, 0, ra symbol: .frame sp, 0, ra
/* /*
* NESTED - declare nested routine entry point * NESTED - declare nested routine entry point
*/ */
#define NESTED(symbol, framesize, rpc) \ #define NESTED(symbol, framesize, rpc) \
.globl symbol; \ .globl symbol; \
.align 2; \ .align 2; \
.type symbol, @function; \ .type symbol, @function; \
.ent symbol, 0; \ .ent symbol, 0; \
.section .text.symbol, "x"; \ .section .text.symbol, "x"; \
symbol: .frame sp, framesize, rpc symbol: .frame sp, framesize, rpc
/* /*
* END - mark end of function * END - mark end of function
*/ */
#define END(function) \ #define END(function) \
.end function; \ .end function; \
.size function, .-function .size function, .-function
/* /*
* EXPORT - export definition of symbol * EXPORT - export definition of symbol
*/ */
#define EXPORT(symbol) \ #define EXPORT(symbol) \
.globl symbol; \ .globl symbol; \
symbol: symbol:
/* /*
@ -98,16 +96,16 @@ symbol:
/* /*
* ABS - export absolute symbol * ABS - export absolute symbol
*/ */
#define ABS(symbol,value) \ #define ABS(symbol,value) \
.globl symbol; \ .globl symbol; \
symbol = value symbol = value
#define PANIC(msg) \ #define PANIC(msg) \
.set push; \ .set push; \
.set reorder; \ .set reorder; \
PTR_LA a0, 8f; \ PTR_LA a0, 8f; \
jal panic; \ jal panic; \
9: b 9b; \ 9: b 9b; \
.set pop; \ .set pop; \
TEXT(msg) TEXT(msg)
@ -115,31 +113,31 @@ symbol = value
* Print formatted string * Print formatted string
*/ */
#ifdef CONFIG_PRINTK #ifdef CONFIG_PRINTK
#define PRINT(string) \ #define PRINT(string) \
.set push; \ .set push; \
.set reorder; \ .set reorder; \
PTR_LA a0, 8f; \ PTR_LA a0, 8f; \
jal printk; \ jal printk; \
.set pop; \ .set pop; \
TEXT(string) TEXT(string)
#else #else
#define PRINT(string) #define PRINT(string)
#endif #endif
#define TEXT(msg) \ #define TEXT(msg) \
.pushsection .data; \ .pushsection .data; \
8: .asciiz msg; \ 8: .asciiz msg; \
.popsection; .popsection;
/* /*
* Build text tables * Build text tables
*/ */
#define TTABLE(string) \ #define TTABLE(string) \
.pushsection .text; \ .pushsection .text; \
.word 1f; \ .word 1f; \
.popsection \ .popsection \
.pushsection .data; \ .pushsection .data; \
1: .asciiz string; \ 1: .asciiz string; \
.popsection .popsection
/* /*
@ -151,21 +149,29 @@ symbol = value
*/ */
#ifdef CONFIG_CPU_HAS_PREFETCH #ifdef CONFIG_CPU_HAS_PREFETCH
#define PREF(hint,addr) \ #define PREF(hint, addr) \
.set push; \ .set push; \
.set mips4; \ .set arch=r5000; \
pref hint, addr; \ pref hint, addr; \
.set pop .set pop
#define PREFX(hint,addr) \ #define PREFE(hint, addr) \
.set push; \ .set push; \
.set mips4; \ .set mips0; \
.set eva; \
prefe hint, addr; \
.set pop
#define PREFX(hint, addr) \
.set push; \
.set arch=r5000; \
prefx hint, addr; \ prefx hint, addr; \
.set pop .set pop
#else /* !CONFIG_CPU_HAS_PREFETCH */ #else /* !CONFIG_CPU_HAS_PREFETCH */
#define PREF(hint, addr) #define PREF(hint, addr)
#define PREFE(hint, addr)
#define PREFX(hint, addr) #define PREFX(hint, addr)
#endif /* !CONFIG_CPU_HAS_PREFETCH */ #endif /* !CONFIG_CPU_HAS_PREFETCH */
@ -174,42 +180,42 @@ symbol = value
* MIPS ISA IV/V movn/movz instructions and equivalents for older CPUs. * MIPS ISA IV/V movn/movz instructions and equivalents for older CPUs.
*/ */
#if (_MIPS_ISA == _MIPS_ISA_MIPS1) #if (_MIPS_ISA == _MIPS_ISA_MIPS1)
#define MOVN(rd, rs, rt) \ #define MOVN(rd, rs, rt) \
.set push; \ .set push; \
.set reorder; \ .set reorder; \
beqz rt, 9f; \ beqz rt, 9f; \
move rd, rs; \ move rd, rs; \
.set pop; \ .set pop; \
9: 9:
#define MOVZ(rd, rs, rt) \ #define MOVZ(rd, rs, rt) \
.set push; \ .set push; \
.set reorder; \ .set reorder; \
bnez rt, 9f; \ bnez rt, 9f; \
move rd, rs; \ move rd, rs; \
.set pop; \ .set pop; \
9: 9:
#endif /* _MIPS_ISA == _MIPS_ISA_MIPS1 */ #endif /* _MIPS_ISA == _MIPS_ISA_MIPS1 */
#if (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3) #if (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3)
#define MOVN(rd, rs, rt) \ #define MOVN(rd, rs, rt) \
.set push; \ .set push; \
.set noreorder; \ .set noreorder; \
bnezl rt, 9f; \ bnezl rt, 9f; \
move rd, rs; \ move rd, rs; \
.set pop; \ .set pop; \
9: 9:
#define MOVZ(rd, rs, rt) \ #define MOVZ(rd, rs, rt) \
.set push; \ .set push; \
.set noreorder; \ .set noreorder; \
beqzl rt, 9f; \ beqzl rt, 9f; \
move rd, rs; \ move rd, rs; \
.set pop; \ .set pop; \
9: 9:
#endif /* (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3) */ #endif /* (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3) */
#if (_MIPS_ISA == _MIPS_ISA_MIPS4 ) || (_MIPS_ISA == _MIPS_ISA_MIPS5) || \ #if (_MIPS_ISA == _MIPS_ISA_MIPS4 ) || (_MIPS_ISA == _MIPS_ISA_MIPS5) || \
(_MIPS_ISA == _MIPS_ISA_MIPS32) || (_MIPS_ISA == _MIPS_ISA_MIPS64) (_MIPS_ISA == _MIPS_ISA_MIPS32) || (_MIPS_ISA == _MIPS_ISA_MIPS64)
#define MOVN(rd, rs, rt) \ #define MOVN(rd, rs, rt) \
movn rd, rs, rt movn rd, rs, rt
#define MOVZ(rd, rs, rt) \ #define MOVZ(rd, rs, rt) \
movz rd, rs, rt movz rd, rs, rt
#endif /* MIPS IV, MIPS V, MIPS32 or MIPS64 */ #endif /* MIPS IV, MIPS V, MIPS32 or MIPS64 */
@ -304,6 +310,7 @@ symbol = value
#define LONG_SUBU subu #define LONG_SUBU subu
#define LONG_L lw #define LONG_L lw
#define LONG_S sw #define LONG_S sw
#define LONG_SP swp
#define LONG_SLL sll #define LONG_SLL sll
#define LONG_SLLV sllv #define LONG_SLLV sllv
#define LONG_SRL srl #define LONG_SRL srl
@ -326,6 +333,7 @@ symbol = value
#define LONG_SUBU dsubu #define LONG_SUBU dsubu
#define LONG_L ld #define LONG_L ld
#define LONG_S sd #define LONG_S sd
#define LONG_SP sdp
#define LONG_SLL dsll #define LONG_SLL dsll
#define LONG_SLLV dsllv #define LONG_SLLV dsllv
#define LONG_SRL dsrl #define LONG_SRL dsrl

6
arch/mips/include/asm/isadep.h
View file

@ -4,6 +4,8 @@
* of Coprocessor 0 registers. * of Coprocessor 0 registers.
* *
* Copyright (c) 1998 Harald Koerfgen * Copyright (c) 1998 Harald Koerfgen
*
* SPDX-License-Identifier: GPL-2.0
*/ */
#ifndef __ASM_ISADEP_H #ifndef __ASM_ISADEP_H
@ -18,7 +20,7 @@
* kernel or user mode? (CP0_STATUS) * kernel or user mode? (CP0_STATUS)
*/ */
#define KU_MASK 0x08 #define KU_MASK 0x08
#define KU_USER 0x08 #define KU_USER 0x08
#define KU_KERN 0x00 #define KU_KERN 0x00
#else #else
@ -26,7 +28,7 @@
* kernel or user mode? * kernel or user mode?
*/ */
#define KU_MASK 0x18 #define KU_MASK 0x18
#define KU_USER 0x10 #define KU_USER 0x10
#define KU_KERN 0x00 #define KU_KERN 0x00
#endif #endif

1721
arch/mips/include/asm/mipsregs.h
View file

File diff suppressed because it is too large Load diff

6
arch/mips/include/asm/processor.h
View file

@ -1,12 +1,10 @@
/* /*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1994 Waldorf GMBH * Copyright (C) 1994 Waldorf GMBH
* Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003 Ralf Baechle * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003 Ralf Baechle
* Copyright (C) 1996 Paul M. Antoine * Copyright (C) 1996 Paul M. Antoine
* Copyright (C) 1999, 2000 Silicon Graphics, Inc. * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
*
* SPDX-License-Identifier: GPL-2.0
*/ */
#ifndef _ASM_PROCESSOR_H #ifndef _ASM_PROCESSOR_H
#define _ASM_PROCESSOR_H #define _ASM_PROCESSOR_H

99
arch/mips/include/asm/ptrace.h
View file

@ -1,35 +1,27 @@
/* /*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1994, 95, 96, 97, 98, 99, 2000 by Ralf Baechle * Copyright (C) 1994, 95, 96, 97, 98, 99, 2000 by Ralf Baechle
* Copyright (C) 1999, 2000 Silicon Graphics, Inc. * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
*
* SPDX-License-Identifier: GPL-2.0
*/ */
#ifndef _ASM_PTRACE_H #ifndef _ASM_PTRACE_H
#define _ASM_PTRACE_H #define _ASM_PTRACE_H
/* 0 - 31 are integer registers, 32 - 63 are fp registers. */ #include <linux/compiler.h>
#define FPR_BASE 32 #include <linux/types.h>
#define PC 64 #include <asm/isadep.h>
#define CAUSE 65
#define BADVADDR 66
#define MMHI 67
#define MMLO 68
#define FPC_CSR 69
#define FPC_EIR 70
#define DSP_BASE 71 /* 3 more hi / lo register pairs */
#define DSP_CONTROL 77
#define ACX 78
/* /*
* This struct defines the way the registers are stored on the stack during a * This struct defines the way the registers are stored on the stack during a
* system call/exception. As usual the registers k0/k1 aren't being saved. * system call/exception. As usual the registers k0/k1 aren't being saved.
*
* If you add a register here, also add it to regoffset_table[] in
* arch/mips/kernel/ptrace.c.
*/ */
struct pt_regs { struct pt_regs {
#ifdef CONFIG_32BIT #ifdef CONFIG_32BIT
/* Pad bytes for argument save space on the stack. */ /* Pad bytes for argument save space on the stack. */
unsigned long pad0[6]; unsigned long pad0[8];
#endif #endif
/* Saved main processor registers. */ /* Saved main processor registers. */
@ -45,34 +37,50 @@ struct pt_regs {
unsigned long cp0_badvaddr; unsigned long cp0_badvaddr;
unsigned long cp0_cause; unsigned long cp0_cause;
unsigned long cp0_epc; unsigned long cp0_epc;
#ifdef CONFIG_MIPS_MT_SMTC #ifdef CONFIG_CPU_CAVIUM_OCTEON
unsigned long cp0_tcstatus; unsigned long long mpl[6]; /* MTM{0-5} */
#endif /* CONFIG_MIPS_MT_SMTC */ unsigned long long mtp[6]; /* MTP{0-5} */
} __attribute__ ((aligned (8))); #endif
unsigned long __last[0];
} __aligned(8);
/* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */ static inline unsigned long kernel_stack_pointer(struct pt_regs *regs)
#define PTRACE_GETREGS 12 {
#define PTRACE_SETREGS 13 return regs->regs[31];
#define PTRACE_GETFPREGS 14 }
#define PTRACE_SETFPREGS 15
/* #define PTRACE_GETFPXREGS 18 */
/* #define PTRACE_SETFPXREGS 19 */
#define PTRACE_OLDSETOPTIONS 21 /*
* Don't use asm-generic/ptrace.h it defines FP accessors that don't make
* sense on MIPS. We rather want an error if they get invoked.
*/
#define PTRACE_GET_THREAD_AREA 25 static inline void instruction_pointer_set(struct pt_regs *regs,
#define PTRACE_SET_THREAD_AREA 26 unsigned long val)
{
regs->cp0_epc = val;
}
/* Calls to trace a 64bit program from a 32bit program. */ /* Query offset/name of register from its name/offset */
#define PTRACE_PEEKTEXT_3264 0xc0 extern int regs_query_register_offset(const char *name);
#define PTRACE_PEEKDATA_3264 0xc1 #define MAX_REG_OFFSET (offsetof(struct pt_regs, __last))
#define PTRACE_POKETEXT_3264 0xc2
#define PTRACE_POKEDATA_3264 0xc3
#define PTRACE_GET_THREAD_AREA_3264 0xc4
#ifdef __KERNEL__ /**
* regs_get_register() - get register value from its offset
* @regs: pt_regs from which register value is gotten.
* @offset: offset number of the register.
*
* regs_get_register returns the value of a register. The @offset is the
* offset of the register in struct pt_regs address which specified by @regs.
* If @offset is bigger than MAX_REG_OFFSET, this returns 0.
*/
static inline unsigned long regs_get_register(struct pt_regs *regs,
unsigned int offset)
{
if (unlikely(offset > MAX_REG_OFFSET))
return 0;
#include <asm/isadep.h> return *(unsigned long *)((unsigned long)regs + offset);
}
/* /*
* Does the process account for user or for system time? * Does the process account for user or for system time?
@ -82,6 +90,17 @@ struct pt_regs {
#define instruction_pointer(regs) ((regs)->cp0_epc) #define instruction_pointer(regs) ((regs)->cp0_epc)
#define profile_pc(regs) instruction_pointer(regs) #define profile_pc(regs) instruction_pointer(regs)
#endif /* Helpers for working with the user stack pointer */
static inline unsigned long user_stack_pointer(struct pt_regs *regs)
{
return regs->regs[29];
}
static inline void user_stack_pointer_set(struct pt_regs *regs,
unsigned long val)
{
regs->regs[29] = val;
}
#endif /* _ASM_PTRACE_H */ #endif /* _ASM_PTRACE_H */

12
arch/mips/include/asm/regdef.h
View file

@ -1,11 +1,11 @@
/* /*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1985 MIPS Computer Systems, Inc. * Copyright (C) 1985 MIPS Computer Systems, Inc.
* Copyright (C) 1994, 95, 99, 2003 by Ralf Baechle * Copyright (C) 1994, 95, 99, 2003 by Ralf Baechle
* Copyright (C) 1990 - 1992, 1999 Silicon Graphics, Inc. * Copyright (C) 1990 - 1992, 1999 Silicon Graphics, Inc.
* Copyright (C) 2011 Wind River Systems,
* written by Ralf Baechle <ralf@linux-mips.org>
*
* SPDX-License-Identifier: GPL-2.0
*/ */
#ifndef _ASM_REGDEF_H #ifndef _ASM_REGDEF_H
#define _ASM_REGDEF_H #define _ASM_REGDEF_H
@ -30,9 +30,13 @@
#define t2 $10 #define t2 $10
#define t3 $11 #define t3 $11
#define t4 $12 #define t4 $12
#define ta0 $12
#define t5 $13 #define t5 $13
#define ta1 $13
#define t6 $14 #define t6 $14
#define ta2 $14
#define t7 $15 #define t7 $15
#define ta3 $15
#define s0 $16 /* callee saved */ #define s0 $16 /* callee saved */
#define s1 $17 #define s1 $17
#define s2 $18 #define s2 $18

4
arch/mips/lib/cache.c
View file

@ -27,7 +27,7 @@ static inline unsigned long icache_line_size(void)
{ {
unsigned long conf1, il; unsigned long conf1, il;
conf1 = read_c0_config1(); conf1 = read_c0_config1();
il = (conf1 & MIPS_CONF1_IL) >> MIPS_CONF1_IL_SHIFT; il = (conf1 & MIPS_CONF1_IL) >> MIPS_CONF1_IL_SHF;
if (!il) if (!il)
return 0; return 0;
return 2 << il; return 2 << il;
@ -37,7 +37,7 @@ static inline unsigned long dcache_line_size(void)
{ {
unsigned long conf1, dl; unsigned long conf1, dl;
conf1 = read_c0_config1(); conf1 = read_c0_config1();
dl = (conf1 & MIPS_CONF1_DL) >> MIPS_CONF1_DL_SHIFT; dl = (conf1 & MIPS_CONF1_DL) >> MIPS_CONF1_DL_SHF;
if (!dl) if (!dl)
return 0; return 0;
return 2 << dl; return 2 << dl;

16
arch/mips/lib/cache_init.S
View file

@ -54,24 +54,24 @@
mfc0 $1, CP0_CONFIG, 1 mfc0 $1, CP0_CONFIG, 1
/* detect line size */ /* detect line size */
srl \line_sz, $1, \off + MIPS_CONF1_DL_SHIFT - MIPS_CONF1_DA_SHIFT srl \line_sz, $1, \off + MIPS_CONF1_DL_SHF - MIPS_CONF1_DA_SHF
andi \line_sz, \line_sz, (MIPS_CONF1_DL >> MIPS_CONF1_DL_SHIFT) andi \line_sz, \line_sz, (MIPS_CONF1_DL >> MIPS_CONF1_DL_SHF)
move \sz, zero move \sz, zero
beqz \line_sz, 10f beqz \line_sz, 10f
li \sz, 2 li \sz, 2
sllv \line_sz, \sz, \line_sz sllv \line_sz, \sz, \line_sz
/* detect associativity */ /* detect associativity */
srl \sz, $1, \off + MIPS_CONF1_DA_SHIFT - MIPS_CONF1_DA_SHIFT srl \sz, $1, \off + MIPS_CONF1_DA_SHF - MIPS_CONF1_DA_SHF
andi \sz, \sz, (MIPS_CONF1_DA >> MIPS_CONF1_DA_SHIFT) andi \sz, \sz, (MIPS_CONF1_DA >> MIPS_CONF1_DA_SHF)
addi \sz, \sz, 1 addi \sz, \sz, 1
/* sz *= line_sz */ /* sz *= line_sz */
mul \sz, \sz, \line_sz mul \sz, \sz, \line_sz
/* detect log32(sets) */ /* detect log32(sets) */
srl $1, $1, \off + MIPS_CONF1_DS_SHIFT - MIPS_CONF1_DA_SHIFT srl $1, $1, \off + MIPS_CONF1_DS_SHF - MIPS_CONF1_DA_SHF
andi $1, $1, (MIPS_CONF1_DS >> MIPS_CONF1_DS_SHIFT) andi $1, $1, (MIPS_CONF1_DS >> MIPS_CONF1_DS_SHF)
addiu $1, $1, 1 addiu $1, $1, 1
andi $1, $1, 0x7 andi $1, $1, 0x7
@ -103,14 +103,14 @@ LEAF(mips_cache_reset)
li t2, CONFIG_SYS_ICACHE_SIZE li t2, CONFIG_SYS_ICACHE_SIZE
li t8, CONFIG_SYS_CACHELINE_SIZE li t8, CONFIG_SYS_CACHELINE_SIZE
#else #else
l1_info t2, t8, MIPS_CONF1_IA_SHIFT l1_info t2, t8, MIPS_CONF1_IA_SHF
#endif #endif
#ifdef CONFIG_SYS_DCACHE_SIZE #ifdef CONFIG_SYS_DCACHE_SIZE
li t3, CONFIG_SYS_DCACHE_SIZE li t3, CONFIG_SYS_DCACHE_SIZE
li t9, CONFIG_SYS_CACHELINE_SIZE li t9, CONFIG_SYS_CACHELINE_SIZE
#else #else
l1_info t3, t9, MIPS_CONF1_DA_SHIFT l1_info t3, t9, MIPS_CONF1_DA_SHF
#endif #endif
#ifdef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD #ifdef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD