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imx:mx6ul add dram spl configuration and header file
1. Define two structures mx6ul_iomux_ddr_regs and mx6ul_iomux_grp_regs. 2. Add a new function mx6ul_dram_iocfg to configure dram io. 3. Refactor MMDC1 macro, discard "#ifdef CONFIG_MX6SX". Since only mmdc0 channel exists on i.MX6SX/UL, redefine MMDC1 macro support runtime check, but not hardcoding #ifdef macros. 4. Introduce mx6ul-ddr.h, which includes the register address for DRAM IO configuration. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
This commit is contained in:
Peng Fan
Stefano Babic
parent
94bd1d1430
commit
a462c34602
3 changed files with 141 additions and 10 deletions
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@ -71,6 +71,50 @@ void mx6sx_dram_iocfg(unsigned width,
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}
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#endif
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#ifdef CONFIG_MX6UL
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void mx6ul_dram_iocfg(unsigned width,
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const struct mx6ul_iomux_ddr_regs *ddr,
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const struct mx6ul_iomux_grp_regs *grp)
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{
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struct mx6ul_iomux_ddr_regs *mx6_ddr_iomux;
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struct mx6ul_iomux_grp_regs *mx6_grp_iomux;
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mx6_ddr_iomux = (struct mx6ul_iomux_ddr_regs *)MX6UL_IOM_DDR_BASE;
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mx6_grp_iomux = (struct mx6ul_iomux_grp_regs *)MX6UL_IOM_GRP_BASE;
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/* DDR IO TYPE */
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writel(grp->grp_ddr_type, &mx6_grp_iomux->grp_ddr_type);
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writel(grp->grp_ddrpke, &mx6_grp_iomux->grp_ddrpke);
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/* CLOCK */
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writel(ddr->dram_sdclk_0, &mx6_ddr_iomux->dram_sdclk_0);
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/* ADDRESS */
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writel(ddr->dram_cas, &mx6_ddr_iomux->dram_cas);
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writel(ddr->dram_ras, &mx6_ddr_iomux->dram_ras);
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writel(grp->grp_addds, &mx6_grp_iomux->grp_addds);
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/* Control */
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writel(ddr->dram_reset, &mx6_ddr_iomux->dram_reset);
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writel(ddr->dram_sdba2, &mx6_ddr_iomux->dram_sdba2);
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writel(ddr->dram_odt0, &mx6_ddr_iomux->dram_odt0);
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writel(ddr->dram_odt1, &mx6_ddr_iomux->dram_odt1);
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writel(grp->grp_ctlds, &mx6_grp_iomux->grp_ctlds);
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/* Data Strobes */
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writel(grp->grp_ddrmode_ctl, &mx6_grp_iomux->grp_ddrmode_ctl);
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writel(ddr->dram_sdqs0, &mx6_ddr_iomux->dram_sdqs0);
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writel(ddr->dram_sdqs1, &mx6_ddr_iomux->dram_sdqs1);
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/* Data */
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writel(grp->grp_ddrmode, &mx6_grp_iomux->grp_ddrmode);
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writel(grp->grp_b0ds, &mx6_grp_iomux->grp_b0ds);
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writel(grp->grp_b1ds, &mx6_grp_iomux->grp_b1ds);
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writel(ddr->dram_dqm0, &mx6_ddr_iomux->dram_dqm0);
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writel(ddr->dram_dqm1, &mx6_ddr_iomux->dram_dqm1);
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}
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#endif
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#if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6Q) || defined(CONFIG_MX6D)
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/* Configure MX6DQ mmdc iomux */
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void mx6dq_dram_iocfg(unsigned width,
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@ -243,19 +287,17 @@ void mx6sdl_dram_iocfg(unsigned width,
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*/
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#define MR(val, ba, cmd, cs1) \
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((val << 16) | (1 << 15) | (cmd << 4) | (cs1 << 3) | ba)
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#ifdef CONFIG_MX6SX
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#define MMDC1(entry, value) do {} while (0)
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#else
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#define MMDC1(entry, value) do { mmdc1->entry = value; } while (0)
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#endif
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#define MMDC1(entry, value) do { \
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if (!is_cpu_type(MXC_CPU_MX6SX) && !is_cpu_type(MXC_CPU_MX6UL)) \
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mmdc1->entry = value; \
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} while (0)
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void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo,
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const struct mx6_mmdc_calibration *calib,
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const struct mx6_ddr3_cfg *ddr3_cfg)
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{
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volatile struct mmdc_p_regs *mmdc0;
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#ifndef CONFIG_MX6SX
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volatile struct mmdc_p_regs *mmdc1;
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#endif
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u32 val;
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u8 tcke, tcksrx, tcksre, txpdll, taofpd, taonpd, trrd;
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u8 todtlon, taxpd, tanpd, tcwl, txp, tfaw, tcl;
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@ -270,9 +312,8 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo,
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u16 mem_speed = ddr3_cfg->mem_speed;
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mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
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#ifndef CONFIG_MX6SX
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mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
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#endif
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if (!is_cpu_type(MXC_CPU_MX6SX) && !is_cpu_type(MXC_CPU_MX6UL))
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mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
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/* Limit mem_speed for MX6D/MX6Q */
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if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) {
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@ -16,7 +16,11 @@
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#ifdef CONFIG_MX6SX
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#include "mx6sx-ddr.h"
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#else
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#ifdef CONFIG_MX6UL
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#include "mx6ul-ddr.h"
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#else
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#error "Please select cpu"
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#endif /* CONFIG_MX6UL */
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#endif /* CONFIG_MX6SX */
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#endif /* CONFIG_MX6DL or CONFIG_MX6S */
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#endif /* CONFIG_MX6Q */
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@ -62,6 +66,44 @@ struct mmdc_p_regs {
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u32 mpmur0;
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};
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#define MX6UL_IOM_DDR_BASE 0x020e0200
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struct mx6ul_iomux_ddr_regs {
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u32 res1[17];
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u32 dram_dqm0;
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u32 dram_dqm1;
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u32 dram_ras;
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u32 dram_cas;
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u32 dram_cs0;
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u32 dram_cs1;
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u32 dram_sdwe_b;
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u32 dram_odt0;
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u32 dram_odt1;
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u32 dram_sdba0;
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u32 dram_sdba1;
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u32 dram_sdba2;
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u32 dram_sdcke0;
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u32 dram_sdcke1;
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u32 dram_sdclk_0;
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u32 dram_sdqs0;
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u32 dram_sdqs1;
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u32 dram_reset;
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};
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#define MX6UL_IOM_GRP_BASE 0x020e0400
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struct mx6ul_iomux_grp_regs {
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u32 res1[36];
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u32 grp_addds;
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u32 grp_ddrmode_ctl;
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u32 grp_b0ds;
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u32 grp_ddrpk;
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u32 grp_ctlds;
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u32 grp_b1ds;
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u32 grp_ddrhys;
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u32 grp_ddrpke;
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u32 grp_ddrmode;
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u32 grp_ddr_type;
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};
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#define MX6SX_IOM_DDR_BASE 0x020e0200
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struct mx6sx_iomux_ddr_regs {
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u32 res1[59];
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@ -290,6 +332,9 @@ void mx6sdl_dram_iocfg(unsigned width,
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void mx6sx_dram_iocfg(unsigned width,
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const struct mx6sx_iomux_ddr_regs *,
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const struct mx6sx_iomux_grp_regs *);
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void mx6ul_dram_iocfg(unsigned width,
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const struct mx6ul_iomux_ddr_regs *,
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const struct mx6ul_iomux_grp_regs *);
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/* configure mx6 mmdc registers */
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void mx6_dram_cfg(const struct mx6_ddr_sysinfo *,
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45
arch/arm/include/asm/arch-mx6/mx6ul-ddr.h
Normal file
45
arch/arm/include/asm/arch-mx6/mx6ul-ddr.h
Normal file
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@ -0,0 +1,45 @@
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/*
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* Copyright (C) 2015 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __ASM_ARCH_MX6UL_DDR_H__
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#define __ASM_ARCH_MX6UL_DDR_H__
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#ifndef CONFIG_MX6UL
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#error "wrong CPU"
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#endif
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#define MX6_IOM_DRAM_DQM0 0x020e0244
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#define MX6_IOM_DRAM_DQM1 0x020e0248
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#define MX6_IOM_DRAM_RAS 0x020e024c
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#define MX6_IOM_DRAM_CAS 0x020e0250
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#define MX6_IOM_DRAM_CS0 0x020e0254
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#define MX6_IOM_DRAM_CS1 0x020e0258
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#define MX6_IOM_DRAM_SDWE_B 0x020e025c
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#define MX6_IOM_DRAM_SDODT0 0x020e0260
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#define MX6_IOM_DRAM_SDODT1 0x020e0264
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#define MX6_IOM_DRAM_SDBA0 0x020e0268
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#define MX6_IOM_DRAM_SDBA1 0x020e026c
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#define MX6_IOM_DRAM_SDBA2 0x020e0270
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#define MX6_IOM_DRAM_SDCKE0 0x020e0274
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#define MX6_IOM_DRAM_SDCKE1 0x020e0278
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#define MX6_IOM_DRAM_SDCLK_0 0x020e027c
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#define MX6_IOM_DRAM_SDQS0 0x020e0280
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#define MX6_IOM_DRAM_SDQS1 0x020e0284
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#define MX6_IOM_DRAM_RESET 0x020e0288
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#define MX6_IOM_GRP_ADDDS 0x020e0490
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#define MX6_IOM_DDRMODE_CTL 0x020e0494
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#define MX6_IOM_GRP_B0DS 0x020e0498
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#define MX6_IOM_GRP_DDRPK 0x020e049c
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#define MX6_IOM_GRP_CTLDS 0x020e04a0
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#define MX6_IOM_GRP_B1DS 0x020e04a4
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#define MX6_IOM_GRP_DDRHYS 0x020e04a8
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#define MX6_IOM_GRP_DDRPKE 0x020e04ac
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#define MX6_IOM_GRP_DDRMODE 0x020e04b0
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#define MX6_IOM_GRP_DDR_TYPE 0x020e04b4
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#endif /*__ASM_ARCH_MX6SX_DDR_H__ */
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